1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=instcombine -S | FileCheck %s 3 4; Check simplification of 5; (icmp sgt x, -1) & (icmp sgt/sge n, x) --> icmp ugt/uge n, x 6 7define i1 @test_and1(i32 %x, i32 %n) { 8; CHECK-LABEL: @test_and1( 9; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 10; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], [[NN]] 11; CHECK-NEXT: ret i1 [[C]] 12; 13 %nn = and i32 %n, 2147483647 14 %a = icmp sge i32 %x, 0 15 %b = icmp slt i32 %x, %nn 16 %c = and i1 %a, %b 17 ret i1 %c 18} 19 20define i1 @test_and1_logical(i32 %x, i32 %n) { 21; CHECK-LABEL: @test_and1_logical( 22; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 23; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1 24; CHECK-NEXT: [[B:%.*]] = icmp slt i32 [[X]], [[NN]] 25; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false 26; CHECK-NEXT: ret i1 [[C]] 27; 28 %nn = and i32 %n, 2147483647 29 %a = icmp sge i32 %x, 0 30 %b = icmp slt i32 %x, %nn 31 %c = select i1 %a, i1 %b, i1 false 32 ret i1 %c 33} 34 35define i1 @test_and1_sext(i32 %x, i64 %n) { 36; CHECK-LABEL: @test_and1_sext( 37; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 38; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 39; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 40; CHECK-NEXT: [[C:%.*]] = icmp ugt i64 [[NN]], [[X_SEXT]] 41; CHECK-NEXT: ret i1 [[C]] 42; 43 %n_not_negative = icmp sge i64 %n, 0 44 call void @llvm.assume(i1 %n_not_negative) 45 %x_sext = sext i32 %x to i64 46 %a = icmp sge i32 %x, 0 47 %b = icmp slt i64 %x_sext, %n 48 %c = and i1 %a, %b 49 ret i1 %c 50} 51 52define i1 @test_and2(i32 %x, i32 %n) { 53; CHECK-LABEL: @test_and2( 54; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 55; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[X:%.*]], [[NN]] 56; CHECK-NEXT: ret i1 [[C]] 57; 58 %nn = and i32 %n, 2147483647 59 %a = icmp sgt i32 %x, -1 60 %b = icmp sle i32 %x, %nn 61 %c = and i1 %a, %b 62 ret i1 %c 63} 64 65define i1 @test_and2_logical(i32 %x, i32 %n) { 66; CHECK-LABEL: @test_and2_logical( 67; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 68; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1 69; CHECK-NEXT: [[B:%.*]] = icmp sle i32 [[X]], [[NN]] 70; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false 71; CHECK-NEXT: ret i1 [[C]] 72; 73 %nn = and i32 %n, 2147483647 74 %a = icmp sgt i32 %x, -1 75 %b = icmp sle i32 %x, %nn 76 %c = select i1 %a, i1 %b, i1 false 77 ret i1 %c 78} 79 80define i1 @test_and2_sext(i32 %x, i64 %n) { 81; CHECK-LABEL: @test_and2_sext( 82; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 83; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 84; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 85; CHECK-NEXT: [[C:%.*]] = icmp uge i64 [[NN]], [[X_SEXT]] 86; CHECK-NEXT: ret i1 [[C]] 87; 88 %n_not_negative = icmp sge i64 %n, 0 89 call void @llvm.assume(i1 %n_not_negative) 90 %x_sext = sext i32 %x to i64 91 %a = icmp sgt i32 %x, -1 92 %b = icmp sle i64 %x_sext, %n 93 %c = and i1 %a, %b 94 ret i1 %c 95} 96 97define i1 @test_and3(i32 %x, i32 %n) { 98; CHECK-LABEL: @test_and3( 99; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 100; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], [[NN]] 101; CHECK-NEXT: ret i1 [[C]] 102; 103 %nn = and i32 %n, 2147483647 104 %a = icmp sgt i32 %nn, %x 105 %b = icmp sge i32 %x, 0 106 %c = and i1 %a, %b 107 ret i1 %c 108} 109 110define i1 @test_and3_logical(i32 %x, i32 %n) { 111; CHECK-LABEL: @test_and3_logical( 112; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 113; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[X:%.*]], [[NN]] 114; CHECK-NEXT: ret i1 [[C]] 115; 116 %nn = and i32 %n, 2147483647 117 %a = icmp sgt i32 %nn, %x 118 %b = icmp sge i32 %x, 0 119 %c = select i1 %a, i1 %b, i1 false 120 ret i1 %c 121} 122 123define i1 @test_and3_sext(i32 %x, i64 %n) { 124; CHECK-LABEL: @test_and3_sext( 125; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 126; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 127; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 128; CHECK-NEXT: [[C:%.*]] = icmp ugt i64 [[NN]], [[X_SEXT]] 129; CHECK-NEXT: ret i1 [[C]] 130; 131 %n_not_negative = icmp sge i64 %n, 0 132 call void @llvm.assume(i1 %n_not_negative) 133 %x_sext = sext i32 %x to i64 134 %a = icmp sgt i64 %n, %x_sext 135 %b = icmp sge i32 %x, 0 136 %c = and i1 %a, %b 137 ret i1 %c 138} 139 140define i1 @test_and4(i32 %x, i32 %n) { 141; CHECK-LABEL: @test_and4( 142; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 143; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[X:%.*]], [[NN]] 144; CHECK-NEXT: ret i1 [[C]] 145; 146 %nn = and i32 %n, 2147483647 147 %a = icmp sge i32 %nn, %x 148 %b = icmp sge i32 %x, 0 149 %c = and i1 %a, %b 150 ret i1 %c 151} 152 153define i1 @test_and4_logical(i32 %x, i32 %n) { 154; CHECK-LABEL: @test_and4_logical( 155; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 156; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[X:%.*]], [[NN]] 157; CHECK-NEXT: ret i1 [[C]] 158; 159 %nn = and i32 %n, 2147483647 160 %a = icmp sge i32 %nn, %x 161 %b = icmp sge i32 %x, 0 162 %c = select i1 %a, i1 %b, i1 false 163 ret i1 %c 164} 165 166define i1 @test_and4_sext(i32 %x, i64 %n) { 167; CHECK-LABEL: @test_and4_sext( 168; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 169; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 170; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 171; CHECK-NEXT: [[C:%.*]] = icmp uge i64 [[NN]], [[X_SEXT]] 172; CHECK-NEXT: ret i1 [[C]] 173; 174 %n_not_negative = icmp sge i64 %n, 0 175 call void @llvm.assume(i1 %n_not_negative) 176 %x_sext = sext i32 %x to i64 177 %a = icmp sge i64 %n, %x_sext 178 %b = icmp sge i32 %x, 0 179 %c = and i1 %a, %b 180 ret i1 %c 181} 182 183define i1 @test_or1(i32 %x, i32 %n) { 184; CHECK-LABEL: @test_or1( 185; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 186; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[X:%.*]], [[NN]] 187; CHECK-NEXT: ret i1 [[C]] 188; 189 %nn = and i32 %n, 2147483647 190 %a = icmp slt i32 %x, 0 191 %b = icmp sge i32 %x, %nn 192 %c = or i1 %a, %b 193 ret i1 %c 194} 195 196define i1 @test_or1_logical(i32 %x, i32 %n) { 197; CHECK-LABEL: @test_or1_logical( 198; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 199; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], 0 200; CHECK-NEXT: [[B:%.*]] = icmp sge i32 [[X]], [[NN]] 201; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 true, i1 [[B]] 202; CHECK-NEXT: ret i1 [[C]] 203; 204 %nn = and i32 %n, 2147483647 205 %a = icmp slt i32 %x, 0 206 %b = icmp sge i32 %x, %nn 207 %c = select i1 %a, i1 true, i1 %b 208 ret i1 %c 209} 210 211define i1 @test_or1_sext(i32 %x, i64 %n) { 212; CHECK-LABEL: @test_or1_sext( 213; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 214; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 215; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 216; CHECK-NEXT: [[C:%.*]] = icmp ule i64 [[NN]], [[X_SEXT]] 217; CHECK-NEXT: ret i1 [[C]] 218; 219 %n_not_negative = icmp sge i64 %n, 0 220 call void @llvm.assume(i1 %n_not_negative) 221 %x_sext = sext i32 %x to i64 222 %a = icmp slt i32 %x, 0 223 %b = icmp sge i64 %x_sext, %n 224 %c = or i1 %a, %b 225 ret i1 %c 226} 227 228define i1 @test_or2(i32 %x, i32 %n) { 229; CHECK-LABEL: @test_or2( 230; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 231; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], [[NN]] 232; CHECK-NEXT: ret i1 [[C]] 233; 234 %nn = and i32 %n, 2147483647 235 %a = icmp sle i32 %x, -1 236 %b = icmp sgt i32 %x, %nn 237 %c = or i1 %a, %b 238 ret i1 %c 239} 240 241define i1 @test_or2_logical(i32 %x, i32 %n) { 242; CHECK-LABEL: @test_or2_logical( 243; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 244; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], 0 245; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], [[NN]] 246; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 true, i1 [[B]] 247; CHECK-NEXT: ret i1 [[C]] 248; 249 %nn = and i32 %n, 2147483647 250 %a = icmp sle i32 %x, -1 251 %b = icmp sgt i32 %x, %nn 252 %c = select i1 %a, i1 true, i1 %b 253 ret i1 %c 254} 255 256define i1 @test_or2_sext(i32 %x, i64 %n) { 257; CHECK-LABEL: @test_or2_sext( 258; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 259; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 260; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 261; CHECK-NEXT: [[C:%.*]] = icmp ult i64 [[NN]], [[X_SEXT]] 262; CHECK-NEXT: ret i1 [[C]] 263; 264 %n_not_negative = icmp sge i64 %n, 0 265 call void @llvm.assume(i1 %n_not_negative) 266 %x_sext = sext i32 %x to i64 267 %a = icmp sle i32 %x, -1 268 %b = icmp sgt i64 %x_sext, %n 269 %c = or i1 %a, %b 270 ret i1 %c 271} 272 273define i1 @test_or3(i32 %x, i32 %n) { 274; CHECK-LABEL: @test_or3( 275; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 276; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[X:%.*]], [[NN]] 277; CHECK-NEXT: ret i1 [[C]] 278; 279 %nn = and i32 %n, 2147483647 280 %a = icmp sle i32 %nn, %x 281 %b = icmp slt i32 %x, 0 282 %c = or i1 %a, %b 283 ret i1 %c 284} 285 286define i1 @test_or3_logical(i32 %x, i32 %n) { 287; CHECK-LABEL: @test_or3_logical( 288; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 289; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[X:%.*]], [[NN]] 290; CHECK-NEXT: ret i1 [[C]] 291; 292 %nn = and i32 %n, 2147483647 293 %a = icmp sle i32 %nn, %x 294 %b = icmp slt i32 %x, 0 295 %c = select i1 %a, i1 true, i1 %b 296 ret i1 %c 297} 298 299define i1 @test_or3_sext(i32 %x, i64 %n) { 300; CHECK-LABEL: @test_or3_sext( 301; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 302; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 303; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 304; CHECK-NEXT: [[C:%.*]] = icmp ule i64 [[NN]], [[X_SEXT]] 305; CHECK-NEXT: ret i1 [[C]] 306; 307 %n_not_negative = icmp sge i64 %n, 0 308 call void @llvm.assume(i1 %n_not_negative) 309 %x_sext = sext i32 %x to i64 310 %a = icmp sle i64 %n, %x_sext 311 %b = icmp slt i32 %x, 0 312 %c = or i1 %a, %b 313 ret i1 %c 314} 315 316define i1 @test_or4(i32 %x, i32 %n) { 317; CHECK-LABEL: @test_or4( 318; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 319; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], [[NN]] 320; CHECK-NEXT: ret i1 [[C]] 321; 322 %nn = and i32 %n, 2147483647 323 %a = icmp slt i32 %nn, %x 324 %b = icmp slt i32 %x, 0 325 %c = or i1 %a, %b 326 ret i1 %c 327} 328 329define i1 @test_or4_logical(i32 %x, i32 %n) { 330; CHECK-LABEL: @test_or4_logical( 331; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 332; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[X:%.*]], [[NN]] 333; CHECK-NEXT: ret i1 [[C]] 334; 335 %nn = and i32 %n, 2147483647 336 %a = icmp slt i32 %nn, %x 337 %b = icmp slt i32 %x, 0 338 %c = select i1 %a, i1 true, i1 %b 339 ret i1 %c 340} 341 342define i1 @test_or4_sext(i32 %x, i64 %n) { 343; CHECK-LABEL: @test_or4_sext( 344; CHECK-NEXT: [[N_NOT_NEGATIVE:%.*]] = icmp sgt i64 [[NN:%.*]], -1 345; CHECK-NEXT: call void @llvm.assume(i1 [[N_NOT_NEGATIVE]]) 346; CHECK-NEXT: [[X_SEXT:%.*]] = sext i32 [[X:%.*]] to i64 347; CHECK-NEXT: [[C:%.*]] = icmp ult i64 [[NN]], [[X_SEXT]] 348; CHECK-NEXT: ret i1 [[C]] 349; 350 %n_not_negative = icmp sge i64 %n, 0 351 call void @llvm.assume(i1 %n_not_negative) 352 %x_sext = sext i32 %x to i64 353 %a = icmp slt i64 %n, %x_sext 354 %b = icmp slt i32 %x, 0 355 %c = or i1 %a, %b 356 ret i1 %c 357} 358 359; Negative tests 360 361define i1 @negative1(i32 %x, i32 %n) { 362; CHECK-LABEL: @negative1( 363; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 364; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[NN]] 365; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], 0 366; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] 367; CHECK-NEXT: ret i1 [[C]] 368; 369 %nn = and i32 %n, 2147483647 370 %a = icmp slt i32 %x, %nn 371 %b = icmp sgt i32 %x, 0 ; should be: icmp sge 372 %c = and i1 %a, %b 373 ret i1 %c 374} 375 376define i1 @negative1_logical(i32 %x, i32 %n) { 377; CHECK-LABEL: @negative1_logical( 378; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 379; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[NN]] 380; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], 0 381; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] 382; CHECK-NEXT: ret i1 [[C]] 383; 384 %nn = and i32 %n, 2147483647 385 %a = icmp slt i32 %x, %nn 386 %b = icmp sgt i32 %x, 0 ; should be: icmp sge 387 %c = select i1 %a, i1 %b, i1 false 388 ret i1 %c 389} 390 391define i1 @negative2(i32 %x, i32 %n) { 392; CHECK-LABEL: @negative2( 393; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[N:%.*]] 394; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1 395; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] 396; CHECK-NEXT: ret i1 [[C]] 397; 398 %a = icmp slt i32 %x, %n ; n can be negative 399 %b = icmp sge i32 %x, 0 400 %c = and i1 %a, %b 401 ret i1 %c 402} 403 404define i1 @negative2_logical(i32 %x, i32 %n) { 405; CHECK-LABEL: @negative2_logical( 406; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[N:%.*]] 407; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1 408; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] 409; CHECK-NEXT: ret i1 [[C]] 410; 411 %a = icmp slt i32 %x, %n ; n can be negative 412 %b = icmp sge i32 %x, 0 413 %c = select i1 %a, i1 %b, i1 false 414 ret i1 %c 415} 416 417define i1 @negative3(i32 %x, i32 %y, i32 %n) { 418; CHECK-LABEL: @negative3( 419; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 420; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[NN]] 421; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1 422; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] 423; CHECK-NEXT: ret i1 [[C]] 424; 425 %nn = and i32 %n, 2147483647 426 %a = icmp slt i32 %x, %nn 427 %b = icmp sge i32 %y, 0 ; should compare %x and not %y 428 %c = and i1 %a, %b 429 ret i1 %c 430} 431 432define i1 @negative3_logical(i32 %x, i32 %y, i32 %n) { 433; CHECK-LABEL: @negative3_logical( 434; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 435; CHECK-NEXT: [[A:%.*]] = icmp slt i32 [[X:%.*]], [[NN]] 436; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[Y:%.*]], -1 437; CHECK-NEXT: [[C:%.*]] = select i1 [[A]], i1 [[B]], i1 false 438; CHECK-NEXT: ret i1 [[C]] 439; 440 %nn = and i32 %n, 2147483647 441 %a = icmp slt i32 %x, %nn 442 %b = icmp sge i32 %y, 0 ; should compare %x and not %y 443 %c = select i1 %a, i1 %b, i1 false 444 ret i1 %c 445} 446 447define i1 @negative4(i32 %x, i32 %n) { 448; CHECK-LABEL: @negative4( 449; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 450; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[NN]] 451; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1 452; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] 453; CHECK-NEXT: ret i1 [[C]] 454; 455 %nn = and i32 %n, 2147483647 456 %a = icmp ne i32 %x, %nn ; should be: icmp slt/sle 457 %b = icmp sge i32 %x, 0 458 %c = and i1 %a, %b 459 ret i1 %c 460} 461 462define i1 @negative4_logical(i32 %x, i32 %n) { 463; CHECK-LABEL: @negative4_logical( 464; CHECK-NEXT: [[NN:%.*]] = and i32 [[N:%.*]], 2147483647 465; CHECK-NEXT: [[A:%.*]] = icmp ne i32 [[X:%.*]], [[NN]] 466; CHECK-NEXT: [[B:%.*]] = icmp sgt i32 [[X]], -1 467; CHECK-NEXT: [[C:%.*]] = and i1 [[A]], [[B]] 468; CHECK-NEXT: ret i1 [[C]] 469; 470 %nn = and i32 %n, 2147483647 471 %a = icmp ne i32 %x, %nn ; should be: icmp slt/sle 472 %b = icmp sge i32 %x, 0 473 %c = select i1 %a, i1 %b, i1 false 474 ret i1 %c 475} 476 477define i1 @negative5(i32 %x, i32 %n) { 478; CHECK-LABEL: @negative5( 479; CHECK-NEXT: ret i1 true 480; 481 %nn = and i32 %n, 2147483647 482 %a = icmp slt i32 %x, %nn 483 %b = icmp sge i32 %x, 0 484 %c = or i1 %a, %b ; should be: and 485 ret i1 %c 486} 487 488define i1 @negative5_logical(i32 %x, i32 %n) { 489; CHECK-LABEL: @negative5_logical( 490; CHECK-NEXT: ret i1 true 491; 492 %nn = and i32 %n, 2147483647 493 %a = icmp slt i32 %x, %nn 494 %b = icmp sge i32 %x, 0 495 %c = select i1 %a, i1 true, i1 %b ; should be: and 496 ret i1 %c 497} 498 499