xref: /llvm-project/llvm/test/Transforms/InstCombine/modulo.ll (revision 38fffa630ee80163dc65e759392ad29798905679) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -S -passes=instcombine | FileCheck %s
3
4; PR21929
5define i32 @modulo2(i32 %x) {
6; CHECK-LABEL: @modulo2(
7; CHECK-NEXT:    [[RET_I:%.*]] = and i32 [[X:%.*]], 1
8; CHECK-NEXT:    ret i32 [[RET_I]]
9;
10  %rem.i = srem i32 %x, 2
11  %cmp.i = icmp slt i32 %rem.i, 0
12  %add.i = select i1 %cmp.i, i32 2, i32 0
13  %ret.i = add nsw i32 %add.i, %rem.i
14  ret i32 %ret.i
15}
16
17define <2 x i32> @modulo2_vec(<2 x i32> %x) {
18; CHECK-LABEL: @modulo2_vec(
19; CHECK-NEXT:    [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 1)
20; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
21;
22  %rem.i = srem <2 x i32> %x, <i32 2, i32 2>
23  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
24  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 2, i32 2>, <2 x i32> zeroinitializer
25  %ret.i = add nsw <2 x i32> %add.i, %rem.i
26  ret <2 x i32> %ret.i
27}
28
29define i32 @modulo3(i32 %x) {
30; CHECK-LABEL: @modulo3(
31; CHECK-NEXT:    [[REM_I:%.*]] = srem i32 [[X:%.*]], 3
32; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt i32 [[REM_I]], 0
33; CHECK-NEXT:    [[ADD_I:%.*]] = select i1 [[CMP_I]], i32 3, i32 0
34; CHECK-NEXT:    [[RET_I:%.*]] = add nsw i32 [[ADD_I]], [[REM_I]]
35; CHECK-NEXT:    ret i32 [[RET_I]]
36;
37  %rem.i = srem i32 %x, 3
38  %cmp.i = icmp slt i32 %rem.i, 0
39  %add.i = select i1 %cmp.i, i32 3, i32 0
40  %ret.i = add nsw i32 %add.i, %rem.i
41  ret i32 %ret.i
42}
43
44define <2 x i32> @modulo3_vec(<2 x i32> %x) {
45; CHECK-LABEL: @modulo3_vec(
46; CHECK-NEXT:    [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], splat (i32 3)
47; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
48; CHECK-NEXT:    [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> splat (i32 3), <2 x i32> zeroinitializer
49; CHECK-NEXT:    [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
50; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
51;
52  %rem.i = srem <2 x i32> %x, <i32 3, i32 3>
53  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
54  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 3, i32 3>, <2 x i32> zeroinitializer
55  %ret.i = add nsw <2 x i32> %add.i, %rem.i
56  ret <2 x i32> %ret.i
57}
58
59define i32 @modulo4(i32 %x) {
60; CHECK-LABEL: @modulo4(
61; CHECK-NEXT:    [[RET_I:%.*]] = and i32 [[X:%.*]], 3
62; CHECK-NEXT:    ret i32 [[RET_I]]
63;
64  %rem.i = srem i32 %x, 4
65  %cmp.i = icmp slt i32 %rem.i, 0
66  %add.i = select i1 %cmp.i, i32 4, i32 0
67  %ret.i = add nsw i32 %add.i, %rem.i
68  ret i32 %ret.i
69}
70
71define <2 x i32> @modulo4_vec(<2 x i32> %x) {
72; CHECK-LABEL: @modulo4_vec(
73; CHECK-NEXT:    [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 3)
74; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
75;
76  %rem.i = srem <2 x i32> %x, <i32 4, i32 4>
77  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
78  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 4, i32 4>, <2 x i32> zeroinitializer
79  %ret.i = add nsw <2 x i32> %add.i, %rem.i
80  ret <2 x i32> %ret.i
81}
82
83define i32 @modulo7(i32 %x) {
84; CHECK-LABEL: @modulo7(
85; CHECK-NEXT:    [[REM_I:%.*]] = srem i32 [[X:%.*]], 7
86; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt i32 [[REM_I]], 0
87; CHECK-NEXT:    [[ADD_I:%.*]] = select i1 [[CMP_I]], i32 7, i32 0
88; CHECK-NEXT:    [[RET_I:%.*]] = add nsw i32 [[ADD_I]], [[REM_I]]
89; CHECK-NEXT:    ret i32 [[RET_I]]
90;
91  %rem.i = srem i32 %x, 7
92  %cmp.i = icmp slt i32 %rem.i, 0
93  %add.i = select i1 %cmp.i, i32 7, i32 0
94  %ret.i = add nsw i32 %add.i, %rem.i
95  ret i32 %ret.i
96}
97
98define <2 x i32> @modulo7_vec(<2 x i32> %x) {
99; CHECK-LABEL: @modulo7_vec(
100; CHECK-NEXT:    [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], splat (i32 7)
101; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
102; CHECK-NEXT:    [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> splat (i32 7), <2 x i32> zeroinitializer
103; CHECK-NEXT:    [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
104; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
105;
106  %rem.i = srem <2 x i32> %x, <i32 7, i32 7>
107  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
108  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 7, i32 7>, <2 x i32> zeroinitializer
109  %ret.i = add nsw <2 x i32> %add.i, %rem.i
110  ret <2 x i32> %ret.i
111}
112
113define i32 @modulo32(i32 %x) {
114; CHECK-LABEL: @modulo32(
115; CHECK-NEXT:    [[RET_I:%.*]] = and i32 [[X:%.*]], 31
116; CHECK-NEXT:    ret i32 [[RET_I]]
117;
118  %rem.i = srem i32 %x, 32
119  %cmp.i = icmp slt i32 %rem.i, 0
120  %add.i = select i1 %cmp.i, i32 32, i32 0
121  %ret.i = add nsw i32 %add.i, %rem.i
122  ret i32 %ret.i
123}
124
125define <2 x i32> @modulo32_vec(<2 x i32> %x) {
126; CHECK-LABEL: @modulo32_vec(
127; CHECK-NEXT:    [[RET_I:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 31)
128; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
129;
130  %rem.i = srem <2 x i32> %x, <i32 32, i32 32>
131  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
132  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 32, i32 32>, <2 x i32> zeroinitializer
133  %ret.i = add nsw <2 x i32> %add.i, %rem.i
134  ret <2 x i32> %ret.i
135}
136
137define <2 x i32> @modulo16_32_vec(<2 x i32> %x) {
138; CHECK-LABEL: @modulo16_32_vec(
139; CHECK-NEXT:    [[REM_I:%.*]] = srem <2 x i32> [[X:%.*]], <i32 16, i32 32>
140; CHECK-NEXT:    [[CMP_I:%.*]] = icmp slt <2 x i32> [[REM_I]], zeroinitializer
141; CHECK-NEXT:    [[ADD_I:%.*]] = select <2 x i1> [[CMP_I]], <2 x i32> <i32 16, i32 32>, <2 x i32> zeroinitializer
142; CHECK-NEXT:    [[RET_I:%.*]] = add nsw <2 x i32> [[ADD_I]], [[REM_I]]
143; CHECK-NEXT:    ret <2 x i32> [[RET_I]]
144;
145  %rem.i = srem <2 x i32> %x, <i32 16, i32 32>
146  %cmp.i = icmp slt <2 x i32> %rem.i, zeroinitializer
147  %add.i = select <2 x i1> %cmp.i, <2 x i32> <i32 16, i32 32>, <2 x i32> zeroinitializer
148  %ret.i = add nsw <2 x i32> %add.i, %rem.i
149  ret <2 x i32> %ret.i
150}
151