1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=instcombine -S -o - %s | FileCheck %s 3 4define i1 @masked_and_notallzeroes(i32 %A) { 5; CHECK-LABEL: @masked_and_notallzeroes( 6; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 7; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 0 8; CHECK-NEXT: ret i1 [[TST1]] 9; 10 %mask1 = and i32 %A, 7 11 %tst1 = icmp ne i32 %mask1, 0 12 %mask2 = and i32 %A, 39 13 %tst2 = icmp ne i32 %mask2, 0 14 %res = and i1 %tst1, %tst2 15 ret i1 %res 16} 17 18define <2 x i1> @masked_and_notallzeroes_splat(<2 x i32> %A) { 19; CHECK-LABEL: @masked_and_notallzeroes_splat( 20; CHECK-NEXT: [[MASK1:%.*]] = and <2 x i32> [[A:%.*]], splat (i32 7) 21; CHECK-NEXT: [[TST1:%.*]] = icmp ne <2 x i32> [[MASK1]], zeroinitializer 22; CHECK-NEXT: ret <2 x i1> [[TST1]] 23; 24 %mask1 = and <2 x i32> %A, <i32 7, i32 7> 25 %tst1 = icmp ne <2 x i32> %mask1, <i32 0, i32 0> 26 %mask2 = and <2 x i32> %A, <i32 39, i32 39> 27 %tst2 = icmp ne <2 x i32> %mask2, <i32 0, i32 0> 28 %res = and <2 x i1> %tst1, %tst2 29 ret <2 x i1> %res 30} 31 32define i1 @masked_and_notallzeroes_logical(i32 %A) { 33; CHECK-LABEL: @masked_and_notallzeroes_logical( 34; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 35; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 0 36; CHECK-NEXT: ret i1 [[TST1]] 37; 38 %mask1 = and i32 %A, 7 39 %tst1 = icmp ne i32 %mask1, 0 40 %mask2 = and i32 %A, 39 41 %tst2 = icmp ne i32 %mask2, 0 42 %res = select i1 %tst1, i1 %tst2, i1 false 43 ret i1 %res 44} 45 46define i1 @masked_or_allzeroes(i32 %A) { 47; CHECK-LABEL: @masked_or_allzeroes( 48; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 49; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0 50; CHECK-NEXT: ret i1 [[TST1]] 51; 52 %mask1 = and i32 %A, 7 53 %tst1 = icmp eq i32 %mask1, 0 54 %mask2 = and i32 %A, 39 55 %tst2 = icmp eq i32 %mask2, 0 56 %res = or i1 %tst1, %tst2 57 ret i1 %res 58} 59 60define i1 @masked_or_allzeroes_logical(i32 %A) { 61; CHECK-LABEL: @masked_or_allzeroes_logical( 62; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 63; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0 64; CHECK-NEXT: ret i1 [[TST1]] 65; 66 %mask1 = and i32 %A, 7 67 %tst1 = icmp eq i32 %mask1, 0 68 %mask2 = and i32 %A, 39 69 %tst2 = icmp eq i32 %mask2, 0 70 %res = select i1 %tst1, i1 true, i1 %tst2 71 ret i1 %res 72} 73 74define i1 @masked_and_notallones(i32 %A) { 75; CHECK-LABEL: @masked_and_notallones( 76; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 77; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 7 78; CHECK-NEXT: ret i1 [[TST1]] 79; 80 %mask1 = and i32 %A, 7 81 %tst1 = icmp ne i32 %mask1, 7 82 %mask2 = and i32 %A, 39 83 %tst2 = icmp ne i32 %mask2, 39 84 %res = and i1 %tst1, %tst2 85 ret i1 %res 86} 87 88define i1 @masked_and_notallones_logical(i32 %A) { 89; CHECK-LABEL: @masked_and_notallones_logical( 90; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 91; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 7 92; CHECK-NEXT: ret i1 [[TST1]] 93; 94 %mask1 = and i32 %A, 7 95 %tst1 = icmp ne i32 %mask1, 7 96 %mask2 = and i32 %A, 39 97 %tst2 = icmp ne i32 %mask2, 39 98 %res = select i1 %tst1, i1 %tst2, i1 false 99 ret i1 %res 100} 101 102define i1 @masked_or_allones(i32 %A) { 103; CHECK-LABEL: @masked_or_allones( 104; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 105; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 7 106; CHECK-NEXT: ret i1 [[TST1]] 107; 108 %mask1 = and i32 %A, 7 109 %tst1 = icmp eq i32 %mask1, 7 110 %mask2 = and i32 %A, 39 111 %tst2 = icmp eq i32 %mask2, 39 112 %res = or i1 %tst1, %tst2 113 ret i1 %res 114} 115 116define i1 @masked_or_allones_logical(i32 %A) { 117; CHECK-LABEL: @masked_or_allones_logical( 118; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7 119; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 7 120; CHECK-NEXT: ret i1 [[TST1]] 121; 122 %mask1 = and i32 %A, 7 123 %tst1 = icmp eq i32 %mask1, 7 124 %mask2 = and i32 %A, 39 125 %tst2 = icmp eq i32 %mask2, 39 126 %res = select i1 %tst1, i1 true, i1 %tst2 127 ret i1 %res 128} 129 130define i1 @masked_and_notA(i32 %A) { 131; CHECK-LABEL: @masked_and_notA( 132; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -79 133; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[TMP1]], 0 134; CHECK-NEXT: ret i1 [[TST2]] 135; 136 %mask1 = and i32 %A, 14 137 %tst1 = icmp ne i32 %mask1, %A 138 %mask2 = and i32 %A, 78 139 %tst2 = icmp ne i32 %mask2, %A 140 %res = and i1 %tst1, %tst2 141 ret i1 %res 142} 143 144define i1 @masked_and_notA_logical(i32 %A) { 145; CHECK-LABEL: @masked_and_notA_logical( 146; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -79 147; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[TMP1]], 0 148; CHECK-NEXT: ret i1 [[TST2]] 149; 150 %mask1 = and i32 %A, 14 151 %tst1 = icmp ne i32 %mask1, %A 152 %mask2 = and i32 %A, 78 153 %tst2 = icmp ne i32 %mask2, %A 154 %res = select i1 %tst1, i1 %tst2, i1 false 155 ret i1 %res 156} 157 158define i1 @masked_and_notA_slightly_optimized(i32 %A) { 159; CHECK-LABEL: @masked_and_notA_slightly_optimized( 160; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -40 161; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[TMP1]], 0 162; CHECK-NEXT: ret i1 [[TST2]] 163; 164 %t0 = icmp uge i32 %A, 8 165 %mask2 = and i32 %A, 39 166 %tst2 = icmp ne i32 %mask2, %A 167 %res = and i1 %t0, %tst2 168 ret i1 %res 169} 170 171define i1 @masked_and_notA_slightly_optimized_logical(i32 %A) { 172; CHECK-LABEL: @masked_and_notA_slightly_optimized_logical( 173; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -40 174; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[TMP1]], 0 175; CHECK-NEXT: ret i1 [[TST2]] 176; 177 %t0 = icmp uge i32 %A, 8 178 %mask2 = and i32 %A, 39 179 %tst2 = icmp ne i32 %mask2, %A 180 %res = select i1 %t0, i1 %tst2, i1 false 181 ret i1 %res 182} 183 184define i1 @masked_or_A(i32 %A) { 185; CHECK-LABEL: @masked_or_A( 186; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -79 187; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[TMP1]], 0 188; CHECK-NEXT: ret i1 [[TST2]] 189; 190 %mask1 = and i32 %A, 14 191 %tst1 = icmp eq i32 %mask1, %A 192 %mask2 = and i32 %A, 78 193 %tst2 = icmp eq i32 %mask2, %A 194 %res = or i1 %tst1, %tst2 195 ret i1 %res 196} 197 198define i1 @masked_or_A_logical(i32 %A) { 199; CHECK-LABEL: @masked_or_A_logical( 200; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -79 201; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[TMP1]], 0 202; CHECK-NEXT: ret i1 [[TST2]] 203; 204 %mask1 = and i32 %A, 14 205 %tst1 = icmp eq i32 %mask1, %A 206 %mask2 = and i32 %A, 78 207 %tst2 = icmp eq i32 %mask2, %A 208 %res = select i1 %tst1, i1 true, i1 %tst2 209 ret i1 %res 210} 211 212define i1 @masked_or_A_slightly_optimized(i32 %A) { 213; CHECK-LABEL: @masked_or_A_slightly_optimized( 214; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -40 215; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[TMP1]], 0 216; CHECK-NEXT: ret i1 [[TST2]] 217; 218 %t0 = icmp ult i32 %A, 8 219 %mask2 = and i32 %A, 39 220 %tst2 = icmp eq i32 %mask2, %A 221 %res = or i1 %t0, %tst2 222 ret i1 %res 223} 224 225define i1 @masked_or_A_slightly_optimized_logical(i32 %A) { 226; CHECK-LABEL: @masked_or_A_slightly_optimized_logical( 227; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -40 228; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[TMP1]], 0 229; CHECK-NEXT: ret i1 [[TST2]] 230; 231 %t0 = icmp ult i32 %A, 8 232 %mask2 = and i32 %A, 39 233 %tst2 = icmp eq i32 %mask2, %A 234 %res = select i1 %t0, i1 true, i1 %tst2 235 ret i1 %res 236} 237 238define i1 @masked_or_allzeroes_notoptimised(i32 %A) { 239; CHECK-LABEL: @masked_or_allzeroes_notoptimised( 240; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15 241; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0 242; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 39 243; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], 0 244; CHECK-NEXT: [[RES:%.*]] = or i1 [[TST1]], [[TST2]] 245; CHECK-NEXT: ret i1 [[RES]] 246; 247 %mask1 = and i32 %A, 15 248 %tst1 = icmp eq i32 %mask1, 0 249 %mask2 = and i32 %A, 39 250 %tst2 = icmp eq i32 %mask2, 0 251 %res = or i1 %tst1, %tst2 252 ret i1 %res 253} 254 255define i1 @masked_or_allzeroes_notoptimised_logical(i32 %A) { 256; CHECK-LABEL: @masked_or_allzeroes_notoptimised_logical( 257; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15 258; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0 259; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 39 260; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], 0 261; CHECK-NEXT: [[RES:%.*]] = or i1 [[TST1]], [[TST2]] 262; CHECK-NEXT: ret i1 [[RES]] 263; 264 %mask1 = and i32 %A, 15 265 %tst1 = icmp eq i32 %mask1, 0 266 %mask2 = and i32 %A, 39 267 %tst2 = icmp eq i32 %mask2, 0 268 %res = select i1 %tst1, i1 true, i1 %tst2 269 ret i1 %res 270} 271 272define i1 @nomask_lhs(i32 %in) { 273; CHECK-LABEL: @nomask_lhs( 274; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[IN:%.*]], 1 275; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASKED]], 0 276; CHECK-NEXT: ret i1 [[TST2]] 277; 278 %tst1 = icmp eq i32 %in, 0 279 %masked = and i32 %in, 1 280 %tst2 = icmp eq i32 %masked, 0 281 %val = or i1 %tst1, %tst2 282 ret i1 %val 283} 284 285define i1 @nomask_lhs_logical(i32 %in) { 286; CHECK-LABEL: @nomask_lhs_logical( 287; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[IN:%.*]], 1 288; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASKED]], 0 289; CHECK-NEXT: ret i1 [[TST2]] 290; 291 %tst1 = icmp eq i32 %in, 0 292 %masked = and i32 %in, 1 293 %tst2 = icmp eq i32 %masked, 0 294 %val = select i1 %tst1, i1 true, i1 %tst2 295 ret i1 %val 296} 297 298define i1 @nomask_rhs(i32 %in) { 299; CHECK-LABEL: @nomask_rhs( 300; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[IN:%.*]], 1 301; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASKED]], 0 302; CHECK-NEXT: ret i1 [[TST1]] 303; 304 %masked = and i32 %in, 1 305 %tst1 = icmp eq i32 %masked, 0 306 %tst2 = icmp eq i32 %in, 0 307 %val = or i1 %tst1, %tst2 308 ret i1 %val 309} 310 311define i1 @nomask_rhs_logical(i32 %in) { 312; CHECK-LABEL: @nomask_rhs_logical( 313; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[IN:%.*]], 1 314; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASKED]], 0 315; CHECK-NEXT: ret i1 [[TST1]] 316; 317 %masked = and i32 %in, 1 318 %tst1 = icmp eq i32 %masked, 0 319 %tst2 = icmp eq i32 %in, 0 320 %val = select i1 %tst1, i1 true, i1 %tst2 321 ret i1 %val 322} 323 324; TODO: This test simplifies to a constant, so the functionality and test could be in InstSimplify. 325 326define i1 @fold_mask_cmps_to_false(i32 %x) { 327; CHECK-LABEL: @fold_mask_cmps_to_false( 328; CHECK-NEXT: ret i1 false 329; 330 %t1 = and i32 %x, 2147483647 331 %t2 = icmp eq i32 %t1, 0 332 %t3 = icmp eq i32 %x, 2147483647 333 %t4 = and i1 %t3, %t2 334 ret i1 %t4 335} 336 337define i1 @fold_mask_cmps_to_false_logical(i32 %x) { 338; CHECK-LABEL: @fold_mask_cmps_to_false_logical( 339; CHECK-NEXT: ret i1 false 340; 341 %t1 = and i32 %x, 2147483647 342 %t2 = icmp eq i32 %t1, 0 343 %t3 = icmp eq i32 %x, 2147483647 344 %t4 = select i1 %t3, i1 %t2, i1 false 345 ret i1 %t4 346} 347 348; TODO: This test simplifies to a constant, so the functionality and test could be in InstSimplify. 349 350define i1 @fold_mask_cmps_to_true(i32 %x) { 351; CHECK-LABEL: @fold_mask_cmps_to_true( 352; CHECK-NEXT: ret i1 true 353; 354 %t1 = and i32 %x, 2147483647 355 %t2 = icmp ne i32 %t1, 0 356 %t3 = icmp ne i32 %x, 2147483647 357 %t4 = or i1 %t3, %t2 358 ret i1 %t4 359} 360 361define i1 @fold_mask_cmps_to_true_logical(i32 %x) { 362; CHECK-LABEL: @fold_mask_cmps_to_true_logical( 363; CHECK-NEXT: ret i1 true 364; 365 %t1 = and i32 %x, 2147483647 366 %t2 = icmp ne i32 %t1, 0 367 %t3 = icmp ne i32 %x, 2147483647 368 %t4 = select i1 %t3, i1 true, i1 %t2 369 ret i1 %t4 370} 371 372define <2 x i1> @nomask_splat_and_B_allones(<2 x i32> %A) { 373; CHECK-LABEL: @nomask_splat_and_B_allones( 374; CHECK-NEXT: [[RES:%.*]] = icmp ugt <2 x i32> [[A:%.*]], splat (i32 -268435457) 375; CHECK-NEXT: ret <2 x i1> [[RES]] 376; 377 %tst1 = icmp slt <2 x i32> %A, <i32 0, i32 poison> 378 %mask2 = and <2 x i32> %A, <i32 1879048192, i32 1879048192> 379 %tst2 = icmp eq <2 x i32> %mask2, <i32 1879048192, i32 1879048192> 380 %res = and <2 x i1> %tst1, %tst2 381 ret <2 x i1> %res 382} 383 384define <2 x i1> @nomask_splat_and_B_mixed(<2 x i32> %A) { 385; CHECK-LABEL: @nomask_splat_and_B_mixed( 386; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], splat (i32 -268435456) 387; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x i32> [[TMP1]], splat (i32 1879048192) 388; CHECK-NEXT: ret <2 x i1> [[RES]] 389; 390 %tst1 = icmp sgt <2 x i32> %A, <i32 -1, i32 poison> 391 %mask2 = and <2 x i32> %A, <i32 1879048192, i32 1879048192> 392 %tst2 = icmp eq <2 x i32> %mask2, <i32 1879048192, i32 1879048192> 393 %res = and <2 x i1> %tst1, %tst2 394 ret <2 x i1> %res 395} 396 397; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401 398 399define i1 @cmpeq_bitwise(i8 %a, i8 %b, i8 %c, i8 %d) { 400; CHECK-LABEL: @cmpeq_bitwise( 401; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[A:%.*]], [[B:%.*]] 402; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[C:%.*]], [[D:%.*]] 403; CHECK-NEXT: [[CMP:%.*]] = and i1 [[TMP1]], [[TMP2]] 404; CHECK-NEXT: ret i1 [[CMP]] 405; 406 %xor1 = xor i8 %a, %b 407 %xor2 = xor i8 %c, %d 408 %or = or i8 %xor1, %xor2 409 %cmp = icmp eq i8 %or, 0 410 ret i1 %cmp 411} 412 413define <2 x i1> @cmpne_bitwise(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) { 414; CHECK-LABEL: @cmpne_bitwise( 415; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> [[A:%.*]], [[B:%.*]] 416; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[C:%.*]], [[D:%.*]] 417; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP1]], [[TMP2]] 418; CHECK-NEXT: ret <2 x i1> [[CMP]] 419; 420 %xor1 = xor <2 x i64> %a, %b 421 %xor2 = xor <2 x i64> %c, %d 422 %or = or <2 x i64> %xor1, %xor2 423 %cmp = icmp ne <2 x i64> %or, zeroinitializer 424 ret <2 x i1> %cmp 425} 426 427; ((X & 12) != 0 & (X & 3) == 1) -> no change 428define i1 @masked_icmps_mask_notallzeros_bmask_mixed_0(i32 %x) { 429; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_0( 430; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 431; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 432; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 433; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 434; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] 435; CHECK-NEXT: ret i1 [[T5]] 436; 437 %t1 = and i32 %x, 12 438 %t2 = icmp ne i32 %t1, 0 439 %t3 = and i32 %x, 3 440 %t4 = icmp eq i32 %t3, 1 441 %t5 = and i1 %t2, %t4 442 ret i1 %t5 443} 444 445define i1 @masked_icmps_mask_notallzeros_bmask_mixed_0_logical(i32 %x) { 446; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_0_logical( 447; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 448; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 449; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 450; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 451; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] 452; CHECK-NEXT: ret i1 [[T5]] 453; 454 %t1 = and i32 %x, 12 455 %t2 = icmp ne i32 %t1, 0 456 %t3 = and i32 %x, 3 457 %t4 = icmp eq i32 %t3, 1 458 %t5 = select i1 %t2, i1 %t4, i1 false 459 ret i1 %t5 460} 461 462; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9 463define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1(i32 %x) { 464; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1( 465; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 466; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 9 467; CHECK-NEXT: ret i1 [[T5]] 468; 469 %t1 = and i32 %x, 12 470 %t2 = icmp ne i32 %t1, 0 471 %t3 = and i32 %x, 7 472 %t4 = icmp eq i32 %t3, 1 473 %t5 = and i1 %t2, %t4 474 ret i1 %t5 475} 476 477define <2 x i1> @masked_icmps_mask_notallzeros_bmask_mixed_1_vector(<2 x i32> %x) { 478; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1_vector( 479; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], splat (i32 15) 480; CHECK-NEXT: [[T5:%.*]] = icmp eq <2 x i32> [[TMP1]], splat (i32 9) 481; CHECK-NEXT: ret <2 x i1> [[T5]] 482; 483 %t1 = and <2 x i32> %x, <i32 12, i32 12> 484 %t2 = icmp ne <2 x i32> %t1, zeroinitializer 485 %t3 = and <2 x i32> %x, <i32 7, i32 7> 486 %t4 = icmp eq <2 x i32> %t3, <i32 1, i32 1> 487 %t5 = and <2 x i1> %t2, %t4 488 ret <2 x i1> %t5 489} 490 491define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1_logical(i32 %x) { 492; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1_logical( 493; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 494; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 9 495; CHECK-NEXT: ret i1 [[T5]] 496; 497 %t1 = and i32 %x, 12 498 %t2 = icmp ne i32 %t1, 0 499 %t3 = and i32 %x, 7 500 %t4 = icmp eq i32 %t3, 1 501 %t5 = select i1 %t2, i1 %t4, i1 false 502 ret i1 %t5 503} 504 505; ((X & 14) != 0 & (X & 3) == 1) -> no change 506define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1b(i32 %x) { 507; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1b( 508; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 509; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 510; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 511; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 512; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] 513; CHECK-NEXT: ret i1 [[T5]] 514; 515 %t1 = and i32 %x, 14 516 %t2 = icmp ne i32 %t1, 0 517 %t3 = and i32 %x, 3 518 %t4 = icmp eq i32 %t3, 1 519 %t5 = and i1 %t2, %t4 520 ret i1 %t5 521} 522 523define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1b_logical(i32 %x) { 524; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1b_logical( 525; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 526; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 527; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 528; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 529; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] 530; CHECK-NEXT: ret i1 [[T5]] 531; 532 %t1 = and i32 %x, 14 533 %t2 = icmp ne i32 %t1, 0 534 %t3 = and i32 %x, 3 535 %t4 = icmp eq i32 %t3, 1 536 %t5 = select i1 %t2, i1 %t4, i1 false 537 ret i1 %t5 538} 539 540; ((X & 3) != 0 & (X & 7) == 0) -> false 541define i1 @masked_icmps_mask_notallzeros_bmask_mixed_2(i32 %x) { 542; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_2( 543; CHECK-NEXT: ret i1 false 544; 545 %t1 = and i32 %x, 3 546 %t2 = icmp ne i32 %t1, 0 547 %t3 = and i32 %x, 7 548 %t4 = icmp eq i32 %t3, 0 549 %t5 = and i1 %t2, %t4 550 ret i1 %t5 551} 552 553define i1 @masked_icmps_mask_notallzeros_bmask_mixed_2_logical(i32 %x) { 554; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_2_logical( 555; CHECK-NEXT: ret i1 false 556; 557 %t1 = and i32 %x, 3 558 %t2 = icmp ne i32 %t1, 0 559 %t3 = and i32 %x, 7 560 %t4 = icmp eq i32 %t3, 0 561 %t5 = select i1 %t2, i1 %t4, i1 false 562 ret i1 %t5 563} 564 565; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8 566define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3(i32 %x) { 567; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3( 568; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 569; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 8 570; CHECK-NEXT: ret i1 [[T5]] 571; 572 %t1 = and i32 %x, 15 573 %t2 = icmp ne i32 %t1, 0 574 %t3 = and i32 %x, 7 575 %t4 = icmp eq i32 %t3, 0 576 %t5 = and i1 %t2, %t4 577 ret i1 %t5 578} 579 580define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3_logical(i32 %x) { 581; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3_logical( 582; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 583; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 8 584; CHECK-NEXT: ret i1 [[T5]] 585; 586 %t1 = and i32 %x, 15 587 %t2 = icmp ne i32 %t1, 0 588 %t3 = and i32 %x, 7 589 %t4 = icmp eq i32 %t3, 0 590 %t5 = select i1 %t2, i1 %t4, i1 false 591 ret i1 %t5 592} 593 594; ((X & 15) != 0 & (X & 3) == 0) -> no change 595define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3b(i32 %x) { 596; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3b( 597; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 598; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 599; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 600; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 0 601; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] 602; CHECK-NEXT: ret i1 [[T5]] 603; 604 %t1 = and i32 %x, 15 605 %t2 = icmp ne i32 %t1, 0 606 %t3 = and i32 %x, 3 607 %t4 = icmp eq i32 %t3, 0 608 %t5 = and i1 %t2, %t4 609 ret i1 %t5 610} 611 612define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3b_logical(i32 %x) { 613; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3b_logical( 614; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 615; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 616; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 617; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 0 618; CHECK-NEXT: [[T5:%.*]] = and i1 [[T2]], [[T4]] 619; CHECK-NEXT: ret i1 [[T5]] 620; 621 %t1 = and i32 %x, 15 622 %t2 = icmp ne i32 %t1, 0 623 %t3 = and i32 %x, 3 624 %t4 = icmp eq i32 %t3, 0 625 %t5 = select i1 %t2, i1 %t4, i1 false 626 ret i1 %t5 627} 628 629; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8 630define i1 @masked_icmps_mask_notallzeros_bmask_mixed_4(i32 %x) { 631; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_4( 632; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 633; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 634; CHECK-NEXT: ret i1 [[T4]] 635; 636 %t1 = and i32 %x, 255 637 %t2 = icmp ne i32 %t1, 0 638 %t3 = and i32 %x, 15 639 %t4 = icmp eq i32 %t3, 8 640 %t5 = and i1 %t2, %t4 641 ret i1 %t5 642} 643 644define i1 @masked_icmps_mask_notallzeros_bmask_mixed_4_logical(i32 %x) { 645; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_4_logical( 646; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 647; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 648; CHECK-NEXT: ret i1 [[T4]] 649; 650 %t1 = and i32 %x, 255 651 %t2 = icmp ne i32 %t1, 0 652 %t3 = and i32 %x, 15 653 %t4 = icmp eq i32 %t3, 8 654 %t5 = select i1 %t2, i1 %t4, i1 false 655 ret i1 %t5 656} 657 658; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8 659define i1 @masked_icmps_mask_notallzeros_bmask_mixed_5(i32 %x) { 660; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_5( 661; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 662; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 663; CHECK-NEXT: ret i1 [[T4]] 664; 665 %t1 = and i32 %x, 15 666 %t2 = icmp ne i32 %t1, 0 667 %t3 = and i32 %x, 15 668 %t4 = icmp eq i32 %t3, 8 669 %t5 = and i1 %t2, %t4 670 ret i1 %t5 671} 672 673define i1 @masked_icmps_mask_notallzeros_bmask_mixed_5_logical(i32 %x) { 674; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_5_logical( 675; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 676; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 677; CHECK-NEXT: ret i1 [[T4]] 678; 679 %t1 = and i32 %x, 15 680 %t2 = icmp ne i32 %t1, 0 681 %t3 = and i32 %x, 15 682 %t4 = icmp eq i32 %t3, 8 683 %t5 = select i1 %t2, i1 %t4, i1 false 684 ret i1 %t5 685} 686 687; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8 688define i1 @masked_icmps_mask_notallzeros_bmask_mixed_6(i32 %x) { 689; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_6( 690; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 691; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 692; CHECK-NEXT: ret i1 [[T4]] 693; 694 %t1 = and i32 %x, 12 695 %t2 = icmp ne i32 %t1, 0 696 %t3 = and i32 %x, 15 697 %t4 = icmp eq i32 %t3, 8 698 %t5 = and i1 %t2, %t4 699 ret i1 %t5 700} 701 702define i1 @masked_icmps_mask_notallzeros_bmask_mixed_6_logical(i32 %x) { 703; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_6_logical( 704; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 705; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 706; CHECK-NEXT: ret i1 [[T4]] 707; 708 %t1 = and i32 %x, 12 709 %t2 = icmp ne i32 %t1, 0 710 %t3 = and i32 %x, 15 711 %t4 = icmp eq i32 %t3, 8 712 %t5 = select i1 %t2, i1 %t4, i1 false 713 ret i1 %t5 714} 715 716; ((X & 7) != 0 & (X & 15) == 8) -> false 717define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7(i32 %x) { 718; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7( 719; CHECK-NEXT: ret i1 false 720; 721 %t1 = and i32 %x, 7 722 %t2 = icmp ne i32 %t1, 0 723 %t3 = and i32 %x, 15 724 %t4 = icmp eq i32 %t3, 8 725 %t5 = and i1 %t2, %t4 726 ret i1 %t5 727} 728 729define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7_logical(i32 %x) { 730; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7_logical( 731; CHECK-NEXT: ret i1 false 732; 733 %t1 = and i32 %x, 7 734 %t2 = icmp ne i32 %t1, 0 735 %t3 = and i32 %x, 15 736 %t4 = icmp eq i32 %t3, 8 737 %t5 = select i1 %t2, i1 %t4, i1 false 738 ret i1 %t5 739} 740 741; ((X & 6) != 0 & (X & 15) == 8) -> false 742define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7b(i32 %x) { 743; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7b( 744; CHECK-NEXT: ret i1 false 745; 746 %t1 = and i32 %x, 6 747 %t2 = icmp ne i32 %t1, 0 748 %t3 = and i32 %x, 15 749 %t4 = icmp eq i32 %t3, 8 750 %t5 = and i1 %t2, %t4 751 ret i1 %t5 752} 753 754define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7b_logical(i32 %x) { 755; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7b_logical( 756; CHECK-NEXT: ret i1 false 757; 758 %t1 = and i32 %x, 6 759 %t2 = icmp ne i32 %t1, 0 760 %t3 = and i32 %x, 15 761 %t4 = icmp eq i32 %t3, 8 762 %t5 = select i1 %t2, i1 %t4, i1 false 763 ret i1 %t5 764} 765 766; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) -> 767; no change 768define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(i32 %x) { 769; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_0( 770; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 771; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 772; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 773; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 774; CHECK-NEXT: [[T5:%.*]] = or i1 [[T2]], [[T4]] 775; CHECK-NEXT: ret i1 [[T5]] 776; 777 %t1 = and i32 %x, 12 778 %t2 = icmp eq i32 %t1, 0 779 %t3 = and i32 %x, 3 780 %t4 = icmp ne i32 %t3, 1 781 %t5 = or i1 %t2, %t4 782 ret i1 %t5 783} 784 785define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_0_logical(i32 %x) { 786; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_0_logical( 787; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 788; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 789; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 790; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 791; CHECK-NEXT: [[T5:%.*]] = or i1 [[T2]], [[T4]] 792; CHECK-NEXT: ret i1 [[T5]] 793; 794 %t1 = and i32 %x, 12 795 %t2 = icmp eq i32 %t1, 0 796 %t3 = and i32 %x, 3 797 %t4 = icmp ne i32 %t3, 1 798 %t5 = select i1 %t2, i1 true, i1 %t4 799 ret i1 %t5 800} 801 802; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) -> 803; !((X & 15) == 9) -> (X & 15) != 9 804define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(i32 %x) { 805; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1( 806; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 807; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 9 808; CHECK-NEXT: ret i1 [[T5]] 809; 810 %t1 = and i32 %x, 12 811 %t2 = icmp eq i32 %t1, 0 812 %t3 = and i32 %x, 7 813 %t4 = icmp ne i32 %t3, 1 814 %t5 = or i1 %t2, %t4 815 ret i1 %t5 816} 817 818define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1_logical(i32 %x) { 819; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1_logical( 820; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 821; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 9 822; CHECK-NEXT: ret i1 [[T5]] 823; 824 %t1 = and i32 %x, 12 825 %t2 = icmp eq i32 %t1, 0 826 %t3 = and i32 %x, 7 827 %t4 = icmp ne i32 %t3, 1 828 %t5 = select i1 %t2, i1 true, i1 %t4 829 ret i1 %t5 830} 831 832; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) -> 833; no change. 834define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(i32 %x) { 835; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b( 836; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 837; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 838; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 839; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 840; CHECK-NEXT: [[T5:%.*]] = or i1 [[T2]], [[T4]] 841; CHECK-NEXT: ret i1 [[T5]] 842; 843 %t1 = and i32 %x, 14 844 %t2 = icmp eq i32 %t1, 0 845 %t3 = and i32 %x, 3 846 %t4 = icmp ne i32 %t3, 1 847 %t5 = or i1 %t2, %t4 848 ret i1 %t5 849} 850 851define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b_logical(i32 %x) { 852; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b_logical( 853; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 854; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 855; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 856; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 857; CHECK-NEXT: [[T5:%.*]] = or i1 [[T2]], [[T4]] 858; CHECK-NEXT: ret i1 [[T5]] 859; 860 %t1 = and i32 %x, 14 861 %t2 = icmp eq i32 %t1, 0 862 %t3 = and i32 %x, 3 863 %t4 = icmp ne i32 %t3, 1 864 %t5 = select i1 %t2, i1 true, i1 %t4 865 ret i1 %t5 866} 867 868; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) -> 869; !(false) -> true 870define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(i32 %x) { 871; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_2( 872; CHECK-NEXT: ret i1 true 873; 874 %t1 = and i32 %x, 3 875 %t2 = icmp eq i32 %t1, 0 876 %t3 = and i32 %x, 7 877 %t4 = icmp ne i32 %t3, 0 878 %t5 = or i1 %t2, %t4 879 ret i1 %t5 880} 881 882define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_2_logical(i32 %x) { 883; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_2_logical( 884; CHECK-NEXT: ret i1 true 885; 886 %t1 = and i32 %x, 3 887 %t2 = icmp eq i32 %t1, 0 888 %t3 = and i32 %x, 7 889 %t4 = icmp ne i32 %t3, 0 890 %t5 = select i1 %t2, i1 true, i1 %t4 891 ret i1 %t5 892} 893 894; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) -> 895; !((X & 15) == 8) -> (X & 15) != 8 896define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(i32 %x) { 897; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3( 898; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 899; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 8 900; CHECK-NEXT: ret i1 [[T5]] 901; 902 %t1 = and i32 %x, 15 903 %t2 = icmp eq i32 %t1, 0 904 %t3 = and i32 %x, 7 905 %t4 = icmp ne i32 %t3, 0 906 %t5 = or i1 %t2, %t4 907 ret i1 %t5 908} 909 910define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3_logical(i32 %x) { 911; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3_logical( 912; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 913; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 8 914; CHECK-NEXT: ret i1 [[T5]] 915; 916 %t1 = and i32 %x, 15 917 %t2 = icmp eq i32 %t1, 0 918 %t3 = and i32 %x, 7 919 %t4 = icmp ne i32 %t3, 0 920 %t5 = select i1 %t2, i1 true, i1 %t4 921 ret i1 %t5 922} 923 924; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) -> 925; no change. 926define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(i32 %x) { 927; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b( 928; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 929; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 930; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 931; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 0 932; CHECK-NEXT: [[T5:%.*]] = or i1 [[T2]], [[T4]] 933; CHECK-NEXT: ret i1 [[T5]] 934; 935 %t1 = and i32 %x, 15 936 %t2 = icmp eq i32 %t1, 0 937 %t3 = and i32 %x, 3 938 %t4 = icmp ne i32 %t3, 0 939 %t5 = or i1 %t2, %t4 940 ret i1 %t5 941} 942 943define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b_logical(i32 %x) { 944; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b_logical( 945; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 946; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 947; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 948; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 0 949; CHECK-NEXT: [[T5:%.*]] = or i1 [[T2]], [[T4]] 950; CHECK-NEXT: ret i1 [[T5]] 951; 952 %t1 = and i32 %x, 15 953 %t2 = icmp eq i32 %t1, 0 954 %t3 = and i32 %x, 3 955 %t4 = icmp ne i32 %t3, 0 956 %t5 = select i1 %t2, i1 true, i1 %t4 957 ret i1 %t5 958} 959 960; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) -> 961; !((X & 15) == 8) -> ((X & 15) != 8) 962define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(i32 %x) { 963; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_4( 964; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 965; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 966; CHECK-NEXT: ret i1 [[T4]] 967; 968 %t1 = and i32 %x, 255 969 %t2 = icmp eq i32 %t1, 0 970 %t3 = and i32 %x, 15 971 %t4 = icmp ne i32 %t3, 8 972 %t5 = or i1 %t2, %t4 973 ret i1 %t5 974} 975 976define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_4_logical(i32 %x) { 977; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_4_logical( 978; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 979; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 980; CHECK-NEXT: ret i1 [[T4]] 981; 982 %t1 = and i32 %x, 255 983 %t2 = icmp eq i32 %t1, 0 984 %t3 = and i32 %x, 15 985 %t4 = icmp ne i32 %t3, 8 986 %t5 = select i1 %t2, i1 true, i1 %t4 987 ret i1 %t5 988} 989 990; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) -> 991; !((X & 15) == 8) -> ((X & 15) != 8) 992define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(i32 %x) { 993; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_5( 994; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 995; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 996; CHECK-NEXT: ret i1 [[T4]] 997; 998 %t1 = and i32 %x, 15 999 %t2 = icmp eq i32 %t1, 0 1000 %t3 = and i32 %x, 15 1001 %t4 = icmp ne i32 %t3, 8 1002 %t5 = or i1 %t2, %t4 1003 ret i1 %t5 1004} 1005 1006define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_5_logical(i32 %x) { 1007; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_5_logical( 1008; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1009; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1010; CHECK-NEXT: ret i1 [[T4]] 1011; 1012 %t1 = and i32 %x, 15 1013 %t2 = icmp eq i32 %t1, 0 1014 %t3 = and i32 %x, 15 1015 %t4 = icmp ne i32 %t3, 8 1016 %t5 = select i1 %t2, i1 true, i1 %t4 1017 ret i1 %t5 1018} 1019 1020; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) -> 1021; !((X & 15) == 8) -> ((X & 15) != 8 1022define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(i32 %x) { 1023; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_6( 1024; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1025; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1026; CHECK-NEXT: ret i1 [[T4]] 1027; 1028 %t1 = and i32 %x, 12 1029 %t2 = icmp eq i32 %t1, 0 1030 %t3 = and i32 %x, 15 1031 %t4 = icmp ne i32 %t3, 8 1032 %t5 = or i1 %t2, %t4 1033 ret i1 %t5 1034} 1035 1036define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_6_logical(i32 %x) { 1037; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_6_logical( 1038; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1039; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1040; CHECK-NEXT: ret i1 [[T4]] 1041; 1042 %t1 = and i32 %x, 12 1043 %t2 = icmp eq i32 %t1, 0 1044 %t3 = and i32 %x, 15 1045 %t4 = icmp ne i32 %t3, 8 1046 %t5 = select i1 %t2, i1 true, i1 %t4 1047 ret i1 %t5 1048} 1049 1050; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) -> 1051; !(false) -> true 1052define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(i32 %x) { 1053; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7( 1054; CHECK-NEXT: ret i1 true 1055; 1056 %t1 = and i32 %x, 7 1057 %t2 = icmp eq i32 %t1, 0 1058 %t3 = and i32 %x, 15 1059 %t4 = icmp ne i32 %t3, 8 1060 %t5 = or i1 %t2, %t4 1061 ret i1 %t5 1062} 1063 1064define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7_logical(i32 %x) { 1065; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7_logical( 1066; CHECK-NEXT: ret i1 true 1067; 1068 %t1 = and i32 %x, 7 1069 %t2 = icmp eq i32 %t1, 0 1070 %t3 = and i32 %x, 15 1071 %t4 = icmp ne i32 %t3, 8 1072 %t5 = select i1 %t2, i1 true, i1 %t4 1073 ret i1 %t5 1074} 1075 1076; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) -> 1077; !(false) -> true 1078define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(i32 %x) { 1079; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b( 1080; CHECK-NEXT: ret i1 true 1081; 1082 %t1 = and i32 %x, 6 1083 %t2 = icmp eq i32 %t1, 0 1084 %t3 = and i32 %x, 15 1085 %t4 = icmp ne i32 %t3, 8 1086 %t5 = or i1 %t2, %t4 1087 ret i1 %t5 1088} 1089 1090define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b_logical(i32 %x) { 1091; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b_logical( 1092; CHECK-NEXT: ret i1 true 1093; 1094 %t1 = and i32 %x, 6 1095 %t2 = icmp eq i32 %t1, 0 1096 %t3 = and i32 %x, 15 1097 %t4 = icmp ne i32 %t3, 8 1098 %t5 = select i1 %t2, i1 true, i1 %t4 1099 ret i1 %t5 1100} 1101 1102 1103; ((X & 12) != 0 & (X & 3) == 1) -> no change 1104define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(i32 %x) { 1105; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0( 1106; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 1107; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 1108; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1109; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 1110; CHECK-NEXT: [[T5:%.*]] = and i1 [[T4]], [[T2]] 1111; CHECK-NEXT: ret i1 [[T5]] 1112; 1113 %t1 = and i32 %x, 12 1114 %t2 = icmp ne i32 %t1, 0 1115 %t3 = and i32 %x, 3 1116 %t4 = icmp eq i32 %t3, 1 1117 %t5 = and i1 %t4, %t2 1118 ret i1 %t5 1119} 1120 1121define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0_logical(i32 %x) { 1122; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0_logical( 1123; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 1124; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 1125; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1126; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 1127; CHECK-NEXT: [[T5:%.*]] = and i1 [[T4]], [[T2]] 1128; CHECK-NEXT: ret i1 [[T5]] 1129; 1130 %t1 = and i32 %x, 12 1131 %t2 = icmp ne i32 %t1, 0 1132 %t3 = and i32 %x, 3 1133 %t4 = icmp eq i32 %t3, 1 1134 %t5 = select i1 %t4, i1 %t2, i1 false 1135 ret i1 %t5 1136} 1137 1138; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9 1139define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(i32 %x) { 1140; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1( 1141; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1142; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 9 1143; CHECK-NEXT: ret i1 [[T5]] 1144; 1145 %t1 = and i32 %x, 12 1146 %t2 = icmp ne i32 %t1, 0 1147 %t3 = and i32 %x, 7 1148 %t4 = icmp eq i32 %t3, 1 1149 %t5 = and i1 %t4, %t2 1150 ret i1 %t5 1151} 1152 1153define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1_logical(i32 %x) { 1154; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1_logical( 1155; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1156; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 9 1157; CHECK-NEXT: ret i1 [[T5]] 1158; 1159 %t1 = and i32 %x, 12 1160 %t2 = icmp ne i32 %t1, 0 1161 %t3 = and i32 %x, 7 1162 %t4 = icmp eq i32 %t3, 1 1163 %t5 = select i1 %t4, i1 %t2, i1 false 1164 ret i1 %t5 1165} 1166 1167; ((X & 14) != 0 & (X & 3) == 1) -> no change 1168define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(i32 %x) { 1169; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b( 1170; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 1171; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 1172; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1173; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 1174; CHECK-NEXT: [[T5:%.*]] = and i1 [[T4]], [[T2]] 1175; CHECK-NEXT: ret i1 [[T5]] 1176; 1177 %t1 = and i32 %x, 14 1178 %t2 = icmp ne i32 %t1, 0 1179 %t3 = and i32 %x, 3 1180 %t4 = icmp eq i32 %t3, 1 1181 %t5 = and i1 %t4, %t2 1182 ret i1 %t5 1183} 1184 1185define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b_logical(i32 %x) { 1186; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b_logical( 1187; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 1188; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 1189; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1190; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 1 1191; CHECK-NEXT: [[T5:%.*]] = and i1 [[T4]], [[T2]] 1192; CHECK-NEXT: ret i1 [[T5]] 1193; 1194 %t1 = and i32 %x, 14 1195 %t2 = icmp ne i32 %t1, 0 1196 %t3 = and i32 %x, 3 1197 %t4 = icmp eq i32 %t3, 1 1198 %t5 = select i1 %t4, i1 %t2, i1 false 1199 ret i1 %t5 1200} 1201 1202; ((X & 3) != 0 & (X & 7) == 0) -> false 1203define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(i32 %x) { 1204; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2( 1205; CHECK-NEXT: ret i1 false 1206; 1207 %t1 = and i32 %x, 3 1208 %t2 = icmp ne i32 %t1, 0 1209 %t3 = and i32 %x, 7 1210 %t4 = icmp eq i32 %t3, 0 1211 %t5 = and i1 %t4, %t2 1212 ret i1 %t5 1213} 1214 1215define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2_logical(i32 %x) { 1216; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2_logical( 1217; CHECK-NEXT: ret i1 false 1218; 1219 %t1 = and i32 %x, 3 1220 %t2 = icmp ne i32 %t1, 0 1221 %t3 = and i32 %x, 7 1222 %t4 = icmp eq i32 %t3, 0 1223 %t5 = select i1 %t4, i1 %t2, i1 false 1224 ret i1 %t5 1225} 1226 1227; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8 1228define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(i32 %x) { 1229; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3( 1230; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1231; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 8 1232; CHECK-NEXT: ret i1 [[T5]] 1233; 1234 %t1 = and i32 %x, 15 1235 %t2 = icmp ne i32 %t1, 0 1236 %t3 = and i32 %x, 7 1237 %t4 = icmp eq i32 %t3, 0 1238 %t5 = and i1 %t4, %t2 1239 ret i1 %t5 1240} 1241 1242define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3_logical(i32 %x) { 1243; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3_logical( 1244; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1245; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[TMP1]], 8 1246; CHECK-NEXT: ret i1 [[T5]] 1247; 1248 %t1 = and i32 %x, 15 1249 %t2 = icmp ne i32 %t1, 0 1250 %t3 = and i32 %x, 7 1251 %t4 = icmp eq i32 %t3, 0 1252 %t5 = select i1 %t4, i1 %t2, i1 false 1253 ret i1 %t5 1254} 1255 1256; ((X & 15) != 0 & (X & 3) == 0) -> no change 1257define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(i32 %x) { 1258; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b( 1259; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 1260; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 1261; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1262; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 0 1263; CHECK-NEXT: [[T5:%.*]] = and i1 [[T4]], [[T2]] 1264; CHECK-NEXT: ret i1 [[T5]] 1265; 1266 %t1 = and i32 %x, 15 1267 %t2 = icmp ne i32 %t1, 0 1268 %t3 = and i32 %x, 3 1269 %t4 = icmp eq i32 %t3, 0 1270 %t5 = and i1 %t4, %t2 1271 ret i1 %t5 1272} 1273 1274define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b_logical(i32 %x) { 1275; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b_logical( 1276; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 1277; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 1278; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1279; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 0 1280; CHECK-NEXT: [[T5:%.*]] = and i1 [[T4]], [[T2]] 1281; CHECK-NEXT: ret i1 [[T5]] 1282; 1283 %t1 = and i32 %x, 15 1284 %t2 = icmp ne i32 %t1, 0 1285 %t3 = and i32 %x, 3 1286 %t4 = icmp eq i32 %t3, 0 1287 %t5 = select i1 %t4, i1 %t2, i1 false 1288 ret i1 %t5 1289} 1290 1291; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8 1292define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(i32 %x) { 1293; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4( 1294; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1295; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 1296; CHECK-NEXT: ret i1 [[T4]] 1297; 1298 %t1 = and i32 %x, 255 1299 %t2 = icmp ne i32 %t1, 0 1300 %t3 = and i32 %x, 15 1301 %t4 = icmp eq i32 %t3, 8 1302 %t5 = and i1 %t4, %t2 1303 ret i1 %t5 1304} 1305 1306define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4_logical(i32 %x) { 1307; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4_logical( 1308; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1309; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 1310; CHECK-NEXT: ret i1 [[T4]] 1311; 1312 %t1 = and i32 %x, 255 1313 %t2 = icmp ne i32 %t1, 0 1314 %t3 = and i32 %x, 15 1315 %t4 = icmp eq i32 %t3, 8 1316 %t5 = select i1 %t4, i1 %t2, i1 false 1317 ret i1 %t5 1318} 1319 1320; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8 1321define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(i32 %x) { 1322; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5( 1323; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1324; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 1325; CHECK-NEXT: ret i1 [[T4]] 1326; 1327 %t1 = and i32 %x, 15 1328 %t2 = icmp ne i32 %t1, 0 1329 %t3 = and i32 %x, 15 1330 %t4 = icmp eq i32 %t3, 8 1331 %t5 = and i1 %t4, %t2 1332 ret i1 %t5 1333} 1334 1335define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5_logical(i32 %x) { 1336; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5_logical( 1337; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1338; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 1339; CHECK-NEXT: ret i1 [[T4]] 1340; 1341 %t1 = and i32 %x, 15 1342 %t2 = icmp ne i32 %t1, 0 1343 %t3 = and i32 %x, 15 1344 %t4 = icmp eq i32 %t3, 8 1345 %t5 = select i1 %t4, i1 %t2, i1 false 1346 ret i1 %t5 1347} 1348 1349; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8 1350define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(i32 %x) { 1351; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6( 1352; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1353; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 1354; CHECK-NEXT: ret i1 [[T4]] 1355; 1356 %t1 = and i32 %x, 12 1357 %t2 = icmp ne i32 %t1, 0 1358 %t3 = and i32 %x, 15 1359 %t4 = icmp eq i32 %t3, 8 1360 %t5 = and i1 %t4, %t2 1361 ret i1 %t5 1362} 1363 1364define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6_logical(i32 %x) { 1365; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6_logical( 1366; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1367; CHECK-NEXT: [[T4:%.*]] = icmp eq i32 [[T3]], 8 1368; CHECK-NEXT: ret i1 [[T4]] 1369; 1370 %t1 = and i32 %x, 12 1371 %t2 = icmp ne i32 %t1, 0 1372 %t3 = and i32 %x, 15 1373 %t4 = icmp eq i32 %t3, 8 1374 %t5 = select i1 %t4, i1 %t2, i1 false 1375 ret i1 %t5 1376} 1377 1378; ((X & 7) != 0 & (X & 15) == 8) -> false 1379define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(i32 %x) { 1380; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7( 1381; CHECK-NEXT: ret i1 false 1382; 1383 %t1 = and i32 %x, 7 1384 %t2 = icmp ne i32 %t1, 0 1385 %t3 = and i32 %x, 15 1386 %t4 = icmp eq i32 %t3, 8 1387 %t5 = and i1 %t4, %t2 1388 ret i1 %t5 1389} 1390 1391define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7_logical(i32 %x) { 1392; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7_logical( 1393; CHECK-NEXT: ret i1 false 1394; 1395 %t1 = and i32 %x, 7 1396 %t2 = icmp ne i32 %t1, 0 1397 %t3 = and i32 %x, 15 1398 %t4 = icmp eq i32 %t3, 8 1399 %t5 = select i1 %t4, i1 %t2, i1 false 1400 ret i1 %t5 1401} 1402 1403; ((X & 6) != 0 & (X & 15) == 8) -> false 1404define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(i32 %x) { 1405; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b( 1406; CHECK-NEXT: ret i1 false 1407; 1408 %t1 = and i32 %x, 6 1409 %t2 = icmp ne i32 %t1, 0 1410 %t3 = and i32 %x, 15 1411 %t4 = icmp eq i32 %t3, 8 1412 %t5 = and i1 %t4, %t2 1413 ret i1 %t5 1414} 1415 1416define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b_logical(i32 %x) { 1417; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b_logical( 1418; CHECK-NEXT: ret i1 false 1419; 1420 %t1 = and i32 %x, 6 1421 %t2 = icmp ne i32 %t1, 0 1422 %t3 = and i32 %x, 15 1423 %t4 = icmp eq i32 %t3, 8 1424 %t5 = select i1 %t4, i1 %t2, i1 false 1425 ret i1 %t5 1426} 1427 1428; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) -> 1429; no change 1430define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(i32 %x) { 1431; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0( 1432; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 1433; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 1434; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1435; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 1436; CHECK-NEXT: [[T5:%.*]] = or i1 [[T4]], [[T2]] 1437; CHECK-NEXT: ret i1 [[T5]] 1438; 1439 %t1 = and i32 %x, 12 1440 %t2 = icmp eq i32 %t1, 0 1441 %t3 = and i32 %x, 3 1442 %t4 = icmp ne i32 %t3, 1 1443 %t5 = or i1 %t4, %t2 1444 ret i1 %t5 1445} 1446 1447define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0_logical(i32 %x) { 1448; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0_logical( 1449; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 12 1450; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 1451; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1452; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 1453; CHECK-NEXT: [[T5:%.*]] = or i1 [[T4]], [[T2]] 1454; CHECK-NEXT: ret i1 [[T5]] 1455; 1456 %t1 = and i32 %x, 12 1457 %t2 = icmp eq i32 %t1, 0 1458 %t3 = and i32 %x, 3 1459 %t4 = icmp ne i32 %t3, 1 1460 %t5 = select i1 %t4, i1 true, i1 %t2 1461 ret i1 %t5 1462} 1463 1464; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) -> 1465; !((X & 15) == 9) -> (X & 15) != 9 1466define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(i32 %x) { 1467; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1( 1468; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1469; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 9 1470; CHECK-NEXT: ret i1 [[T5]] 1471; 1472 %t1 = and i32 %x, 12 1473 %t2 = icmp eq i32 %t1, 0 1474 %t3 = and i32 %x, 7 1475 %t4 = icmp ne i32 %t3, 1 1476 %t5 = or i1 %t4, %t2 1477 ret i1 %t5 1478} 1479 1480define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1_logical(i32 %x) { 1481; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1_logical( 1482; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1483; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 9 1484; CHECK-NEXT: ret i1 [[T5]] 1485; 1486 %t1 = and i32 %x, 12 1487 %t2 = icmp eq i32 %t1, 0 1488 %t3 = and i32 %x, 7 1489 %t4 = icmp ne i32 %t3, 1 1490 %t5 = select i1 %t4, i1 true, i1 %t2 1491 ret i1 %t5 1492} 1493 1494; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) -> 1495; no change. 1496define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(i32 %x) { 1497; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b( 1498; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 1499; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 1500; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1501; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 1502; CHECK-NEXT: [[T5:%.*]] = or i1 [[T4]], [[T2]] 1503; CHECK-NEXT: ret i1 [[T5]] 1504; 1505 %t1 = and i32 %x, 14 1506 %t2 = icmp eq i32 %t1, 0 1507 %t3 = and i32 %x, 3 1508 %t4 = icmp ne i32 %t3, 1 1509 %t5 = or i1 %t4, %t2 1510 ret i1 %t5 1511} 1512 1513define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b_logical(i32 %x) { 1514; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b_logical( 1515; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 14 1516; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 1517; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1518; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 1 1519; CHECK-NEXT: [[T5:%.*]] = or i1 [[T4]], [[T2]] 1520; CHECK-NEXT: ret i1 [[T5]] 1521; 1522 %t1 = and i32 %x, 14 1523 %t2 = icmp eq i32 %t1, 0 1524 %t3 = and i32 %x, 3 1525 %t4 = icmp ne i32 %t3, 1 1526 %t5 = select i1 %t4, i1 true, i1 %t2 1527 ret i1 %t5 1528} 1529 1530; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) -> 1531; !(false) -> true 1532define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(i32 %x) { 1533; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2( 1534; CHECK-NEXT: ret i1 true 1535; 1536 %t1 = and i32 %x, 3 1537 %t2 = icmp eq i32 %t1, 0 1538 %t3 = and i32 %x, 7 1539 %t4 = icmp ne i32 %t3, 0 1540 %t5 = or i1 %t4, %t2 1541 ret i1 %t5 1542} 1543 1544define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2_logical(i32 %x) { 1545; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2_logical( 1546; CHECK-NEXT: ret i1 true 1547; 1548 %t1 = and i32 %x, 3 1549 %t2 = icmp eq i32 %t1, 0 1550 %t3 = and i32 %x, 7 1551 %t4 = icmp ne i32 %t3, 0 1552 %t5 = select i1 %t4, i1 true, i1 %t2 1553 ret i1 %t5 1554} 1555 1556; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) -> 1557; !((X & 15) == 8) -> (X & 15) != 8 1558define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(i32 %x) { 1559; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3( 1560; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1561; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 8 1562; CHECK-NEXT: ret i1 [[T5]] 1563; 1564 %t1 = and i32 %x, 15 1565 %t2 = icmp eq i32 %t1, 0 1566 %t3 = and i32 %x, 7 1567 %t4 = icmp ne i32 %t3, 0 1568 %t5 = or i1 %t4, %t2 1569 ret i1 %t5 1570} 1571 1572define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3_logical(i32 %x) { 1573; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3_logical( 1574; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15 1575; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[TMP1]], 8 1576; CHECK-NEXT: ret i1 [[T5]] 1577; 1578 %t1 = and i32 %x, 15 1579 %t2 = icmp eq i32 %t1, 0 1580 %t3 = and i32 %x, 7 1581 %t4 = icmp ne i32 %t3, 0 1582 %t5 = select i1 %t4, i1 true, i1 %t2 1583 ret i1 %t5 1584} 1585 1586; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) -> 1587; no change. 1588define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(i32 %x) { 1589; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b( 1590; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 1591; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 1592; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1593; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 0 1594; CHECK-NEXT: [[T5:%.*]] = or i1 [[T4]], [[T2]] 1595; CHECK-NEXT: ret i1 [[T5]] 1596; 1597 %t1 = and i32 %x, 15 1598 %t2 = icmp eq i32 %t1, 0 1599 %t3 = and i32 %x, 3 1600 %t4 = icmp ne i32 %t3, 0 1601 %t5 = or i1 %t4, %t2 1602 ret i1 %t5 1603} 1604 1605define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b_logical(i32 %x) { 1606; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b_logical( 1607; CHECK-NEXT: [[T1:%.*]] = and i32 [[X:%.*]], 15 1608; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 1609; CHECK-NEXT: [[T3:%.*]] = and i32 [[X]], 3 1610; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 0 1611; CHECK-NEXT: [[T5:%.*]] = or i1 [[T4]], [[T2]] 1612; CHECK-NEXT: ret i1 [[T5]] 1613; 1614 %t1 = and i32 %x, 15 1615 %t2 = icmp eq i32 %t1, 0 1616 %t3 = and i32 %x, 3 1617 %t4 = icmp ne i32 %t3, 0 1618 %t5 = select i1 %t4, i1 true, i1 %t2 1619 ret i1 %t5 1620} 1621 1622; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) -> 1623; !((X & 15) == 8) -> ((X & 15) != 8) 1624define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(i32 %x) { 1625; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4( 1626; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1627; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1628; CHECK-NEXT: ret i1 [[T4]] 1629; 1630 %t1 = and i32 %x, 255 1631 %t2 = icmp eq i32 %t1, 0 1632 %t3 = and i32 %x, 15 1633 %t4 = icmp ne i32 %t3, 8 1634 %t5 = or i1 %t4, %t2 1635 ret i1 %t5 1636} 1637 1638define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4_logical(i32 %x) { 1639; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4_logical( 1640; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1641; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1642; CHECK-NEXT: ret i1 [[T4]] 1643; 1644 %t1 = and i32 %x, 255 1645 %t2 = icmp eq i32 %t1, 0 1646 %t3 = and i32 %x, 15 1647 %t4 = icmp ne i32 %t3, 8 1648 %t5 = select i1 %t4, i1 true, i1 %t2 1649 ret i1 %t5 1650} 1651 1652; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) -> 1653; !((X & 15) == 8) -> ((X & 15) != 8) 1654define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(i32 %x) { 1655; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5( 1656; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1657; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1658; CHECK-NEXT: ret i1 [[T4]] 1659; 1660 %t1 = and i32 %x, 15 1661 %t2 = icmp eq i32 %t1, 0 1662 %t3 = and i32 %x, 15 1663 %t4 = icmp ne i32 %t3, 8 1664 %t5 = or i1 %t4, %t2 1665 ret i1 %t5 1666} 1667 1668define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5_logical(i32 %x) { 1669; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5_logical( 1670; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1671; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1672; CHECK-NEXT: ret i1 [[T4]] 1673; 1674 %t1 = and i32 %x, 15 1675 %t2 = icmp eq i32 %t1, 0 1676 %t3 = and i32 %x, 15 1677 %t4 = icmp ne i32 %t3, 8 1678 %t5 = select i1 %t4, i1 true, i1 %t2 1679 ret i1 %t5 1680} 1681 1682; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) -> 1683; !((X & 15) == 8) -> ((X & 15) != 8 1684define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(i32 %x) { 1685; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6( 1686; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1687; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1688; CHECK-NEXT: ret i1 [[T4]] 1689; 1690 %t1 = and i32 %x, 12 1691 %t2 = icmp eq i32 %t1, 0 1692 %t3 = and i32 %x, 15 1693 %t4 = icmp ne i32 %t3, 8 1694 %t5 = or i1 %t4, %t2 1695 ret i1 %t5 1696} 1697 1698define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6_logical(i32 %x) { 1699; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6_logical( 1700; CHECK-NEXT: [[T3:%.*]] = and i32 [[X:%.*]], 15 1701; CHECK-NEXT: [[T4:%.*]] = icmp ne i32 [[T3]], 8 1702; CHECK-NEXT: ret i1 [[T4]] 1703; 1704 %t1 = and i32 %x, 12 1705 %t2 = icmp eq i32 %t1, 0 1706 %t3 = and i32 %x, 15 1707 %t4 = icmp ne i32 %t3, 8 1708 %t5 = select i1 %t4, i1 true, i1 %t2 1709 ret i1 %t5 1710} 1711 1712; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) -> 1713; !(false) -> true 1714define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(i32 %x) { 1715; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7( 1716; CHECK-NEXT: ret i1 true 1717; 1718 %t1 = and i32 %x, 7 1719 %t2 = icmp eq i32 %t1, 0 1720 %t3 = and i32 %x, 15 1721 %t4 = icmp ne i32 %t3, 8 1722 %t5 = or i1 %t4, %t2 1723 ret i1 %t5 1724} 1725 1726define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7_logical(i32 %x) { 1727; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7_logical( 1728; CHECK-NEXT: ret i1 true 1729; 1730 %t1 = and i32 %x, 7 1731 %t2 = icmp eq i32 %t1, 0 1732 %t3 = and i32 %x, 15 1733 %t4 = icmp ne i32 %t3, 8 1734 %t5 = select i1 %t4, i1 true, i1 %t2 1735 ret i1 %t5 1736} 1737 1738; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) -> 1739; !(false) -> true 1740define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(i32 %x) { 1741; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b( 1742; CHECK-NEXT: ret i1 true 1743; 1744 %t1 = and i32 %x, 6 1745 %t2 = icmp eq i32 %t1, 0 1746 %t3 = and i32 %x, 15 1747 %t4 = icmp ne i32 %t3, 8 1748 %t5 = or i1 %t4, %t2 1749 ret i1 %t5 1750} 1751 1752define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b_logical(i32 %x) { 1753; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b_logical( 1754; CHECK-NEXT: ret i1 true 1755; 1756 %t1 = and i32 %x, 6 1757 %t2 = icmp eq i32 %t1, 0 1758 %t3 = and i32 %x, 15 1759 %t4 = icmp ne i32 %t3, 8 1760 %t5 = select i1 %t4, i1 true, i1 %t2 1761 ret i1 %t5 1762} 1763 1764 1765define i1 @masked_icmps_bmask_notmixed_or(i32 %A) { 1766; CHECK-LABEL: @masked_icmps_bmask_notmixed_or( 1767; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15 1768; CHECK-NEXT: [[RES:%.*]] = icmp eq i32 [[TMP1]], 3 1769; CHECK-NEXT: ret i1 [[RES]] 1770; 1771 %mask1 = and i32 %A, 15 ; 0x0f 1772 %tst1 = icmp eq i32 %mask1, 3 ; 0x03 1773 %mask2 = and i32 %A, 255 ; 0xff 1774 %tst2 = icmp eq i32 %mask2, 243; 0xf3 1775 %res = or i1 %tst1, %tst2 1776 ret i1 %res 1777} 1778 1779define <2 x i1> @masked_icmps_bmask_notmixed_or_vec(<2 x i8> %A) { 1780; CHECK-LABEL: @masked_icmps_bmask_notmixed_or_vec( 1781; CHECK-NEXT: [[MASK1:%.*]] = and <2 x i8> [[A:%.*]], splat (i8 15) 1782; CHECK-NEXT: [[RES:%.*]] = icmp eq <2 x i8> [[MASK1]], splat (i8 3) 1783; CHECK-NEXT: ret <2 x i1> [[RES]] 1784; 1785 %mask1 = and <2 x i8> %A, <i8 15, i8 15> ; 0x0f 1786 %tst1 = icmp eq <2 x i8> %mask1, <i8 3, i8 3> ; 0x03 1787 %mask2 = and <2 x i8> %A, <i8 255, i8 255> ; 0xff 1788 %tst2 = icmp eq <2 x i8> %mask2, <i8 243, i8 243> ; 0xf3 1789 %res = or <2 x i1> %tst1, %tst2 1790 ret <2 x i1> %res 1791} 1792 1793define <2 x i1> @masked_icmps_bmask_notmixed_or_vec_poison1(<2 x i8> %A) { 1794; CHECK-LABEL: @masked_icmps_bmask_notmixed_or_vec_poison1( 1795; CHECK-NEXT: [[MASK1:%.*]] = and <2 x i8> [[A:%.*]], splat (i8 15) 1796; CHECK-NEXT: [[TST1:%.*]] = icmp eq <2 x i8> [[MASK1]], <i8 3, i8 poison> 1797; CHECK-NEXT: [[TST2:%.*]] = icmp eq <2 x i8> [[A]], splat (i8 -13) 1798; CHECK-NEXT: [[RES:%.*]] = or <2 x i1> [[TST1]], [[TST2]] 1799; CHECK-NEXT: ret <2 x i1> [[RES]] 1800; 1801 %mask1 = and <2 x i8> %A, <i8 15, i8 15> ; 0x0f 1802 %tst1 = icmp eq <2 x i8> %mask1, <i8 3, i8 poison> ; 0x03 1803 %mask2 = and <2 x i8> %A, <i8 255, i8 255> ; 0xff 1804 %tst2 = icmp eq <2 x i8> %mask2, <i8 243, i8 243> ; 0xf3 1805 %res = or <2 x i1> %tst1, %tst2 1806 ret <2 x i1> %res 1807} 1808 1809define <2 x i1> @masked_icmps_bmask_notmixed_or_vec_poison2(<2 x i8> %A) { 1810; CHECK-LABEL: @masked_icmps_bmask_notmixed_or_vec_poison2( 1811; CHECK-NEXT: [[MASK1:%.*]] = and <2 x i8> [[A:%.*]], splat (i8 15) 1812; CHECK-NEXT: [[TST1:%.*]] = icmp eq <2 x i8> [[MASK1]], splat (i8 3) 1813; CHECK-NEXT: [[TST2:%.*]] = icmp eq <2 x i8> [[A]], <i8 -13, i8 poison> 1814; CHECK-NEXT: [[RES:%.*]] = or <2 x i1> [[TST1]], [[TST2]] 1815; CHECK-NEXT: ret <2 x i1> [[RES]] 1816; 1817 %mask1 = and <2 x i8> %A, <i8 15, i8 15> ; 0x0f 1818 %tst1 = icmp eq <2 x i8> %mask1, <i8 3, i8 3> ; 0x03 1819 %mask2 = and <2 x i8> %A, <i8 255, i8 255> ; 0xff 1820 %tst2 = icmp eq <2 x i8> %mask2, <i8 243, i8 poison> ; 0xf3 1821 %res = or <2 x i1> %tst1, %tst2 1822 ret <2 x i1> %res 1823} 1824 1825define i1 @masked_icmps_bmask_notmixed_or_contradict_notoptimized(i32 %A) { 1826; CHECK-LABEL: @masked_icmps_bmask_notmixed_or_contradict_notoptimized( 1827; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15 1828; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 3 1829; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 255 1830; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], 242 1831; CHECK-NEXT: [[RES:%.*]] = or i1 [[TST1]], [[TST2]] 1832; CHECK-NEXT: ret i1 [[RES]] 1833; 1834 %mask1 = and i32 %A, 15 ; 0x0f 1835 %tst1 = icmp eq i32 %mask1, 3 ; 0x03 1836 %mask2 = and i32 %A, 255 ; 0xff 1837 %tst2 = icmp eq i32 %mask2, 242; 0xf2 1838 %res = or i1 %tst1, %tst2 1839 ret i1 %res 1840} 1841 1842define i1 @masked_icmps_bmask_notmixed_and(i32 %A) { 1843; CHECK-LABEL: @masked_icmps_bmask_notmixed_and( 1844; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 15 1845; CHECK-NEXT: [[RES:%.*]] = icmp ne i32 [[TMP1]], 3 1846; CHECK-NEXT: ret i1 [[RES]] 1847; 1848 %mask1 = and i32 %A, 15 ; 0x0f 1849 %tst1 = icmp ne i32 %mask1, 3 ; 0x03 1850 %mask2 = and i32 %A, 255 ; 0xff 1851 %tst2 = icmp ne i32 %mask2, 243 ; 0xf3 1852 %res = and i1 %tst1, %tst2 1853 ret i1 %res 1854} 1855 1856define i1 @masked_icmps_bmask_notmixed_and_contradict_notoptimized(i32 %A) { 1857; CHECK-LABEL: @masked_icmps_bmask_notmixed_and_contradict_notoptimized( 1858; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15 1859; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 3 1860; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 255 1861; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], 242 1862; CHECK-NEXT: [[RES:%.*]] = and i1 [[TST1]], [[TST2]] 1863; CHECK-NEXT: ret i1 [[RES]] 1864; 1865 %mask1 = and i32 %A, 15 ; 0x0f 1866 %tst1 = icmp ne i32 %mask1, 3 ; 0x03 1867 %mask2 = and i32 %A, 255 ; 0xff 1868 %tst2 = icmp ne i32 %mask2, 242 ; 0xf2 1869 %res = and i1 %tst1, %tst2 1870 ret i1 %res 1871} 1872 1873define i1 @masked_icmps_bmask_notmixed_and_expected_false(i32 %A) { 1874; CHECK-LABEL: @masked_icmps_bmask_notmixed_and_expected_false( 1875; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A:%.*]], 255 1876; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], 242 1877; CHECK-NEXT: ret i1 [[TST2]] 1878; 1879 %mask1 = and i32 %A, 3 ; 0x0f 1880 %tst1 = icmp ne i32 %mask1, 15 ; 0x03 1881 %mask2 = and i32 %A, 255 ; 0xff 1882 %tst2 = icmp ne i32 %mask2, 242 ; 0xf2 1883 %res = and i1 %tst1, %tst2 1884 ret i1 %res 1885} 1886 1887define i1 @masked_icmps_bmask_notmixed_not_subset_notoptimized(i32 %A) { 1888; CHECK-LABEL: @masked_icmps_bmask_notmixed_not_subset_notoptimized( 1889; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 254 1890; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 252 1891; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 253 1892; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], 252 1893; CHECK-NEXT: [[RES:%.*]] = and i1 [[TST1]], [[TST2]] 1894; CHECK-NEXT: ret i1 [[RES]] 1895; 1896 %mask1 = and i32 %A, 254 ; 0xfe 1897 %tst1 = icmp ne i32 %mask1, 252 ; 0xfc 1898 %mask2 = and i32 %A, 253 ; 0xfd 1899 %tst2 = icmp ne i32 %mask2, 252 ; 0xfc 1900 %res = and i1 %tst1, %tst2 1901 ret i1 %res 1902} 1903 1904define i1 @pr120361(i8 %x, i8 %y) { 1905; CHECK-LABEL: @pr120361( 1906; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i8 [[X:%.*]], -1 1907; CHECK-NEXT: ret i1 [[CMP1]] 1908; 1909 %cmp1 = icmp samesign eq i8 %x, -1 1910 %cmp2 = icmp ne i8 %x, 0 1911 %result = select i1 %cmp2, i1 %cmp1, i1 false 1912 ret i1 %result 1913} 1914 1915define i1 @pr120361_v2(i32 %x) { 1916; CHECK-LABEL: @pr120361_v2( 1917; CHECK-NEXT: [[AND2:%.*]] = and i32 [[X:%.*]], -113 1918; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 15 1919; CHECK-NEXT: ret i1 [[CMP2]] 1920; 1921 %and1 = and i32 %x, 15 1922 %cmp1 = icmp ne i32 %and1, 0 1923 %and2 = and i32 %x, -113 1924 %cmp2 = icmp samesign eq i32 %and2, 15 1925 %and = select i1 %cmp1, i1 %cmp2, i1 false 1926 ret i1 %and 1927} 1928