1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=instcombine -S < %s | FileCheck %s 3 4; PR5438 5 6define i32 @test1(i32 %a, i32 %b) nounwind readnone { 7; CHECK-LABEL: @test1( 8; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]] 9; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[TMP1]], -1 10; CHECK-NEXT: [[T3:%.*]] = zext i1 [[T2]] to i32 11; CHECK-NEXT: ret i32 [[T3]] 12; 13 %t0 = icmp sgt i32 %a, -1 14 %t1 = icmp slt i32 %b, 0 15 %t2 = xor i1 %t1, %t0 16 %t3 = zext i1 %t2 to i32 17 ret i32 %t3 18} 19 20; TODO: This optimizes partially but not all the way. 21define i32 @test2(i32 %a, i32 %b) nounwind readnone { 22; CHECK-LABEL: @test2( 23; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] 24; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 3 25; CHECK-NEXT: [[DOTLOBIT:%.*]] = and i32 [[TMP2]], 1 26; CHECK-NEXT: [[T3:%.*]] = xor i32 [[DOTLOBIT]], 1 27; CHECK-NEXT: ret i32 [[T3]] 28; 29 %t0 = and i32 %a, 8 30 %t1 = and i32 %b, 8 31 %t2 = icmp eq i32 %t0, %t1 32 %t3 = zext i1 %t2 to i32 33 ret i32 %t3 34} 35 36define i32 @test3(i32 %a, i32 %b) nounwind readnone { 37; CHECK-LABEL: @test3( 38; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] 39; CHECK-NEXT: [[T2:%.*]] = icmp sgt i32 [[T2_UNSHIFTED]], -1 40; CHECK-NEXT: [[T3:%.*]] = zext i1 [[T2]] to i32 41; CHECK-NEXT: ret i32 [[T3]] 42; 43 %t0 = lshr i32 %a, 31 44 %t1 = lshr i32 %b, 31 45 %t2 = icmp eq i32 %t0, %t1 46 %t3 = zext i1 %t2 to i32 47 ret i32 %t3 48} 49 50define <2 x i32> @test3vec(<2 x i32> %a, <2 x i32> %b) nounwind readnone { 51; CHECK-LABEL: @test3vec( 52; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]] 53; CHECK-NEXT: [[T2:%.*]] = icmp sgt <2 x i32> [[T2_UNSHIFTED]], splat (i32 -1) 54; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32> 55; CHECK-NEXT: ret <2 x i32> [[T3]] 56; 57 %t0 = lshr <2 x i32> %a, <i32 31, i32 31> 58 %t1 = lshr <2 x i32> %b, <i32 31, i32 31> 59 %t2 = icmp eq <2 x i32> %t0, %t1 60 %t3 = zext <2 x i1> %t2 to <2 x i32> 61 ret <2 x i32> %t3 62} 63 64define <2 x i32> @test3vec_poison1(<2 x i32> %a, <2 x i32> %b) nounwind readnone { 65; CHECK-LABEL: @test3vec_poison1( 66; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]] 67; CHECK-NEXT: [[T2:%.*]] = icmp ult <2 x i32> [[T2_UNSHIFTED]], splat (i32 16777216) 68; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32> 69; CHECK-NEXT: ret <2 x i32> [[T3]] 70; 71 %t0 = lshr <2 x i32> %a, <i32 24, i32 poison> 72 %t1 = lshr <2 x i32> %b, <i32 24, i32 24> 73 %t2 = icmp eq <2 x i32> %t0, %t1 74 %t3 = zext <2 x i1> %t2 to <2 x i32> 75 ret <2 x i32> %t3 76} 77 78define <2 x i32> @test3vec_poison2(<2 x i32> %a, <2 x i32> %b) nounwind readnone { 79; CHECK-LABEL: @test3vec_poison2( 80; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor <2 x i32> [[A:%.*]], [[B:%.*]] 81; CHECK-NEXT: [[T2:%.*]] = icmp ult <2 x i32> [[T2_UNSHIFTED]], splat (i32 131072) 82; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32> 83; CHECK-NEXT: ret <2 x i32> [[T3]] 84; 85 %t0 = lshr <2 x i32> %a, <i32 poison, i32 17> 86 %t1 = lshr <2 x i32> %b, <i32 poison, i32 17> 87 %t2 = icmp eq <2 x i32> %t0, %t1 88 %t3 = zext <2 x i1> %t2 to <2 x i32> 89 ret <2 x i32> %t3 90} 91 92; negative test 93 94define <2 x i32> @test3vec_diff(<2 x i32> %a, <2 x i32> %b) nounwind readnone { 95; CHECK-LABEL: @test3vec_diff( 96; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[A:%.*]], splat (i32 31) 97; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[B:%.*]], splat (i32 30) 98; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T0]], [[T1]] 99; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32> 100; CHECK-NEXT: ret <2 x i32> [[T3]] 101; 102 %t0 = lshr <2 x i32> %a, <i32 31, i32 31> 103 %t1 = lshr <2 x i32> %b, <i32 30, i32 30> 104 %t2 = icmp eq <2 x i32> %t0, %t1 105 %t3 = zext <2 x i1> %t2 to <2 x i32> 106 ret <2 x i32> %t3 107} 108 109define <2 x i32> @test3vec_non-uniform(<2 x i32> %a, <2 x i32> %b) nounwind readnone { 110; CHECK-LABEL: @test3vec_non-uniform( 111; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 30, i32 31> 112; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[B:%.*]], <i32 30, i32 31> 113; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T0]], [[T1]] 114; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32> 115; CHECK-NEXT: ret <2 x i32> [[T3]] 116; 117 %t0 = lshr <2 x i32> %a, <i32 30, i32 31> 118 %t1 = lshr <2 x i32> %b, <i32 30, i32 31> 119 %t2 = icmp eq <2 x i32> %t0, %t1 120 %t3 = zext <2 x i1> %t2 to <2 x i32> 121 ret <2 x i32> %t3 122} 123 124; Variation on @test3: checking the 2nd bit in a situation where the 5th bit 125; is one, not zero. 126define i32 @test3i(i32 %a, i32 %b) nounwind readnone { 127; CHECK-LABEL: @test3i( 128; CHECK-NEXT: [[T01:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] 129; CHECK-NEXT: [[T4:%.*]] = icmp sgt i32 [[T01]], -1 130; CHECK-NEXT: [[T5:%.*]] = zext i1 [[T4]] to i32 131; CHECK-NEXT: ret i32 [[T5]] 132; 133 %t0 = lshr i32 %a, 29 134 %t1 = lshr i32 %b, 29 135 %t2 = or i32 %t0, 35 136 %t3 = or i32 %t1, 35 137 %t4 = icmp eq i32 %t2, %t3 138 %t5 = zext i1 %t4 to i32 139 ret i32 %t5 140} 141 142define i1 @test4a(i32 %a) { 143; CHECK-LABEL: @test4a( 144; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[A:%.*]], 1 145; CHECK-NEXT: ret i1 [[C]] 146; 147 %l = ashr i32 %a, 31 148 %na = sub i32 0, %a 149 %r = lshr i32 %na, 31 150 %signum = or i32 %l, %r 151 %c = icmp slt i32 %signum, 1 152 ret i1 %c 153} 154 155define i1 @test4a_commuted(i32 %a) { 156; CHECK-LABEL: @test4a_commuted( 157; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[SIGNUM:%.*]], 1 158; CHECK-NEXT: ret i1 [[C]] 159; 160 %l = ashr i32 %a, 31 161 %na = sub i32 0, %a 162 %r = lshr i32 %na, 31 163 %signum = or i32 %r, %l 164 %c = icmp slt i32 %signum, 1 165 ret i1 %c 166} 167 168define <2 x i1> @test4a_vec(<2 x i32> %a) { 169; CHECK-LABEL: @test4a_vec( 170; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[A:%.*]], splat (i32 1) 171; CHECK-NEXT: ret <2 x i1> [[C]] 172; 173 %l = ashr <2 x i32> %a, <i32 31, i32 31> 174 %na = sub <2 x i32> zeroinitializer, %a 175 %r = lshr <2 x i32> %na, <i32 31, i32 31> 176 %signum = or <2 x i32> %l, %r 177 %c = icmp slt <2 x i32> %signum, <i32 1, i32 1> 178 ret <2 x i1> %c 179} 180 181define i1 @test4b(i64 %a) { 182; CHECK-LABEL: @test4b( 183; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[A:%.*]], 1 184; CHECK-NEXT: ret i1 [[C]] 185; 186 %l = ashr i64 %a, 63 187 %na = sub i64 0, %a 188 %r = lshr i64 %na, 63 189 %signum = or i64 %l, %r 190 %c = icmp slt i64 %signum, 1 191 ret i1 %c 192} 193 194define i1 @test4c(i64 %a) { 195; CHECK-LABEL: @test4c( 196; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[A:%.*]], 1 197; CHECK-NEXT: ret i1 [[C]] 198; 199 %l = ashr i64 %a, 63 200 %na = sub i64 0, %a 201 %r = lshr i64 %na, 63 202 %signum = or i64 %l, %r 203 %signum.trunc = trunc i64 %signum to i32 204 %c = icmp slt i32 %signum.trunc, 1 205 ret i1 %c 206} 207 208define <2 x i1> @test4c_vec(<2 x i64> %a) { 209; CHECK-LABEL: @test4c_vec( 210; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[A:%.*]], splat (i64 1) 211; CHECK-NEXT: ret <2 x i1> [[C]] 212; 213 %l = ashr <2 x i64> %a, <i64 63, i64 63> 214 %na = sub <2 x i64> zeroinitializer, %a 215 %r = lshr <2 x i64> %na, <i64 63, i64 63> 216 %signum = or <2 x i64> %l, %r 217 %signum.trunc = trunc <2 x i64> %signum to <2 x i32> 218 %c = icmp slt <2 x i32> %signum.trunc, <i32 1, i32 1> 219 ret <2 x i1> %c 220} 221 222; PR49866 223 224define i1 @shift_trunc_signbit_test(i32 %x) { 225; CHECK-LABEL: @shift_trunc_signbit_test( 226; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[X:%.*]], 0 227; CHECK-NEXT: ret i1 [[R]] 228; 229 %sh = lshr i32 %x, 24 230 %tr = trunc i32 %sh to i8 231 %r = icmp slt i8 %tr, 0 232 ret i1 %r 233} 234 235define <2 x i1> @shift_trunc_signbit_test_vec_uses(<2 x i17> %x, ptr %p1, ptr %p2) { 236; CHECK-LABEL: @shift_trunc_signbit_test_vec_uses( 237; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i17> [[X:%.*]], splat (i17 4) 238; CHECK-NEXT: store <2 x i17> [[SH]], ptr [[P1:%.*]], align 8 239; CHECK-NEXT: [[TR:%.*]] = trunc nuw <2 x i17> [[SH]] to <2 x i13> 240; CHECK-NEXT: store <2 x i13> [[TR]], ptr [[P2:%.*]], align 4 241; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i17> [[X]], splat (i17 -1) 242; CHECK-NEXT: ret <2 x i1> [[R]] 243; 244 %sh = lshr <2 x i17> %x, <i17 4, i17 4> 245 store <2 x i17> %sh, ptr %p1 246 %tr = trunc <2 x i17> %sh to <2 x i13> 247 store <2 x i13> %tr, ptr %p2 248 %r = icmp sgt <2 x i13> %tr, <i13 -1, i13 -1> 249 ret <2 x i1> %r 250} 251 252; negative test - but this reduces with a mask op 253 254define i1 @shift_trunc_wrong_shift(i32 %x) { 255; CHECK-LABEL: @shift_trunc_wrong_shift( 256; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741824 257; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP1]], 0 258; CHECK-NEXT: ret i1 [[R]] 259; 260 %sh = lshr i32 %x, 23 261 %tr = trunc i32 %sh to i8 262 %r = icmp slt i8 %tr, 0 263 ret i1 %r 264} 265 266; negative test 267 268define i1 @shift_trunc_wrong_cmp(i32 %x) { 269; CHECK-LABEL: @shift_trunc_wrong_cmp( 270; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 24 271; CHECK-NEXT: [[TR:%.*]] = trunc nuw i32 [[SH]] to i8 272; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[TR]], 1 273; CHECK-NEXT: ret i1 [[R]] 274; 275 %sh = lshr i32 %x, 24 276 %tr = trunc i32 %sh to i8 277 %r = icmp slt i8 %tr, 1 278 ret i1 %r 279} 280