xref: /llvm-project/llvm/test/Transforms/InstCombine/and-sub-combine.ll (revision c3175c50a3cefef05046a2f78afb55028b30eb5a) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4define i8 @and_sub(i8 %a) {
5; CHECK-LABEL: @and_sub(
6; CHECK-NEXT:    [[RET:%.*]] = and i8 [[A:%.*]], 12
7; CHECK-NEXT:    ret i8 [[RET]]
8;
9  %and1 = and i8 %a, 15
10  %and2 = and i8 %a, 3
11
12  %ret = sub i8 %and1, %and2
13  ret i8 %ret
14}
15
16declare void @use(i8)
17define i8 @and_sub_multi_use(i8 %a) {
18; CHECK-LABEL: @and_sub_multi_use(
19; CHECK-NEXT:    [[AND1:%.*]] = and i8 [[A:%.*]], 15
20; CHECK-NEXT:    call void @use(i8 [[AND1]])
21; CHECK-NEXT:    [[AND2:%.*]] = and i8 [[A]], 3
22; CHECK-NEXT:    call void @use(i8 [[AND2]])
23; CHECK-NEXT:    [[RET:%.*]] = and i8 [[A]], 12
24; CHECK-NEXT:    ret i8 [[RET]]
25;
26  %and1 = and i8 %a, 15
27  call void @use(i8 %and1)
28  %and2 = and i8 %a, 3
29  call void @use(i8 %and2)
30  %ret = sub i8 %and1, %and2
31  ret i8 %ret
32}
33
34define <2 x i32> @and_sub_vec(<2 x i32> %a) {
35; CHECK-LABEL: @and_sub_vec(
36; CHECK-NEXT:    [[RET:%.*]] = and <2 x i32> [[A:%.*]], <i32 3, i32 8>
37; CHECK-NEXT:    ret <2 x i32> [[RET]]
38;
39  %and1 = and <2 x i32> %a, <i32 11, i32 10>
40  %and2 = and <2 x i32> %a, <i32 8, i32 2>
41
42  %ret = sub <2 x i32> %and1, %and2
43  ret <2 x i32> %ret
44}
45
46define <2 x i32> @and_sub_vec_posion(<2 x i32> %a) {
47; CHECK-LABEL: @and_sub_vec_posion(
48; CHECK-NEXT:    ret <2 x i32> poison
49;
50  %and1 = and <2 x i32> %a, <i32 11, i32 poison>
51  %and2 = and <2 x i32> %a, <i32 poison, i32 2>
52
53  %ret = sub <2 x i32> %and1, %and2
54  ret <2 x i32> %ret
55}
56
57define <2 x i32> @and_sub_vec_undef(<2 x i32> %a) {
58; CHECK-LABEL: @and_sub_vec_undef(
59; CHECK-NEXT:    [[AND1:%.*]] = and <2 x i32> [[A:%.*]], <i32 11, i32 undef>
60; CHECK-NEXT:    [[AND2:%.*]] = and <2 x i32> [[A]], <i32 undef, i32 2>
61; CHECK-NEXT:    [[RET:%.*]] = sub <2 x i32> [[AND1]], [[AND2]]
62; CHECK-NEXT:    ret <2 x i32> [[RET]]
63;
64  %and1 = and <2 x i32> %a, <i32 11, i32 undef>
65  %and2 = and <2 x i32> %a, <i32 undef, i32 2>
66
67  %ret = sub <2 x i32> %and1, %and2
68  ret <2 x i32> %ret
69}
70
71define i8 @and_sub_negtive(i8 %a) {
72; CHECK-LABEL: @and_sub_negtive(
73; CHECK-NEXT:    [[AND1:%.*]] = and i8 [[A:%.*]], 10
74; CHECK-NEXT:    [[AND2:%.*]] = and i8 [[A]], 9
75; CHECK-NEXT:    [[RET:%.*]] = sub nsw i8 [[AND1]], [[AND2]]
76; CHECK-NEXT:    ret i8 [[RET]]
77;
78  %and1 = and i8 %a, 10
79  %and2 = and i8 %a, 9
80
81  %ret = sub i8 %and1, %and2
82  ret i8 %ret
83}
84