xref: /llvm-project/llvm/test/Transforms/InstCombine/X86/x86-ternlog.ll (revision 38fffa630ee80163dc65e759392ad29798905679) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
3
4declare <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i32 immarg)
5declare <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i32 immarg)
6declare <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i32 immarg)
7declare <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i32 immarg)
8declare <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i32 immarg)
9declare <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i32 immarg)
10
11define <16 x i32> @vpternlog_d_v512_imm0(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
12; CHECK-LABEL: @vpternlog_d_v512_imm0(
13; CHECK-NEXT:    ret <16 x i32> zeroinitializer
14;
15  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 0)
16  ret <16 x i32> %r
17}
18
19define <2 x i64> @vpternlog_q_v128_imm1(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
20; CHECK-LABEL: @vpternlog_q_v128_imm1(
21; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 1)
22; CHECK-NEXT:    ret <2 x i64> [[R]]
23;
24  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 1)
25  ret <2 x i64> %r
26}
27
28define <8 x i32> @vpternlog_d_v256_imm2(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
29; CHECK-LABEL: @vpternlog_d_v256_imm2(
30; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 2)
31; CHECK-NEXT:    ret <8 x i32> [[R]]
32;
33  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 2)
34  ret <8 x i32> %r
35}
36
37define <8 x i64> @vpternlog_q_v512_imm3(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
38; CHECK-LABEL: @vpternlog_q_v512_imm3(
39; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 3)
40; CHECK-NEXT:    ret <8 x i64> [[R]]
41;
42  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 3)
43  ret <8 x i64> %r
44}
45
46define <4 x i32> @vpternlog_d_v128_imm4(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
47; CHECK-LABEL: @vpternlog_d_v128_imm4(
48; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 4)
49; CHECK-NEXT:    ret <4 x i32> [[R]]
50;
51  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 4)
52  ret <4 x i32> %r
53}
54
55define <4 x i64> @vpternlog_q_v256_imm5(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
56; CHECK-LABEL: @vpternlog_q_v256_imm5(
57; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 5)
58; CHECK-NEXT:    ret <4 x i64> [[R]]
59;
60  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 5)
61  ret <4 x i64> %r
62}
63
64define <16 x i32> @vpternlog_d_v512_imm6(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
65; CHECK-LABEL: @vpternlog_d_v512_imm6(
66; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 6)
67; CHECK-NEXT:    ret <16 x i32> [[R]]
68;
69  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 6)
70  ret <16 x i32> %r
71}
72
73define <2 x i64> @vpternlog_q_v128_imm7(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
74; CHECK-LABEL: @vpternlog_q_v128_imm7(
75; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 7)
76; CHECK-NEXT:    ret <2 x i64> [[R]]
77;
78  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 7)
79  ret <2 x i64> %r
80}
81
82define <8 x i32> @vpternlog_d_v256_imm8(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
83; CHECK-LABEL: @vpternlog_d_v256_imm8(
84; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 8)
85; CHECK-NEXT:    ret <8 x i32> [[R]]
86;
87  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 8)
88  ret <8 x i32> %r
89}
90
91define <8 x i64> @vpternlog_q_v512_imm9(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
92; CHECK-LABEL: @vpternlog_q_v512_imm9(
93; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 9)
94; CHECK-NEXT:    ret <8 x i64> [[R]]
95;
96  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 9)
97  ret <8 x i64> %r
98}
99
100define <4 x i32> @vpternlog_d_v128_imm10(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
101; CHECK-LABEL: @vpternlog_d_v128_imm10(
102; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 10)
103; CHECK-NEXT:    ret <4 x i32> [[R]]
104;
105  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 10)
106  ret <4 x i32> %r
107}
108
109define <4 x i64> @vpternlog_q_v256_imm11(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
110; CHECK-LABEL: @vpternlog_q_v256_imm11(
111; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 11)
112; CHECK-NEXT:    ret <4 x i64> [[R]]
113;
114  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 11)
115  ret <4 x i64> %r
116}
117
118define <16 x i32> @vpternlog_d_v512_imm12(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
119; CHECK-LABEL: @vpternlog_d_v512_imm12(
120; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 12)
121; CHECK-NEXT:    ret <16 x i32> [[R]]
122;
123  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 12)
124  ret <16 x i32> %r
125}
126
127define <2 x i64> @vpternlog_q_v128_imm13(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
128; CHECK-LABEL: @vpternlog_q_v128_imm13(
129; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 13)
130; CHECK-NEXT:    ret <2 x i64> [[R]]
131;
132  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 13)
133  ret <2 x i64> %r
134}
135
136define <8 x i32> @vpternlog_d_v256_imm14(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
137; CHECK-LABEL: @vpternlog_d_v256_imm14(
138; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 14)
139; CHECK-NEXT:    ret <8 x i32> [[R]]
140;
141  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 14)
142  ret <8 x i32> %r
143}
144
145define <8 x i64> @vpternlog_q_v512_imm15(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
146; CHECK-LABEL: @vpternlog_q_v512_imm15(
147; CHECK-NEXT:    [[R:%.*]] = xor <8 x i64> [[V0:%.*]], splat (i64 -1)
148; CHECK-NEXT:    ret <8 x i64> [[R]]
149;
150  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 15)
151  ret <8 x i64> %r
152}
153
154define <4 x i32> @vpternlog_d_v128_imm16(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
155; CHECK-LABEL: @vpternlog_d_v128_imm16(
156; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 16)
157; CHECK-NEXT:    ret <4 x i32> [[R]]
158;
159  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 16)
160  ret <4 x i32> %r
161}
162
163define <4 x i64> @vpternlog_q_v256_imm17(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
164; CHECK-LABEL: @vpternlog_q_v256_imm17(
165; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 17)
166; CHECK-NEXT:    ret <4 x i64> [[R]]
167;
168  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 17)
169  ret <4 x i64> %r
170}
171
172define <16 x i32> @vpternlog_d_v512_imm18(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
173; CHECK-LABEL: @vpternlog_d_v512_imm18(
174; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 18)
175; CHECK-NEXT:    ret <16 x i32> [[R]]
176;
177  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 18)
178  ret <16 x i32> %r
179}
180
181define <2 x i64> @vpternlog_q_v128_imm19(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
182; CHECK-LABEL: @vpternlog_q_v128_imm19(
183; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 19)
184; CHECK-NEXT:    ret <2 x i64> [[R]]
185;
186  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 19)
187  ret <2 x i64> %r
188}
189
190define <8 x i32> @vpternlog_d_v256_imm20(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
191; CHECK-LABEL: @vpternlog_d_v256_imm20(
192; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 20)
193; CHECK-NEXT:    ret <8 x i32> [[R]]
194;
195  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 20)
196  ret <8 x i32> %r
197}
198
199define <8 x i64> @vpternlog_q_v512_imm21(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
200; CHECK-LABEL: @vpternlog_q_v512_imm21(
201; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 21)
202; CHECK-NEXT:    ret <8 x i64> [[R]]
203;
204  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 21)
205  ret <8 x i64> %r
206}
207
208define <4 x i32> @vpternlog_d_v128_imm22(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
209; CHECK-LABEL: @vpternlog_d_v128_imm22(
210; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 22)
211; CHECK-NEXT:    ret <4 x i32> [[R]]
212;
213  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 22)
214  ret <4 x i32> %r
215}
216
217define <4 x i64> @vpternlog_q_v256_imm23(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
218; CHECK-LABEL: @vpternlog_q_v256_imm23(
219; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 23)
220; CHECK-NEXT:    ret <4 x i64> [[R]]
221;
222  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 23)
223  ret <4 x i64> %r
224}
225
226define <16 x i32> @vpternlog_d_v512_imm24(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
227; CHECK-LABEL: @vpternlog_d_v512_imm24(
228; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 24)
229; CHECK-NEXT:    ret <16 x i32> [[R]]
230;
231  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 24)
232  ret <16 x i32> %r
233}
234
235define <2 x i64> @vpternlog_q_v128_imm25(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
236; CHECK-LABEL: @vpternlog_q_v128_imm25(
237; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 25)
238; CHECK-NEXT:    ret <2 x i64> [[R]]
239;
240  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 25)
241  ret <2 x i64> %r
242}
243
244define <8 x i32> @vpternlog_d_v256_imm26(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
245; CHECK-LABEL: @vpternlog_d_v256_imm26(
246; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 26)
247; CHECK-NEXT:    ret <8 x i32> [[R]]
248;
249  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 26)
250  ret <8 x i32> %r
251}
252
253define <8 x i64> @vpternlog_q_v512_imm27(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
254; CHECK-LABEL: @vpternlog_q_v512_imm27(
255; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 27)
256; CHECK-NEXT:    ret <8 x i64> [[R]]
257;
258  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 27)
259  ret <8 x i64> %r
260}
261
262define <4 x i32> @vpternlog_d_v128_imm28(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
263; CHECK-LABEL: @vpternlog_d_v128_imm28(
264; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 28)
265; CHECK-NEXT:    ret <4 x i32> [[R]]
266;
267  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 28)
268  ret <4 x i32> %r
269}
270
271define <4 x i64> @vpternlog_q_v256_imm29(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
272; CHECK-LABEL: @vpternlog_q_v256_imm29(
273; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 29)
274; CHECK-NEXT:    ret <4 x i64> [[R]]
275;
276  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 29)
277  ret <4 x i64> %r
278}
279
280define <16 x i32> @vpternlog_d_v512_imm30(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
281; CHECK-LABEL: @vpternlog_d_v512_imm30(
282; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 30)
283; CHECK-NEXT:    ret <16 x i32> [[R]]
284;
285  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 30)
286  ret <16 x i32> %r
287}
288
289define <2 x i64> @vpternlog_q_v128_imm31(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
290; CHECK-LABEL: @vpternlog_q_v128_imm31(
291; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 31)
292; CHECK-NEXT:    ret <2 x i64> [[R]]
293;
294  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 31)
295  ret <2 x i64> %r
296}
297
298define <8 x i32> @vpternlog_d_v256_imm32(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
299; CHECK-LABEL: @vpternlog_d_v256_imm32(
300; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 32)
301; CHECK-NEXT:    ret <8 x i32> [[R]]
302;
303  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 32)
304  ret <8 x i32> %r
305}
306
307define <8 x i64> @vpternlog_q_v512_imm33(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
308; CHECK-LABEL: @vpternlog_q_v512_imm33(
309; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 33)
310; CHECK-NEXT:    ret <8 x i64> [[R]]
311;
312  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 33)
313  ret <8 x i64> %r
314}
315
316define <4 x i32> @vpternlog_d_v128_imm34(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
317; CHECK-LABEL: @vpternlog_d_v128_imm34(
318; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 34)
319; CHECK-NEXT:    ret <4 x i32> [[R]]
320;
321  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 34)
322  ret <4 x i32> %r
323}
324
325define <4 x i64> @vpternlog_q_v256_imm35(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
326; CHECK-LABEL: @vpternlog_q_v256_imm35(
327; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 35)
328; CHECK-NEXT:    ret <4 x i64> [[R]]
329;
330  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 35)
331  ret <4 x i64> %r
332}
333
334define <16 x i32> @vpternlog_d_v512_imm36(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
335; CHECK-LABEL: @vpternlog_d_v512_imm36(
336; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 36)
337; CHECK-NEXT:    ret <16 x i32> [[R]]
338;
339  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 36)
340  ret <16 x i32> %r
341}
342
343define <2 x i64> @vpternlog_q_v128_imm37(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
344; CHECK-LABEL: @vpternlog_q_v128_imm37(
345; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 37)
346; CHECK-NEXT:    ret <2 x i64> [[R]]
347;
348  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 37)
349  ret <2 x i64> %r
350}
351
352define <8 x i32> @vpternlog_d_v256_imm38(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
353; CHECK-LABEL: @vpternlog_d_v256_imm38(
354; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 38)
355; CHECK-NEXT:    ret <8 x i32> [[R]]
356;
357  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 38)
358  ret <8 x i32> %r
359}
360
361define <8 x i64> @vpternlog_q_v512_imm39(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
362; CHECK-LABEL: @vpternlog_q_v512_imm39(
363; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 39)
364; CHECK-NEXT:    ret <8 x i64> [[R]]
365;
366  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 39)
367  ret <8 x i64> %r
368}
369
370define <4 x i32> @vpternlog_d_v128_imm40(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
371; CHECK-LABEL: @vpternlog_d_v128_imm40(
372; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 40)
373; CHECK-NEXT:    ret <4 x i32> [[R]]
374;
375  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 40)
376  ret <4 x i32> %r
377}
378
379define <4 x i64> @vpternlog_q_v256_imm41(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
380; CHECK-LABEL: @vpternlog_q_v256_imm41(
381; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 41)
382; CHECK-NEXT:    ret <4 x i64> [[R]]
383;
384  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 41)
385  ret <4 x i64> %r
386}
387
388define <16 x i32> @vpternlog_d_v512_imm42(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
389; CHECK-LABEL: @vpternlog_d_v512_imm42(
390; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 42)
391; CHECK-NEXT:    ret <16 x i32> [[R]]
392;
393  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 42)
394  ret <16 x i32> %r
395}
396
397define <2 x i64> @vpternlog_q_v128_imm43(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
398; CHECK-LABEL: @vpternlog_q_v128_imm43(
399; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 43)
400; CHECK-NEXT:    ret <2 x i64> [[R]]
401;
402  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 43)
403  ret <2 x i64> %r
404}
405
406define <8 x i32> @vpternlog_d_v256_imm44(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
407; CHECK-LABEL: @vpternlog_d_v256_imm44(
408; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 44)
409; CHECK-NEXT:    ret <8 x i32> [[R]]
410;
411  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 44)
412  ret <8 x i32> %r
413}
414
415define <8 x i64> @vpternlog_q_v512_imm45(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
416; CHECK-LABEL: @vpternlog_q_v512_imm45(
417; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 45)
418; CHECK-NEXT:    ret <8 x i64> [[R]]
419;
420  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 45)
421  ret <8 x i64> %r
422}
423
424define <4 x i32> @vpternlog_d_v128_imm46(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
425; CHECK-LABEL: @vpternlog_d_v128_imm46(
426; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 46)
427; CHECK-NEXT:    ret <4 x i32> [[R]]
428;
429  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 46)
430  ret <4 x i32> %r
431}
432
433define <4 x i64> @vpternlog_q_v256_imm47(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
434; CHECK-LABEL: @vpternlog_q_v256_imm47(
435; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 47)
436; CHECK-NEXT:    ret <4 x i64> [[R]]
437;
438  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 47)
439  ret <4 x i64> %r
440}
441
442define <16 x i32> @vpternlog_d_v512_imm48(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
443; CHECK-LABEL: @vpternlog_d_v512_imm48(
444; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 48)
445; CHECK-NEXT:    ret <16 x i32> [[R]]
446;
447  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 48)
448  ret <16 x i32> %r
449}
450
451define <2 x i64> @vpternlog_q_v128_imm49(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
452; CHECK-LABEL: @vpternlog_q_v128_imm49(
453; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 49)
454; CHECK-NEXT:    ret <2 x i64> [[R]]
455;
456  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 49)
457  ret <2 x i64> %r
458}
459
460define <8 x i32> @vpternlog_d_v256_imm50(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
461; CHECK-LABEL: @vpternlog_d_v256_imm50(
462; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 50)
463; CHECK-NEXT:    ret <8 x i32> [[R]]
464;
465  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 50)
466  ret <8 x i32> %r
467}
468
469define <8 x i64> @vpternlog_q_v512_imm51(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
470; CHECK-LABEL: @vpternlog_q_v512_imm51(
471; CHECK-NEXT:    [[R:%.*]] = xor <8 x i64> [[V1:%.*]], splat (i64 -1)
472; CHECK-NEXT:    ret <8 x i64> [[R]]
473;
474  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 51)
475  ret <8 x i64> %r
476}
477
478define <4 x i32> @vpternlog_d_v128_imm52(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
479; CHECK-LABEL: @vpternlog_d_v128_imm52(
480; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 52)
481; CHECK-NEXT:    ret <4 x i32> [[R]]
482;
483  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 52)
484  ret <4 x i32> %r
485}
486
487define <4 x i64> @vpternlog_q_v256_imm53(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
488; CHECK-LABEL: @vpternlog_q_v256_imm53(
489; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 53)
490; CHECK-NEXT:    ret <4 x i64> [[R]]
491;
492  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 53)
493  ret <4 x i64> %r
494}
495
496define <16 x i32> @vpternlog_d_v512_imm54(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
497; CHECK-LABEL: @vpternlog_d_v512_imm54(
498; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 54)
499; CHECK-NEXT:    ret <16 x i32> [[R]]
500;
501  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 54)
502  ret <16 x i32> %r
503}
504
505define <2 x i64> @vpternlog_q_v128_imm55(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
506; CHECK-LABEL: @vpternlog_q_v128_imm55(
507; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 55)
508; CHECK-NEXT:    ret <2 x i64> [[R]]
509;
510  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 55)
511  ret <2 x i64> %r
512}
513
514define <8 x i32> @vpternlog_d_v256_imm56(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
515; CHECK-LABEL: @vpternlog_d_v256_imm56(
516; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 56)
517; CHECK-NEXT:    ret <8 x i32> [[R]]
518;
519  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 56)
520  ret <8 x i32> %r
521}
522
523define <8 x i64> @vpternlog_q_v512_imm57(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
524; CHECK-LABEL: @vpternlog_q_v512_imm57(
525; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 57)
526; CHECK-NEXT:    ret <8 x i64> [[R]]
527;
528  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 57)
529  ret <8 x i64> %r
530}
531
532define <4 x i32> @vpternlog_d_v128_imm58(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
533; CHECK-LABEL: @vpternlog_d_v128_imm58(
534; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 58)
535; CHECK-NEXT:    ret <4 x i32> [[R]]
536;
537  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 58)
538  ret <4 x i32> %r
539}
540
541define <4 x i64> @vpternlog_q_v256_imm59(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
542; CHECK-LABEL: @vpternlog_q_v256_imm59(
543; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 59)
544; CHECK-NEXT:    ret <4 x i64> [[R]]
545;
546  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 59)
547  ret <4 x i64> %r
548}
549
550define <16 x i32> @vpternlog_d_v512_imm60(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
551; CHECK-LABEL: @vpternlog_d_v512_imm60(
552; CHECK-NEXT:    [[R:%.*]] = xor <16 x i32> [[V0:%.*]], [[V1:%.*]]
553; CHECK-NEXT:    ret <16 x i32> [[R]]
554;
555  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 60)
556  ret <16 x i32> %r
557}
558
559define <2 x i64> @vpternlog_q_v128_imm61(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
560; CHECK-LABEL: @vpternlog_q_v128_imm61(
561; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 61)
562; CHECK-NEXT:    ret <2 x i64> [[R]]
563;
564  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 61)
565  ret <2 x i64> %r
566}
567
568define <8 x i32> @vpternlog_d_v256_imm62(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
569; CHECK-LABEL: @vpternlog_d_v256_imm62(
570; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 62)
571; CHECK-NEXT:    ret <8 x i32> [[R]]
572;
573  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 62)
574  ret <8 x i32> %r
575}
576
577define <8 x i64> @vpternlog_q_v512_imm63(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
578; CHECK-LABEL: @vpternlog_q_v512_imm63(
579; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 63)
580; CHECK-NEXT:    ret <8 x i64> [[R]]
581;
582  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 63)
583  ret <8 x i64> %r
584}
585
586define <4 x i32> @vpternlog_d_v128_imm64(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
587; CHECK-LABEL: @vpternlog_d_v128_imm64(
588; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 64)
589; CHECK-NEXT:    ret <4 x i32> [[R]]
590;
591  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 64)
592  ret <4 x i32> %r
593}
594
595define <4 x i64> @vpternlog_q_v256_imm65(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
596; CHECK-LABEL: @vpternlog_q_v256_imm65(
597; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 65)
598; CHECK-NEXT:    ret <4 x i64> [[R]]
599;
600  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 65)
601  ret <4 x i64> %r
602}
603
604define <16 x i32> @vpternlog_d_v512_imm66(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
605; CHECK-LABEL: @vpternlog_d_v512_imm66(
606; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 66)
607; CHECK-NEXT:    ret <16 x i32> [[R]]
608;
609  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 66)
610  ret <16 x i32> %r
611}
612
613define <2 x i64> @vpternlog_q_v128_imm67(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
614; CHECK-LABEL: @vpternlog_q_v128_imm67(
615; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 67)
616; CHECK-NEXT:    ret <2 x i64> [[R]]
617;
618  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 67)
619  ret <2 x i64> %r
620}
621
622define <8 x i32> @vpternlog_d_v256_imm68(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
623; CHECK-LABEL: @vpternlog_d_v256_imm68(
624; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 68)
625; CHECK-NEXT:    ret <8 x i32> [[R]]
626;
627  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 68)
628  ret <8 x i32> %r
629}
630
631define <8 x i64> @vpternlog_q_v512_imm69(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
632; CHECK-LABEL: @vpternlog_q_v512_imm69(
633; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 69)
634; CHECK-NEXT:    ret <8 x i64> [[R]]
635;
636  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 69)
637  ret <8 x i64> %r
638}
639
640define <4 x i32> @vpternlog_d_v128_imm70(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
641; CHECK-LABEL: @vpternlog_d_v128_imm70(
642; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 70)
643; CHECK-NEXT:    ret <4 x i32> [[R]]
644;
645  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 70)
646  ret <4 x i32> %r
647}
648
649define <4 x i64> @vpternlog_q_v256_imm71(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
650; CHECK-LABEL: @vpternlog_q_v256_imm71(
651; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 71)
652; CHECK-NEXT:    ret <4 x i64> [[R]]
653;
654  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 71)
655  ret <4 x i64> %r
656}
657
658define <16 x i32> @vpternlog_d_v512_imm72(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
659; CHECK-LABEL: @vpternlog_d_v512_imm72(
660; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 72)
661; CHECK-NEXT:    ret <16 x i32> [[R]]
662;
663  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 72)
664  ret <16 x i32> %r
665}
666
667define <2 x i64> @vpternlog_q_v128_imm73(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
668; CHECK-LABEL: @vpternlog_q_v128_imm73(
669; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 73)
670; CHECK-NEXT:    ret <2 x i64> [[R]]
671;
672  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 73)
673  ret <2 x i64> %r
674}
675
676define <8 x i32> @vpternlog_d_v256_imm74(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
677; CHECK-LABEL: @vpternlog_d_v256_imm74(
678; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 74)
679; CHECK-NEXT:    ret <8 x i32> [[R]]
680;
681  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 74)
682  ret <8 x i32> %r
683}
684
685define <8 x i64> @vpternlog_q_v512_imm75(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
686; CHECK-LABEL: @vpternlog_q_v512_imm75(
687; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 75)
688; CHECK-NEXT:    ret <8 x i64> [[R]]
689;
690  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 75)
691  ret <8 x i64> %r
692}
693
694define <4 x i32> @vpternlog_d_v128_imm76(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
695; CHECK-LABEL: @vpternlog_d_v128_imm76(
696; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 76)
697; CHECK-NEXT:    ret <4 x i32> [[R]]
698;
699  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 76)
700  ret <4 x i32> %r
701}
702
703define <4 x i64> @vpternlog_q_v256_imm77(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
704; CHECK-LABEL: @vpternlog_q_v256_imm77(
705; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 77)
706; CHECK-NEXT:    ret <4 x i64> [[R]]
707;
708  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 77)
709  ret <4 x i64> %r
710}
711
712define <16 x i32> @vpternlog_d_v512_imm78(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
713; CHECK-LABEL: @vpternlog_d_v512_imm78(
714; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 78)
715; CHECK-NEXT:    ret <16 x i32> [[R]]
716;
717  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 78)
718  ret <16 x i32> %r
719}
720
721define <2 x i64> @vpternlog_q_v128_imm79(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
722; CHECK-LABEL: @vpternlog_q_v128_imm79(
723; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 79)
724; CHECK-NEXT:    ret <2 x i64> [[R]]
725;
726  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 79)
727  ret <2 x i64> %r
728}
729
730define <8 x i32> @vpternlog_d_v256_imm80(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
731; CHECK-LABEL: @vpternlog_d_v256_imm80(
732; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 80)
733; CHECK-NEXT:    ret <8 x i32> [[R]]
734;
735  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 80)
736  ret <8 x i32> %r
737}
738
739define <8 x i64> @vpternlog_q_v512_imm81(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
740; CHECK-LABEL: @vpternlog_q_v512_imm81(
741; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 81)
742; CHECK-NEXT:    ret <8 x i64> [[R]]
743;
744  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 81)
745  ret <8 x i64> %r
746}
747
748define <4 x i32> @vpternlog_d_v128_imm82(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
749; CHECK-LABEL: @vpternlog_d_v128_imm82(
750; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 82)
751; CHECK-NEXT:    ret <4 x i32> [[R]]
752;
753  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 82)
754  ret <4 x i32> %r
755}
756
757define <4 x i64> @vpternlog_q_v256_imm83(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
758; CHECK-LABEL: @vpternlog_q_v256_imm83(
759; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 83)
760; CHECK-NEXT:    ret <4 x i64> [[R]]
761;
762  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 83)
763  ret <4 x i64> %r
764}
765
766define <16 x i32> @vpternlog_d_v512_imm84(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
767; CHECK-LABEL: @vpternlog_d_v512_imm84(
768; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 84)
769; CHECK-NEXT:    ret <16 x i32> [[R]]
770;
771  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 84)
772  ret <16 x i32> %r
773}
774
775define <2 x i64> @vpternlog_q_v128_imm85(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
776; CHECK-LABEL: @vpternlog_q_v128_imm85(
777; CHECK-NEXT:    [[R:%.*]] = xor <2 x i64> [[V2:%.*]], splat (i64 -1)
778; CHECK-NEXT:    ret <2 x i64> [[R]]
779;
780  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 85)
781  ret <2 x i64> %r
782}
783
784define <8 x i32> @vpternlog_d_v256_imm86(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
785; CHECK-LABEL: @vpternlog_d_v256_imm86(
786; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 86)
787; CHECK-NEXT:    ret <8 x i32> [[R]]
788;
789  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 86)
790  ret <8 x i32> %r
791}
792
793define <8 x i64> @vpternlog_q_v512_imm87(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
794; CHECK-LABEL: @vpternlog_q_v512_imm87(
795; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 87)
796; CHECK-NEXT:    ret <8 x i64> [[R]]
797;
798  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 87)
799  ret <8 x i64> %r
800}
801
802define <4 x i32> @vpternlog_d_v128_imm88(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
803; CHECK-LABEL: @vpternlog_d_v128_imm88(
804; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 88)
805; CHECK-NEXT:    ret <4 x i32> [[R]]
806;
807  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 88)
808  ret <4 x i32> %r
809}
810
811define <4 x i64> @vpternlog_q_v256_imm89(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
812; CHECK-LABEL: @vpternlog_q_v256_imm89(
813; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 89)
814; CHECK-NEXT:    ret <4 x i64> [[R]]
815;
816  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 89)
817  ret <4 x i64> %r
818}
819
820define <16 x i32> @vpternlog_d_v512_imm90(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
821; CHECK-LABEL: @vpternlog_d_v512_imm90(
822; CHECK-NEXT:    [[R:%.*]] = xor <16 x i32> [[V0:%.*]], [[V2:%.*]]
823; CHECK-NEXT:    ret <16 x i32> [[R]]
824;
825  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 90)
826  ret <16 x i32> %r
827}
828
829define <2 x i64> @vpternlog_q_v128_imm91(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
830; CHECK-LABEL: @vpternlog_q_v128_imm91(
831; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 91)
832; CHECK-NEXT:    ret <2 x i64> [[R]]
833;
834  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 91)
835  ret <2 x i64> %r
836}
837
838define <8 x i32> @vpternlog_d_v256_imm92(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
839; CHECK-LABEL: @vpternlog_d_v256_imm92(
840; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 92)
841; CHECK-NEXT:    ret <8 x i32> [[R]]
842;
843  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 92)
844  ret <8 x i32> %r
845}
846
847define <8 x i64> @vpternlog_q_v512_imm93(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
848; CHECK-LABEL: @vpternlog_q_v512_imm93(
849; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 93)
850; CHECK-NEXT:    ret <8 x i64> [[R]]
851;
852  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 93)
853  ret <8 x i64> %r
854}
855
856define <4 x i32> @vpternlog_d_v128_imm94(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
857; CHECK-LABEL: @vpternlog_d_v128_imm94(
858; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 94)
859; CHECK-NEXT:    ret <4 x i32> [[R]]
860;
861  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 94)
862  ret <4 x i32> %r
863}
864
865define <4 x i64> @vpternlog_q_v256_imm95(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
866; CHECK-LABEL: @vpternlog_q_v256_imm95(
867; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 95)
868; CHECK-NEXT:    ret <4 x i64> [[R]]
869;
870  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 95)
871  ret <4 x i64> %r
872}
873
874define <16 x i32> @vpternlog_d_v512_imm96(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
875; CHECK-LABEL: @vpternlog_d_v512_imm96(
876; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 96)
877; CHECK-NEXT:    ret <16 x i32> [[R]]
878;
879  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 96)
880  ret <16 x i32> %r
881}
882
883define <2 x i64> @vpternlog_q_v128_imm97(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
884; CHECK-LABEL: @vpternlog_q_v128_imm97(
885; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 97)
886; CHECK-NEXT:    ret <2 x i64> [[R]]
887;
888  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 97)
889  ret <2 x i64> %r
890}
891
892define <8 x i32> @vpternlog_d_v256_imm98(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
893; CHECK-LABEL: @vpternlog_d_v256_imm98(
894; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 98)
895; CHECK-NEXT:    ret <8 x i32> [[R]]
896;
897  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 98)
898  ret <8 x i32> %r
899}
900
901define <8 x i64> @vpternlog_q_v512_imm99(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
902; CHECK-LABEL: @vpternlog_q_v512_imm99(
903; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 99)
904; CHECK-NEXT:    ret <8 x i64> [[R]]
905;
906  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 99)
907  ret <8 x i64> %r
908}
909
910define <4 x i32> @vpternlog_d_v128_imm100(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
911; CHECK-LABEL: @vpternlog_d_v128_imm100(
912; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 100)
913; CHECK-NEXT:    ret <4 x i32> [[R]]
914;
915  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 100)
916  ret <4 x i32> %r
917}
918
919define <4 x i64> @vpternlog_q_v256_imm101(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
920; CHECK-LABEL: @vpternlog_q_v256_imm101(
921; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 101)
922; CHECK-NEXT:    ret <4 x i64> [[R]]
923;
924  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 101)
925  ret <4 x i64> %r
926}
927
928define <16 x i32> @vpternlog_d_v512_imm102(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
929; CHECK-LABEL: @vpternlog_d_v512_imm102(
930; CHECK-NEXT:    [[R:%.*]] = xor <16 x i32> [[V1:%.*]], [[V2:%.*]]
931; CHECK-NEXT:    ret <16 x i32> [[R]]
932;
933  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 102)
934  ret <16 x i32> %r
935}
936
937define <2 x i64> @vpternlog_q_v128_imm103(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
938; CHECK-LABEL: @vpternlog_q_v128_imm103(
939; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 103)
940; CHECK-NEXT:    ret <2 x i64> [[R]]
941;
942  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 103)
943  ret <2 x i64> %r
944}
945
946define <8 x i32> @vpternlog_d_v256_imm104(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
947; CHECK-LABEL: @vpternlog_d_v256_imm104(
948; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 104)
949; CHECK-NEXT:    ret <8 x i32> [[R]]
950;
951  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 104)
952  ret <8 x i32> %r
953}
954
955define <8 x i64> @vpternlog_q_v512_imm105(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
956; CHECK-LABEL: @vpternlog_q_v512_imm105(
957; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 105)
958; CHECK-NEXT:    ret <8 x i64> [[R]]
959;
960  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 105)
961  ret <8 x i64> %r
962}
963
964define <4 x i32> @vpternlog_d_v128_imm106(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
965; CHECK-LABEL: @vpternlog_d_v128_imm106(
966; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 106)
967; CHECK-NEXT:    ret <4 x i32> [[R]]
968;
969  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 106)
970  ret <4 x i32> %r
971}
972
973define <4 x i64> @vpternlog_q_v256_imm107(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
974; CHECK-LABEL: @vpternlog_q_v256_imm107(
975; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 107)
976; CHECK-NEXT:    ret <4 x i64> [[R]]
977;
978  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 107)
979  ret <4 x i64> %r
980}
981
982define <16 x i32> @vpternlog_d_v512_imm108(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
983; CHECK-LABEL: @vpternlog_d_v512_imm108(
984; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 108)
985; CHECK-NEXT:    ret <16 x i32> [[R]]
986;
987  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 108)
988  ret <16 x i32> %r
989}
990
991define <2 x i64> @vpternlog_q_v128_imm109(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
992; CHECK-LABEL: @vpternlog_q_v128_imm109(
993; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 109)
994; CHECK-NEXT:    ret <2 x i64> [[R]]
995;
996  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 109)
997  ret <2 x i64> %r
998}
999
1000define <8 x i32> @vpternlog_d_v256_imm110(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1001; CHECK-LABEL: @vpternlog_d_v256_imm110(
1002; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 110)
1003; CHECK-NEXT:    ret <8 x i32> [[R]]
1004;
1005  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 110)
1006  ret <8 x i32> %r
1007}
1008
1009define <8 x i64> @vpternlog_q_v512_imm111(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1010; CHECK-LABEL: @vpternlog_q_v512_imm111(
1011; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 111)
1012; CHECK-NEXT:    ret <8 x i64> [[R]]
1013;
1014  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 111)
1015  ret <8 x i64> %r
1016}
1017
1018define <4 x i32> @vpternlog_d_v128_imm112(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1019; CHECK-LABEL: @vpternlog_d_v128_imm112(
1020; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 112)
1021; CHECK-NEXT:    ret <4 x i32> [[R]]
1022;
1023  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 112)
1024  ret <4 x i32> %r
1025}
1026
1027define <4 x i64> @vpternlog_q_v256_imm113(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1028; CHECK-LABEL: @vpternlog_q_v256_imm113(
1029; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 113)
1030; CHECK-NEXT:    ret <4 x i64> [[R]]
1031;
1032  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 113)
1033  ret <4 x i64> %r
1034}
1035
1036define <16 x i32> @vpternlog_d_v512_imm114(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1037; CHECK-LABEL: @vpternlog_d_v512_imm114(
1038; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 114)
1039; CHECK-NEXT:    ret <16 x i32> [[R]]
1040;
1041  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 114)
1042  ret <16 x i32> %r
1043}
1044
1045define <2 x i64> @vpternlog_q_v128_imm115(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1046; CHECK-LABEL: @vpternlog_q_v128_imm115(
1047; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 115)
1048; CHECK-NEXT:    ret <2 x i64> [[R]]
1049;
1050  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 115)
1051  ret <2 x i64> %r
1052}
1053
1054define <8 x i32> @vpternlog_d_v256_imm116(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1055; CHECK-LABEL: @vpternlog_d_v256_imm116(
1056; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 116)
1057; CHECK-NEXT:    ret <8 x i32> [[R]]
1058;
1059  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 116)
1060  ret <8 x i32> %r
1061}
1062
1063define <8 x i64> @vpternlog_q_v512_imm117(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1064; CHECK-LABEL: @vpternlog_q_v512_imm117(
1065; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 117)
1066; CHECK-NEXT:    ret <8 x i64> [[R]]
1067;
1068  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 117)
1069  ret <8 x i64> %r
1070}
1071
1072define <4 x i32> @vpternlog_d_v128_imm118(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1073; CHECK-LABEL: @vpternlog_d_v128_imm118(
1074; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 118)
1075; CHECK-NEXT:    ret <4 x i32> [[R]]
1076;
1077  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 118)
1078  ret <4 x i32> %r
1079}
1080
1081define <4 x i64> @vpternlog_q_v256_imm119(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1082; CHECK-LABEL: @vpternlog_q_v256_imm119(
1083; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 119)
1084; CHECK-NEXT:    ret <4 x i64> [[R]]
1085;
1086  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 119)
1087  ret <4 x i64> %r
1088}
1089
1090define <16 x i32> @vpternlog_d_v512_imm120(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1091; CHECK-LABEL: @vpternlog_d_v512_imm120(
1092; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 120)
1093; CHECK-NEXT:    ret <16 x i32> [[R]]
1094;
1095  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 120)
1096  ret <16 x i32> %r
1097}
1098
1099define <2 x i64> @vpternlog_q_v128_imm121(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1100; CHECK-LABEL: @vpternlog_q_v128_imm121(
1101; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 121)
1102; CHECK-NEXT:    ret <2 x i64> [[R]]
1103;
1104  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 121)
1105  ret <2 x i64> %r
1106}
1107
1108define <8 x i32> @vpternlog_d_v256_imm122(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1109; CHECK-LABEL: @vpternlog_d_v256_imm122(
1110; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 122)
1111; CHECK-NEXT:    ret <8 x i32> [[R]]
1112;
1113  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 122)
1114  ret <8 x i32> %r
1115}
1116
1117define <8 x i64> @vpternlog_q_v512_imm123(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1118; CHECK-LABEL: @vpternlog_q_v512_imm123(
1119; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 123)
1120; CHECK-NEXT:    ret <8 x i64> [[R]]
1121;
1122  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 123)
1123  ret <8 x i64> %r
1124}
1125
1126define <4 x i32> @vpternlog_d_v128_imm124(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1127; CHECK-LABEL: @vpternlog_d_v128_imm124(
1128; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 124)
1129; CHECK-NEXT:    ret <4 x i32> [[R]]
1130;
1131  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 124)
1132  ret <4 x i32> %r
1133}
1134
1135define <4 x i64> @vpternlog_q_v256_imm125(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1136; CHECK-LABEL: @vpternlog_q_v256_imm125(
1137; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 125)
1138; CHECK-NEXT:    ret <4 x i64> [[R]]
1139;
1140  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 125)
1141  ret <4 x i64> %r
1142}
1143
1144define <16 x i32> @vpternlog_d_v512_imm126(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1145; CHECK-LABEL: @vpternlog_d_v512_imm126(
1146; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 126)
1147; CHECK-NEXT:    ret <16 x i32> [[R]]
1148;
1149  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 126)
1150  ret <16 x i32> %r
1151}
1152
1153define <2 x i64> @vpternlog_q_v128_imm127(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1154; CHECK-LABEL: @vpternlog_q_v128_imm127(
1155; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 127)
1156; CHECK-NEXT:    ret <2 x i64> [[R]]
1157;
1158  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 127)
1159  ret <2 x i64> %r
1160}
1161
1162define <8 x i32> @vpternlog_d_v256_imm128(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1163; CHECK-LABEL: @vpternlog_d_v256_imm128(
1164; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 128)
1165; CHECK-NEXT:    ret <8 x i32> [[R]]
1166;
1167  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 128)
1168  ret <8 x i32> %r
1169}
1170
1171define <8 x i64> @vpternlog_q_v512_imm129(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1172; CHECK-LABEL: @vpternlog_q_v512_imm129(
1173; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 129)
1174; CHECK-NEXT:    ret <8 x i64> [[R]]
1175;
1176  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 129)
1177  ret <8 x i64> %r
1178}
1179
1180define <4 x i32> @vpternlog_d_v128_imm130(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1181; CHECK-LABEL: @vpternlog_d_v128_imm130(
1182; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 130)
1183; CHECK-NEXT:    ret <4 x i32> [[R]]
1184;
1185  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 130)
1186  ret <4 x i32> %r
1187}
1188
1189define <4 x i64> @vpternlog_q_v256_imm131(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1190; CHECK-LABEL: @vpternlog_q_v256_imm131(
1191; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 131)
1192; CHECK-NEXT:    ret <4 x i64> [[R]]
1193;
1194  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 131)
1195  ret <4 x i64> %r
1196}
1197
1198define <16 x i32> @vpternlog_d_v512_imm132(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1199; CHECK-LABEL: @vpternlog_d_v512_imm132(
1200; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 132)
1201; CHECK-NEXT:    ret <16 x i32> [[R]]
1202;
1203  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 132)
1204  ret <16 x i32> %r
1205}
1206
1207define <2 x i64> @vpternlog_q_v128_imm133(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1208; CHECK-LABEL: @vpternlog_q_v128_imm133(
1209; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 133)
1210; CHECK-NEXT:    ret <2 x i64> [[R]]
1211;
1212  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 133)
1213  ret <2 x i64> %r
1214}
1215
1216define <8 x i32> @vpternlog_d_v256_imm134(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1217; CHECK-LABEL: @vpternlog_d_v256_imm134(
1218; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 134)
1219; CHECK-NEXT:    ret <8 x i32> [[R]]
1220;
1221  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 134)
1222  ret <8 x i32> %r
1223}
1224
1225define <8 x i64> @vpternlog_q_v512_imm135(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1226; CHECK-LABEL: @vpternlog_q_v512_imm135(
1227; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 135)
1228; CHECK-NEXT:    ret <8 x i64> [[R]]
1229;
1230  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 135)
1231  ret <8 x i64> %r
1232}
1233
1234define <4 x i32> @vpternlog_d_v128_imm136(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1235; CHECK-LABEL: @vpternlog_d_v128_imm136(
1236; CHECK-NEXT:    [[R:%.*]] = and <4 x i32> [[V1:%.*]], [[V2:%.*]]
1237; CHECK-NEXT:    ret <4 x i32> [[R]]
1238;
1239  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 136)
1240  ret <4 x i32> %r
1241}
1242
1243define <4 x i64> @vpternlog_q_v256_imm137(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1244; CHECK-LABEL: @vpternlog_q_v256_imm137(
1245; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 137)
1246; CHECK-NEXT:    ret <4 x i64> [[R]]
1247;
1248  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 137)
1249  ret <4 x i64> %r
1250}
1251
1252define <16 x i32> @vpternlog_d_v512_imm138(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1253; CHECK-LABEL: @vpternlog_d_v512_imm138(
1254; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 138)
1255; CHECK-NEXT:    ret <16 x i32> [[R]]
1256;
1257  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 138)
1258  ret <16 x i32> %r
1259}
1260
1261define <2 x i64> @vpternlog_q_v128_imm139(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1262; CHECK-LABEL: @vpternlog_q_v128_imm139(
1263; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 139)
1264; CHECK-NEXT:    ret <2 x i64> [[R]]
1265;
1266  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 139)
1267  ret <2 x i64> %r
1268}
1269
1270define <8 x i32> @vpternlog_d_v256_imm140(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1271; CHECK-LABEL: @vpternlog_d_v256_imm140(
1272; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 140)
1273; CHECK-NEXT:    ret <8 x i32> [[R]]
1274;
1275  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 140)
1276  ret <8 x i32> %r
1277}
1278
1279define <8 x i64> @vpternlog_q_v512_imm141(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1280; CHECK-LABEL: @vpternlog_q_v512_imm141(
1281; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 141)
1282; CHECK-NEXT:    ret <8 x i64> [[R]]
1283;
1284  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 141)
1285  ret <8 x i64> %r
1286}
1287
1288define <4 x i32> @vpternlog_d_v128_imm142(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1289; CHECK-LABEL: @vpternlog_d_v128_imm142(
1290; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 142)
1291; CHECK-NEXT:    ret <4 x i32> [[R]]
1292;
1293  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 142)
1294  ret <4 x i32> %r
1295}
1296
1297define <4 x i64> @vpternlog_q_v256_imm143(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1298; CHECK-LABEL: @vpternlog_q_v256_imm143(
1299; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 143)
1300; CHECK-NEXT:    ret <4 x i64> [[R]]
1301;
1302  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 143)
1303  ret <4 x i64> %r
1304}
1305
1306define <16 x i32> @vpternlog_d_v512_imm144(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1307; CHECK-LABEL: @vpternlog_d_v512_imm144(
1308; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 144)
1309; CHECK-NEXT:    ret <16 x i32> [[R]]
1310;
1311  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 144)
1312  ret <16 x i32> %r
1313}
1314
1315define <2 x i64> @vpternlog_q_v128_imm145(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1316; CHECK-LABEL: @vpternlog_q_v128_imm145(
1317; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 145)
1318; CHECK-NEXT:    ret <2 x i64> [[R]]
1319;
1320  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 145)
1321  ret <2 x i64> %r
1322}
1323
1324define <8 x i32> @vpternlog_d_v256_imm146(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1325; CHECK-LABEL: @vpternlog_d_v256_imm146(
1326; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 146)
1327; CHECK-NEXT:    ret <8 x i32> [[R]]
1328;
1329  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 146)
1330  ret <8 x i32> %r
1331}
1332
1333define <8 x i64> @vpternlog_q_v512_imm147(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1334; CHECK-LABEL: @vpternlog_q_v512_imm147(
1335; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 147)
1336; CHECK-NEXT:    ret <8 x i64> [[R]]
1337;
1338  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 147)
1339  ret <8 x i64> %r
1340}
1341
1342define <4 x i32> @vpternlog_d_v128_imm148(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1343; CHECK-LABEL: @vpternlog_d_v128_imm148(
1344; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 148)
1345; CHECK-NEXT:    ret <4 x i32> [[R]]
1346;
1347  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 148)
1348  ret <4 x i32> %r
1349}
1350
1351define <4 x i64> @vpternlog_q_v256_imm149(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1352; CHECK-LABEL: @vpternlog_q_v256_imm149(
1353; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 149)
1354; CHECK-NEXT:    ret <4 x i64> [[R]]
1355;
1356  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 149)
1357  ret <4 x i64> %r
1358}
1359
1360define <16 x i32> @vpternlog_d_v512_imm150(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1361; CHECK-LABEL: @vpternlog_d_v512_imm150(
1362; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 150)
1363; CHECK-NEXT:    ret <16 x i32> [[R]]
1364;
1365  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 150)
1366  ret <16 x i32> %r
1367}
1368
1369define <2 x i64> @vpternlog_q_v128_imm151(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1370; CHECK-LABEL: @vpternlog_q_v128_imm151(
1371; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 151)
1372; CHECK-NEXT:    ret <2 x i64> [[R]]
1373;
1374  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 151)
1375  ret <2 x i64> %r
1376}
1377
1378define <8 x i32> @vpternlog_d_v256_imm152(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1379; CHECK-LABEL: @vpternlog_d_v256_imm152(
1380; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 152)
1381; CHECK-NEXT:    ret <8 x i32> [[R]]
1382;
1383  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 152)
1384  ret <8 x i32> %r
1385}
1386
1387define <8 x i64> @vpternlog_q_v512_imm153(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1388; CHECK-LABEL: @vpternlog_q_v512_imm153(
1389; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 153)
1390; CHECK-NEXT:    ret <8 x i64> [[R]]
1391;
1392  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 153)
1393  ret <8 x i64> %r
1394}
1395
1396define <4 x i32> @vpternlog_d_v128_imm154(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1397; CHECK-LABEL: @vpternlog_d_v128_imm154(
1398; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 154)
1399; CHECK-NEXT:    ret <4 x i32> [[R]]
1400;
1401  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 154)
1402  ret <4 x i32> %r
1403}
1404
1405define <4 x i64> @vpternlog_q_v256_imm155(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1406; CHECK-LABEL: @vpternlog_q_v256_imm155(
1407; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 155)
1408; CHECK-NEXT:    ret <4 x i64> [[R]]
1409;
1410  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 155)
1411  ret <4 x i64> %r
1412}
1413
1414define <16 x i32> @vpternlog_d_v512_imm156(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1415; CHECK-LABEL: @vpternlog_d_v512_imm156(
1416; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 156)
1417; CHECK-NEXT:    ret <16 x i32> [[R]]
1418;
1419  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 156)
1420  ret <16 x i32> %r
1421}
1422
1423define <2 x i64> @vpternlog_q_v128_imm157(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1424; CHECK-LABEL: @vpternlog_q_v128_imm157(
1425; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 157)
1426; CHECK-NEXT:    ret <2 x i64> [[R]]
1427;
1428  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 157)
1429  ret <2 x i64> %r
1430}
1431
1432define <8 x i32> @vpternlog_d_v256_imm158(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1433; CHECK-LABEL: @vpternlog_d_v256_imm158(
1434; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 158)
1435; CHECK-NEXT:    ret <8 x i32> [[R]]
1436;
1437  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 158)
1438  ret <8 x i32> %r
1439}
1440
1441define <8 x i64> @vpternlog_q_v512_imm159(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1442; CHECK-LABEL: @vpternlog_q_v512_imm159(
1443; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 159)
1444; CHECK-NEXT:    ret <8 x i64> [[R]]
1445;
1446  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 159)
1447  ret <8 x i64> %r
1448}
1449
1450define <4 x i32> @vpternlog_d_v128_imm160(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1451; CHECK-LABEL: @vpternlog_d_v128_imm160(
1452; CHECK-NEXT:    [[R:%.*]] = and <4 x i32> [[V0:%.*]], [[V2:%.*]]
1453; CHECK-NEXT:    ret <4 x i32> [[R]]
1454;
1455  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 160)
1456  ret <4 x i32> %r
1457}
1458
1459define <4 x i64> @vpternlog_q_v256_imm161(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1460; CHECK-LABEL: @vpternlog_q_v256_imm161(
1461; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 161)
1462; CHECK-NEXT:    ret <4 x i64> [[R]]
1463;
1464  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 161)
1465  ret <4 x i64> %r
1466}
1467
1468define <16 x i32> @vpternlog_d_v512_imm162(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1469; CHECK-LABEL: @vpternlog_d_v512_imm162(
1470; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 162)
1471; CHECK-NEXT:    ret <16 x i32> [[R]]
1472;
1473  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 162)
1474  ret <16 x i32> %r
1475}
1476
1477define <2 x i64> @vpternlog_q_v128_imm163(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1478; CHECK-LABEL: @vpternlog_q_v128_imm163(
1479; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 163)
1480; CHECK-NEXT:    ret <2 x i64> [[R]]
1481;
1482  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 163)
1483  ret <2 x i64> %r
1484}
1485
1486define <8 x i32> @vpternlog_d_v256_imm164(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1487; CHECK-LABEL: @vpternlog_d_v256_imm164(
1488; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 164)
1489; CHECK-NEXT:    ret <8 x i32> [[R]]
1490;
1491  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 164)
1492  ret <8 x i32> %r
1493}
1494
1495define <8 x i64> @vpternlog_q_v512_imm165(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1496; CHECK-LABEL: @vpternlog_q_v512_imm165(
1497; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 165)
1498; CHECK-NEXT:    ret <8 x i64> [[R]]
1499;
1500  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 165)
1501  ret <8 x i64> %r
1502}
1503
1504define <4 x i32> @vpternlog_d_v128_imm166(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1505; CHECK-LABEL: @vpternlog_d_v128_imm166(
1506; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 166)
1507; CHECK-NEXT:    ret <4 x i32> [[R]]
1508;
1509  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 166)
1510  ret <4 x i32> %r
1511}
1512
1513define <4 x i64> @vpternlog_q_v256_imm167(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1514; CHECK-LABEL: @vpternlog_q_v256_imm167(
1515; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 167)
1516; CHECK-NEXT:    ret <4 x i64> [[R]]
1517;
1518  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 167)
1519  ret <4 x i64> %r
1520}
1521
1522define <16 x i32> @vpternlog_d_v512_imm168(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1523; CHECK-LABEL: @vpternlog_d_v512_imm168(
1524; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 168)
1525; CHECK-NEXT:    ret <16 x i32> [[R]]
1526;
1527  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 168)
1528  ret <16 x i32> %r
1529}
1530
1531define <2 x i64> @vpternlog_q_v128_imm169(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1532; CHECK-LABEL: @vpternlog_q_v128_imm169(
1533; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 169)
1534; CHECK-NEXT:    ret <2 x i64> [[R]]
1535;
1536  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 169)
1537  ret <2 x i64> %r
1538}
1539
1540define <8 x i32> @vpternlog_d_v256_imm170(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1541; CHECK-LABEL: @vpternlog_d_v256_imm170(
1542; CHECK-NEXT:    ret <8 x i32> [[V2:%.*]]
1543;
1544  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 170)
1545  ret <8 x i32> %r
1546}
1547
1548define <8 x i64> @vpternlog_q_v512_imm171(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1549; CHECK-LABEL: @vpternlog_q_v512_imm171(
1550; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 171)
1551; CHECK-NEXT:    ret <8 x i64> [[R]]
1552;
1553  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 171)
1554  ret <8 x i64> %r
1555}
1556
1557define <4 x i32> @vpternlog_d_v128_imm172(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1558; CHECK-LABEL: @vpternlog_d_v128_imm172(
1559; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 172)
1560; CHECK-NEXT:    ret <4 x i32> [[R]]
1561;
1562  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 172)
1563  ret <4 x i32> %r
1564}
1565
1566define <4 x i64> @vpternlog_q_v256_imm173(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1567; CHECK-LABEL: @vpternlog_q_v256_imm173(
1568; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 173)
1569; CHECK-NEXT:    ret <4 x i64> [[R]]
1570;
1571  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 173)
1572  ret <4 x i64> %r
1573}
1574
1575define <16 x i32> @vpternlog_d_v512_imm174(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1576; CHECK-LABEL: @vpternlog_d_v512_imm174(
1577; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 174)
1578; CHECK-NEXT:    ret <16 x i32> [[R]]
1579;
1580  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 174)
1581  ret <16 x i32> %r
1582}
1583
1584define <2 x i64> @vpternlog_q_v128_imm175(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1585; CHECK-LABEL: @vpternlog_q_v128_imm175(
1586; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 175)
1587; CHECK-NEXT:    ret <2 x i64> [[R]]
1588;
1589  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 175)
1590  ret <2 x i64> %r
1591}
1592
1593define <8 x i32> @vpternlog_d_v256_imm176(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1594; CHECK-LABEL: @vpternlog_d_v256_imm176(
1595; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 176)
1596; CHECK-NEXT:    ret <8 x i32> [[R]]
1597;
1598  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 176)
1599  ret <8 x i32> %r
1600}
1601
1602define <8 x i64> @vpternlog_q_v512_imm177(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1603; CHECK-LABEL: @vpternlog_q_v512_imm177(
1604; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 177)
1605; CHECK-NEXT:    ret <8 x i64> [[R]]
1606;
1607  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 177)
1608  ret <8 x i64> %r
1609}
1610
1611define <4 x i32> @vpternlog_d_v128_imm178(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1612; CHECK-LABEL: @vpternlog_d_v128_imm178(
1613; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 178)
1614; CHECK-NEXT:    ret <4 x i32> [[R]]
1615;
1616  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 178)
1617  ret <4 x i32> %r
1618}
1619
1620define <4 x i64> @vpternlog_q_v256_imm179(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1621; CHECK-LABEL: @vpternlog_q_v256_imm179(
1622; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 179)
1623; CHECK-NEXT:    ret <4 x i64> [[R]]
1624;
1625  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 179)
1626  ret <4 x i64> %r
1627}
1628
1629define <16 x i32> @vpternlog_d_v512_imm180(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1630; CHECK-LABEL: @vpternlog_d_v512_imm180(
1631; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 180)
1632; CHECK-NEXT:    ret <16 x i32> [[R]]
1633;
1634  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 180)
1635  ret <16 x i32> %r
1636}
1637
1638define <2 x i64> @vpternlog_q_v128_imm181(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1639; CHECK-LABEL: @vpternlog_q_v128_imm181(
1640; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 181)
1641; CHECK-NEXT:    ret <2 x i64> [[R]]
1642;
1643  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 181)
1644  ret <2 x i64> %r
1645}
1646
1647define <8 x i32> @vpternlog_d_v256_imm182(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1648; CHECK-LABEL: @vpternlog_d_v256_imm182(
1649; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 182)
1650; CHECK-NEXT:    ret <8 x i32> [[R]]
1651;
1652  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 182)
1653  ret <8 x i32> %r
1654}
1655
1656define <8 x i64> @vpternlog_q_v512_imm183(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1657; CHECK-LABEL: @vpternlog_q_v512_imm183(
1658; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 183)
1659; CHECK-NEXT:    ret <8 x i64> [[R]]
1660;
1661  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 183)
1662  ret <8 x i64> %r
1663}
1664
1665define <4 x i32> @vpternlog_d_v128_imm184(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1666; CHECK-LABEL: @vpternlog_d_v128_imm184(
1667; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 184)
1668; CHECK-NEXT:    ret <4 x i32> [[R]]
1669;
1670  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 184)
1671  ret <4 x i32> %r
1672}
1673
1674define <4 x i64> @vpternlog_q_v256_imm185(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1675; CHECK-LABEL: @vpternlog_q_v256_imm185(
1676; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 185)
1677; CHECK-NEXT:    ret <4 x i64> [[R]]
1678;
1679  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 185)
1680  ret <4 x i64> %r
1681}
1682
1683define <16 x i32> @vpternlog_d_v512_imm186(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1684; CHECK-LABEL: @vpternlog_d_v512_imm186(
1685; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 186)
1686; CHECK-NEXT:    ret <16 x i32> [[R]]
1687;
1688  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 186)
1689  ret <16 x i32> %r
1690}
1691
1692define <2 x i64> @vpternlog_q_v128_imm187(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1693; CHECK-LABEL: @vpternlog_q_v128_imm187(
1694; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 187)
1695; CHECK-NEXT:    ret <2 x i64> [[R]]
1696;
1697  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 187)
1698  ret <2 x i64> %r
1699}
1700
1701define <8 x i32> @vpternlog_d_v256_imm188(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1702; CHECK-LABEL: @vpternlog_d_v256_imm188(
1703; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 188)
1704; CHECK-NEXT:    ret <8 x i32> [[R]]
1705;
1706  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 188)
1707  ret <8 x i32> %r
1708}
1709
1710define <8 x i64> @vpternlog_q_v512_imm189(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1711; CHECK-LABEL: @vpternlog_q_v512_imm189(
1712; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 189)
1713; CHECK-NEXT:    ret <8 x i64> [[R]]
1714;
1715  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 189)
1716  ret <8 x i64> %r
1717}
1718
1719define <4 x i32> @vpternlog_d_v128_imm190(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1720; CHECK-LABEL: @vpternlog_d_v128_imm190(
1721; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 190)
1722; CHECK-NEXT:    ret <4 x i32> [[R]]
1723;
1724  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 190)
1725  ret <4 x i32> %r
1726}
1727
1728define <4 x i64> @vpternlog_q_v256_imm191(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1729; CHECK-LABEL: @vpternlog_q_v256_imm191(
1730; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 191)
1731; CHECK-NEXT:    ret <4 x i64> [[R]]
1732;
1733  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 191)
1734  ret <4 x i64> %r
1735}
1736
1737define <16 x i32> @vpternlog_d_v512_imm192(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1738; CHECK-LABEL: @vpternlog_d_v512_imm192(
1739; CHECK-NEXT:    [[R:%.*]] = and <16 x i32> [[V0:%.*]], [[V1:%.*]]
1740; CHECK-NEXT:    ret <16 x i32> [[R]]
1741;
1742  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 192)
1743  ret <16 x i32> %r
1744}
1745
1746define <2 x i64> @vpternlog_q_v128_imm193(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1747; CHECK-LABEL: @vpternlog_q_v128_imm193(
1748; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 193)
1749; CHECK-NEXT:    ret <2 x i64> [[R]]
1750;
1751  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 193)
1752  ret <2 x i64> %r
1753}
1754
1755define <8 x i32> @vpternlog_d_v256_imm194(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1756; CHECK-LABEL: @vpternlog_d_v256_imm194(
1757; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 194)
1758; CHECK-NEXT:    ret <8 x i32> [[R]]
1759;
1760  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 194)
1761  ret <8 x i32> %r
1762}
1763
1764define <8 x i64> @vpternlog_q_v512_imm195(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1765; CHECK-LABEL: @vpternlog_q_v512_imm195(
1766; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 195)
1767; CHECK-NEXT:    ret <8 x i64> [[R]]
1768;
1769  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 195)
1770  ret <8 x i64> %r
1771}
1772
1773define <4 x i32> @vpternlog_d_v128_imm196(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1774; CHECK-LABEL: @vpternlog_d_v128_imm196(
1775; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 196)
1776; CHECK-NEXT:    ret <4 x i32> [[R]]
1777;
1778  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 196)
1779  ret <4 x i32> %r
1780}
1781
1782define <4 x i64> @vpternlog_q_v256_imm197(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1783; CHECK-LABEL: @vpternlog_q_v256_imm197(
1784; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 197)
1785; CHECK-NEXT:    ret <4 x i64> [[R]]
1786;
1787  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 197)
1788  ret <4 x i64> %r
1789}
1790
1791define <16 x i32> @vpternlog_d_v512_imm198(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1792; CHECK-LABEL: @vpternlog_d_v512_imm198(
1793; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 198)
1794; CHECK-NEXT:    ret <16 x i32> [[R]]
1795;
1796  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 198)
1797  ret <16 x i32> %r
1798}
1799
1800define <2 x i64> @vpternlog_q_v128_imm199(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1801; CHECK-LABEL: @vpternlog_q_v128_imm199(
1802; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 199)
1803; CHECK-NEXT:    ret <2 x i64> [[R]]
1804;
1805  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 199)
1806  ret <2 x i64> %r
1807}
1808
1809define <8 x i32> @vpternlog_d_v256_imm200(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1810; CHECK-LABEL: @vpternlog_d_v256_imm200(
1811; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 200)
1812; CHECK-NEXT:    ret <8 x i32> [[R]]
1813;
1814  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 200)
1815  ret <8 x i32> %r
1816}
1817
1818define <8 x i64> @vpternlog_q_v512_imm201(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1819; CHECK-LABEL: @vpternlog_q_v512_imm201(
1820; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 201)
1821; CHECK-NEXT:    ret <8 x i64> [[R]]
1822;
1823  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 201)
1824  ret <8 x i64> %r
1825}
1826
1827define <4 x i32> @vpternlog_d_v128_imm202(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1828; CHECK-LABEL: @vpternlog_d_v128_imm202(
1829; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 202)
1830; CHECK-NEXT:    ret <4 x i32> [[R]]
1831;
1832  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 202)
1833  ret <4 x i32> %r
1834}
1835
1836define <4 x i64> @vpternlog_q_v256_imm203(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1837; CHECK-LABEL: @vpternlog_q_v256_imm203(
1838; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 203)
1839; CHECK-NEXT:    ret <4 x i64> [[R]]
1840;
1841  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 203)
1842  ret <4 x i64> %r
1843}
1844
1845define <16 x i32> @vpternlog_d_v512_imm204(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1846; CHECK-LABEL: @vpternlog_d_v512_imm204(
1847; CHECK-NEXT:    ret <16 x i32> [[V1:%.*]]
1848;
1849  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 204)
1850  ret <16 x i32> %r
1851}
1852
1853define <2 x i64> @vpternlog_q_v128_imm205(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1854; CHECK-LABEL: @vpternlog_q_v128_imm205(
1855; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 205)
1856; CHECK-NEXT:    ret <2 x i64> [[R]]
1857;
1858  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 205)
1859  ret <2 x i64> %r
1860}
1861
1862define <8 x i32> @vpternlog_d_v256_imm206(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1863; CHECK-LABEL: @vpternlog_d_v256_imm206(
1864; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 206)
1865; CHECK-NEXT:    ret <8 x i32> [[R]]
1866;
1867  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 206)
1868  ret <8 x i32> %r
1869}
1870
1871define <8 x i64> @vpternlog_q_v512_imm207(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1872; CHECK-LABEL: @vpternlog_q_v512_imm207(
1873; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 207)
1874; CHECK-NEXT:    ret <8 x i64> [[R]]
1875;
1876  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 207)
1877  ret <8 x i64> %r
1878}
1879
1880define <4 x i32> @vpternlog_d_v128_imm208(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1881; CHECK-LABEL: @vpternlog_d_v128_imm208(
1882; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 208)
1883; CHECK-NEXT:    ret <4 x i32> [[R]]
1884;
1885  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 208)
1886  ret <4 x i32> %r
1887}
1888
1889define <4 x i64> @vpternlog_q_v256_imm209(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1890; CHECK-LABEL: @vpternlog_q_v256_imm209(
1891; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 209)
1892; CHECK-NEXT:    ret <4 x i64> [[R]]
1893;
1894  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 209)
1895  ret <4 x i64> %r
1896}
1897
1898define <16 x i32> @vpternlog_d_v512_imm210(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1899; CHECK-LABEL: @vpternlog_d_v512_imm210(
1900; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 210)
1901; CHECK-NEXT:    ret <16 x i32> [[R]]
1902;
1903  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 210)
1904  ret <16 x i32> %r
1905}
1906
1907define <2 x i64> @vpternlog_q_v128_imm211(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1908; CHECK-LABEL: @vpternlog_q_v128_imm211(
1909; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 211)
1910; CHECK-NEXT:    ret <2 x i64> [[R]]
1911;
1912  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 211)
1913  ret <2 x i64> %r
1914}
1915
1916define <8 x i32> @vpternlog_d_v256_imm212(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1917; CHECK-LABEL: @vpternlog_d_v256_imm212(
1918; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 212)
1919; CHECK-NEXT:    ret <8 x i32> [[R]]
1920;
1921  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 212)
1922  ret <8 x i32> %r
1923}
1924
1925define <8 x i64> @vpternlog_q_v512_imm213(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1926; CHECK-LABEL: @vpternlog_q_v512_imm213(
1927; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 213)
1928; CHECK-NEXT:    ret <8 x i64> [[R]]
1929;
1930  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 213)
1931  ret <8 x i64> %r
1932}
1933
1934define <4 x i32> @vpternlog_d_v128_imm214(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1935; CHECK-LABEL: @vpternlog_d_v128_imm214(
1936; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 214)
1937; CHECK-NEXT:    ret <4 x i32> [[R]]
1938;
1939  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 214)
1940  ret <4 x i32> %r
1941}
1942
1943define <4 x i64> @vpternlog_q_v256_imm215(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1944; CHECK-LABEL: @vpternlog_q_v256_imm215(
1945; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 215)
1946; CHECK-NEXT:    ret <4 x i64> [[R]]
1947;
1948  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 215)
1949  ret <4 x i64> %r
1950}
1951
1952define <16 x i32> @vpternlog_d_v512_imm216(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
1953; CHECK-LABEL: @vpternlog_d_v512_imm216(
1954; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 216)
1955; CHECK-NEXT:    ret <16 x i32> [[R]]
1956;
1957  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 216)
1958  ret <16 x i32> %r
1959}
1960
1961define <2 x i64> @vpternlog_q_v128_imm217(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
1962; CHECK-LABEL: @vpternlog_q_v128_imm217(
1963; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 217)
1964; CHECK-NEXT:    ret <2 x i64> [[R]]
1965;
1966  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 217)
1967  ret <2 x i64> %r
1968}
1969
1970define <8 x i32> @vpternlog_d_v256_imm218(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
1971; CHECK-LABEL: @vpternlog_d_v256_imm218(
1972; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 218)
1973; CHECK-NEXT:    ret <8 x i32> [[R]]
1974;
1975  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 218)
1976  ret <8 x i32> %r
1977}
1978
1979define <8 x i64> @vpternlog_q_v512_imm219(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
1980; CHECK-LABEL: @vpternlog_q_v512_imm219(
1981; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 219)
1982; CHECK-NEXT:    ret <8 x i64> [[R]]
1983;
1984  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 219)
1985  ret <8 x i64> %r
1986}
1987
1988define <4 x i32> @vpternlog_d_v128_imm220(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
1989; CHECK-LABEL: @vpternlog_d_v128_imm220(
1990; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 220)
1991; CHECK-NEXT:    ret <4 x i32> [[R]]
1992;
1993  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 220)
1994  ret <4 x i32> %r
1995}
1996
1997define <4 x i64> @vpternlog_q_v256_imm221(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
1998; CHECK-LABEL: @vpternlog_q_v256_imm221(
1999; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 221)
2000; CHECK-NEXT:    ret <4 x i64> [[R]]
2001;
2002  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 221)
2003  ret <4 x i64> %r
2004}
2005
2006define <16 x i32> @vpternlog_d_v512_imm222(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
2007; CHECK-LABEL: @vpternlog_d_v512_imm222(
2008; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 222)
2009; CHECK-NEXT:    ret <16 x i32> [[R]]
2010;
2011  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 222)
2012  ret <16 x i32> %r
2013}
2014
2015define <2 x i64> @vpternlog_q_v128_imm223(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
2016; CHECK-LABEL: @vpternlog_q_v128_imm223(
2017; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 223)
2018; CHECK-NEXT:    ret <2 x i64> [[R]]
2019;
2020  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 223)
2021  ret <2 x i64> %r
2022}
2023
2024define <8 x i32> @vpternlog_d_v256_imm224(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
2025; CHECK-LABEL: @vpternlog_d_v256_imm224(
2026; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 224)
2027; CHECK-NEXT:    ret <8 x i32> [[R]]
2028;
2029  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 224)
2030  ret <8 x i32> %r
2031}
2032
2033define <8 x i64> @vpternlog_q_v512_imm225(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
2034; CHECK-LABEL: @vpternlog_q_v512_imm225(
2035; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 225)
2036; CHECK-NEXT:    ret <8 x i64> [[R]]
2037;
2038  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 225)
2039  ret <8 x i64> %r
2040}
2041
2042define <4 x i32> @vpternlog_d_v128_imm226(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
2043; CHECK-LABEL: @vpternlog_d_v128_imm226(
2044; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 226)
2045; CHECK-NEXT:    ret <4 x i32> [[R]]
2046;
2047  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 226)
2048  ret <4 x i32> %r
2049}
2050
2051define <4 x i64> @vpternlog_q_v256_imm227(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
2052; CHECK-LABEL: @vpternlog_q_v256_imm227(
2053; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 227)
2054; CHECK-NEXT:    ret <4 x i64> [[R]]
2055;
2056  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 227)
2057  ret <4 x i64> %r
2058}
2059
2060define <16 x i32> @vpternlog_d_v512_imm228(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
2061; CHECK-LABEL: @vpternlog_d_v512_imm228(
2062; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 228)
2063; CHECK-NEXT:    ret <16 x i32> [[R]]
2064;
2065  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 228)
2066  ret <16 x i32> %r
2067}
2068
2069define <2 x i64> @vpternlog_q_v128_imm229(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
2070; CHECK-LABEL: @vpternlog_q_v128_imm229(
2071; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 229)
2072; CHECK-NEXT:    ret <2 x i64> [[R]]
2073;
2074  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 229)
2075  ret <2 x i64> %r
2076}
2077
2078define <8 x i32> @vpternlog_d_v256_imm230(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
2079; CHECK-LABEL: @vpternlog_d_v256_imm230(
2080; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 230)
2081; CHECK-NEXT:    ret <8 x i32> [[R]]
2082;
2083  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 230)
2084  ret <8 x i32> %r
2085}
2086
2087define <8 x i64> @vpternlog_q_v512_imm231(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
2088; CHECK-LABEL: @vpternlog_q_v512_imm231(
2089; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 231)
2090; CHECK-NEXT:    ret <8 x i64> [[R]]
2091;
2092  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 231)
2093  ret <8 x i64> %r
2094}
2095
2096define <4 x i32> @vpternlog_d_v128_imm232(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
2097; CHECK-LABEL: @vpternlog_d_v128_imm232(
2098; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 232)
2099; CHECK-NEXT:    ret <4 x i32> [[R]]
2100;
2101  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 232)
2102  ret <4 x i32> %r
2103}
2104
2105define <4 x i64> @vpternlog_q_v256_imm233(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
2106; CHECK-LABEL: @vpternlog_q_v256_imm233(
2107; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 233)
2108; CHECK-NEXT:    ret <4 x i64> [[R]]
2109;
2110  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 233)
2111  ret <4 x i64> %r
2112}
2113
2114define <16 x i32> @vpternlog_d_v512_imm234(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
2115; CHECK-LABEL: @vpternlog_d_v512_imm234(
2116; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 234)
2117; CHECK-NEXT:    ret <16 x i32> [[R]]
2118;
2119  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 234)
2120  ret <16 x i32> %r
2121}
2122
2123define <2 x i64> @vpternlog_q_v128_imm235(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
2124; CHECK-LABEL: @vpternlog_q_v128_imm235(
2125; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 235)
2126; CHECK-NEXT:    ret <2 x i64> [[R]]
2127;
2128  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 235)
2129  ret <2 x i64> %r
2130}
2131
2132define <8 x i32> @vpternlog_d_v256_imm236(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
2133; CHECK-LABEL: @vpternlog_d_v256_imm236(
2134; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 236)
2135; CHECK-NEXT:    ret <8 x i32> [[R]]
2136;
2137  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 236)
2138  ret <8 x i32> %r
2139}
2140
2141define <8 x i64> @vpternlog_q_v512_imm237(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
2142; CHECK-LABEL: @vpternlog_q_v512_imm237(
2143; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 237)
2144; CHECK-NEXT:    ret <8 x i64> [[R]]
2145;
2146  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 237)
2147  ret <8 x i64> %r
2148}
2149
2150define <4 x i32> @vpternlog_d_v128_imm238(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
2151; CHECK-LABEL: @vpternlog_d_v128_imm238(
2152; CHECK-NEXT:    [[R:%.*]] = or <4 x i32> [[V1:%.*]], [[V2:%.*]]
2153; CHECK-NEXT:    ret <4 x i32> [[R]]
2154;
2155  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 238)
2156  ret <4 x i32> %r
2157}
2158
2159define <4 x i64> @vpternlog_q_v256_imm239(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
2160; CHECK-LABEL: @vpternlog_q_v256_imm239(
2161; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 239)
2162; CHECK-NEXT:    ret <4 x i64> [[R]]
2163;
2164  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 239)
2165  ret <4 x i64> %r
2166}
2167
2168define <16 x i32> @vpternlog_d_v512_imm240(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
2169; CHECK-LABEL: @vpternlog_d_v512_imm240(
2170; CHECK-NEXT:    ret <16 x i32> [[V0:%.*]]
2171;
2172  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 240)
2173  ret <16 x i32> %r
2174}
2175
2176define <2 x i64> @vpternlog_q_v128_imm241(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
2177; CHECK-LABEL: @vpternlog_q_v128_imm241(
2178; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 241)
2179; CHECK-NEXT:    ret <2 x i64> [[R]]
2180;
2181  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 241)
2182  ret <2 x i64> %r
2183}
2184
2185define <8 x i32> @vpternlog_d_v256_imm242(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
2186; CHECK-LABEL: @vpternlog_d_v256_imm242(
2187; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 242)
2188; CHECK-NEXT:    ret <8 x i32> [[R]]
2189;
2190  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 242)
2191  ret <8 x i32> %r
2192}
2193
2194define <8 x i64> @vpternlog_q_v512_imm243(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
2195; CHECK-LABEL: @vpternlog_q_v512_imm243(
2196; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 243)
2197; CHECK-NEXT:    ret <8 x i64> [[R]]
2198;
2199  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 243)
2200  ret <8 x i64> %r
2201}
2202
2203define <4 x i32> @vpternlog_d_v128_imm244(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
2204; CHECK-LABEL: @vpternlog_d_v128_imm244(
2205; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> [[V0:%.*]], <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 244)
2206; CHECK-NEXT:    ret <4 x i32> [[R]]
2207;
2208  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 244)
2209  ret <4 x i32> %r
2210}
2211
2212define <4 x i64> @vpternlog_q_v256_imm245(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
2213; CHECK-LABEL: @vpternlog_q_v256_imm245(
2214; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 245)
2215; CHECK-NEXT:    ret <4 x i64> [[R]]
2216;
2217  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 245)
2218  ret <4 x i64> %r
2219}
2220
2221define <16 x i32> @vpternlog_d_v512_imm246(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
2222; CHECK-LABEL: @vpternlog_d_v512_imm246(
2223; CHECK-NEXT:    [[R:%.*]] = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> [[V0:%.*]], <16 x i32> [[V1:%.*]], <16 x i32> [[V2:%.*]], i32 246)
2224; CHECK-NEXT:    ret <16 x i32> [[R]]
2225;
2226  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 246)
2227  ret <16 x i32> %r
2228}
2229
2230define <2 x i64> @vpternlog_q_v128_imm247(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
2231; CHECK-LABEL: @vpternlog_q_v128_imm247(
2232; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 247)
2233; CHECK-NEXT:    ret <2 x i64> [[R]]
2234;
2235  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 247)
2236  ret <2 x i64> %r
2237}
2238
2239define <8 x i32> @vpternlog_d_v256_imm248(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
2240; CHECK-LABEL: @vpternlog_d_v256_imm248(
2241; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 248)
2242; CHECK-NEXT:    ret <8 x i32> [[R]]
2243;
2244  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 248)
2245  ret <8 x i32> %r
2246}
2247
2248define <8 x i64> @vpternlog_q_v512_imm249(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
2249; CHECK-LABEL: @vpternlog_q_v512_imm249(
2250; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> [[V0:%.*]], <8 x i64> [[V1:%.*]], <8 x i64> [[V2:%.*]], i32 249)
2251; CHECK-NEXT:    ret <8 x i64> [[R]]
2252;
2253  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 249)
2254  ret <8 x i64> %r
2255}
2256
2257define <4 x i32> @vpternlog_d_v128_imm250(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
2258; CHECK-LABEL: @vpternlog_d_v128_imm250(
2259; CHECK-NEXT:    [[R:%.*]] = or <4 x i32> [[V0:%.*]], [[V2:%.*]]
2260; CHECK-NEXT:    ret <4 x i32> [[R]]
2261;
2262  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, i32 250)
2263  ret <4 x i32> %r
2264}
2265
2266define <4 x i64> @vpternlog_q_v256_imm251(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2) {
2267; CHECK-LABEL: @vpternlog_q_v256_imm251(
2268; CHECK-NEXT:    [[R:%.*]] = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> [[V0:%.*]], <4 x i64> [[V1:%.*]], <4 x i64> [[V2:%.*]], i32 251)
2269; CHECK-NEXT:    ret <4 x i64> [[R]]
2270;
2271  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> %v0, <4 x i64> %v1, <4 x i64> %v2, i32 251)
2272  ret <4 x i64> %r
2273}
2274
2275define <16 x i32> @vpternlog_d_v512_imm252(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) {
2276; CHECK-LABEL: @vpternlog_d_v512_imm252(
2277; CHECK-NEXT:    [[R:%.*]] = or <16 x i32> [[V0:%.*]], [[V1:%.*]]
2278; CHECK-NEXT:    ret <16 x i32> [[R]]
2279;
2280  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2, i32 252)
2281  ret <16 x i32> %r
2282}
2283
2284define <2 x i64> @vpternlog_q_v128_imm253(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2) {
2285; CHECK-LABEL: @vpternlog_q_v128_imm253(
2286; CHECK-NEXT:    [[R:%.*]] = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> [[V0:%.*]], <2 x i64> [[V1:%.*]], <2 x i64> [[V2:%.*]], i32 253)
2287; CHECK-NEXT:    ret <2 x i64> [[R]]
2288;
2289  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> %v0, <2 x i64> %v1, <2 x i64> %v2, i32 253)
2290  ret <2 x i64> %r
2291}
2292
2293define <8 x i32> @vpternlog_d_v256_imm254(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2) {
2294; CHECK-LABEL: @vpternlog_d_v256_imm254(
2295; CHECK-NEXT:    [[R:%.*]] = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> [[V0:%.*]], <8 x i32> [[V1:%.*]], <8 x i32> [[V2:%.*]], i32 254)
2296; CHECK-NEXT:    ret <8 x i32> [[R]]
2297;
2298  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> %v0, <8 x i32> %v1, <8 x i32> %v2, i32 254)
2299  ret <8 x i32> %r
2300}
2301
2302define <8 x i64> @vpternlog_q_v512_imm255(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2) {
2303; CHECK-LABEL: @vpternlog_q_v512_imm255(
2304; CHECK-NEXT:    ret <8 x i64> splat (i64 -1)
2305;
2306  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> %v0, <8 x i64> %v1, <8 x i64> %v2, i32 255)
2307  ret <8 x i64> %r
2308}
2309
2310define <16 x i32> @vpternlog_d_constv512_imm0() {
2311; CHECK-LABEL: @vpternlog_d_constv512_imm0(
2312; CHECK-NEXT:    ret <16 x i32> zeroinitializer
2313;
2314  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 0, i32 6, i32 1, i32 8, i32 1, i32 8, i32 7, i32 9, i32 1, i32 0, i32 8, i32 8, i32 4, i32 7, i32 0, i32 3>, <16 x i32> <i32 2, i32 7, i32 1, i32 6, i32 8, i32 5, i32 0, i32 2, i32 3, i32 5, i32 6, i32 4, i32 9, i32 4, i32 4, i32 5>, <16 x i32> <i32 2, i32 2, i32 0, i32 9, i32 3, i32 1, i32 2, i32 0, i32 8, i32 0, i32 8, i32 5, i32 5, i32 1, i32 4, i32 9>, i32 0)
2315  ret <16 x i32> %r
2316}
2317
2318define <2 x i64> @vpternlog_q_constv128_imm1() {
2319; CHECK-LABEL: @vpternlog_q_constv128_imm1(
2320; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -10>
2321;
2322  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 0>, <2 x i64> <i64 6, i64 1>, <2 x i64> <i64 1, i64 9>, i32 1)
2323  ret <2 x i64> %r
2324}
2325
2326define <8 x i32> @vpternlog_d_constv256_imm2() {
2327; CHECK-LABEL: @vpternlog_d_constv256_imm2(
2328; CHECK-NEXT:    ret <8 x i32> zeroinitializer
2329;
2330  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 3, i32 4, i32 2, i32 4, i32 7, i32 6, i32 7>, <8 x i32> <i32 9, i32 6, i32 3, i32 5, i32 3, i32 5, i32 0, i32 9>, <8 x i32> <i32 1, i32 5, i32 4, i32 2, i32 6, i32 6, i32 4, i32 9>, i32 2)
2331  ret <8 x i32> %r
2332}
2333
2334define <8 x i64> @vpternlog_q_constv512_imm3() {
2335; CHECK-LABEL: @vpternlog_q_constv512_imm3(
2336; CHECK-NEXT:    ret <8 x i64> <i64 -12, i64 -6, i64 -16, i64 -8, i64 -8, i64 -8, i64 -6, i64 -6>
2337;
2338  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 4, i64 7, i64 0, i64 6, i64 5, i64 5, i64 5>, <8 x i64> <i64 8, i64 1, i64 8, i64 7, i64 3, i64 7, i64 1, i64 0>, <8 x i64> <i64 7, i64 8, i64 8, i64 2, i64 3, i64 0, i64 7, i64 5>, i32 3)
2339  ret <8 x i64> %r
2340}
2341
2342define <4 x i32> @vpternlog_d_constv128_imm4() {
2343; CHECK-LABEL: @vpternlog_d_constv128_imm4(
2344; CHECK-NEXT:    ret <4 x i32> <i32 6, i32 0, i32 8, i32 8>
2345;
2346  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 9, i32 1, i32 7>, <4 x i32> <i32 6, i32 0, i32 9, i32 9>, <4 x i32> <i32 0, i32 8, i32 1, i32 1>, i32 4)
2347  ret <4 x i32> %r
2348}
2349
2350define <4 x i64> @vpternlog_q_constv256_imm5() {
2351; CHECK-LABEL: @vpternlog_q_constv256_imm5(
2352; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -4, i64 -8, i64 -6>
2353;
2354  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 2, i64 5, i64 5>, <4 x i64> <i64 5, i64 0, i64 6, i64 5>, <4 x i64> <i64 6, i64 3, i64 2, i64 5>, i32 5)
2355  ret <4 x i64> %r
2356}
2357
2358define <16 x i32> @vpternlog_d_constv512_imm6() {
2359; CHECK-LABEL: @vpternlog_d_constv512_imm6(
2360; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 0, i32 8, i32 2, i32 0, i32 0, i32 1, i32 0, i32 0, i32 8, i32 0, i32 4, i32 2, i32 4, i32 2, i32 11>
2361;
2362  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 2, i32 7, i32 5, i32 5, i32 5, i32 0, i32 3, i32 3, i32 2, i32 6, i32 3, i32 4, i32 3, i32 9, i32 4>, <16 x i32> <i32 9, i32 3, i32 3, i32 6, i32 7, i32 4, i32 0, i32 9, i32 4, i32 9, i32 2, i32 4, i32 7, i32 1, i32 3, i32 8>, <16 x i32> <i32 1, i32 1, i32 9, i32 0, i32 7, i32 0, i32 1, i32 8, i32 4, i32 3, i32 4, i32 2, i32 1, i32 5, i32 0, i32 7>, i32 6)
2363  ret <16 x i32> %r
2364}
2365
2366define <2 x i64> @vpternlog_q_constv128_imm7() {
2367; CHECK-LABEL: @vpternlog_q_constv128_imm7(
2368; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -7>
2369;
2370  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 2>, <2 x i64> <i64 0, i64 5>, <2 x i64> <i64 1, i64 6>, i32 7)
2371  ret <2 x i64> %r
2372}
2373
2374define <8 x i32> @vpternlog_d_constv256_imm8() {
2375; CHECK-LABEL: @vpternlog_d_constv256_imm8(
2376; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 0, i32 4, i32 1, i32 0, i32 0, i32 0>
2377;
2378  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 1, i32 7, i32 9, i32 8, i32 8, i32 9, i32 4>, <8 x i32> <i32 2, i32 9, i32 3, i32 6, i32 1, i32 9, i32 8, i32 8>, <8 x i32> <i32 1, i32 6, i32 8, i32 5, i32 1, i32 2, i32 0, i32 0>, i32 8)
2379  ret <8 x i32> %r
2380}
2381
2382define <8 x i64> @vpternlog_q_constv512_imm9() {
2383; CHECK-LABEL: @vpternlog_q_constv512_imm9(
2384; CHECK-NEXT:    ret <8 x i64> <i64 -15, i64 -8, i64 -14, i64 -8, i64 -16, i64 -6, i64 -15, i64 -8>
2385;
2386  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 8, i64 5, i64 9, i64 7, i64 3, i64 1, i64 2, i64 3>, <8 x i64> <i64 8, i64 0, i64 7, i64 5, i64 9, i64 1, i64 9, i64 7>, <8 x i64> <i64 6, i64 2, i64 2, i64 2, i64 6, i64 4, i64 7, i64 0>, i32 9)
2387  ret <8 x i64> %r
2388}
2389
2390define <4 x i32> @vpternlog_d_constv128_imm10() {
2391; CHECK-LABEL: @vpternlog_d_constv128_imm10(
2392; CHECK-NEXT:    ret <4 x i32> <i32 6, i32 2, i32 9, i32 0>
2393;
2394  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 5, i32 4, i32 4>, <4 x i32> <i32 1, i32 1, i32 2, i32 8>, <4 x i32> <i32 6, i32 2, i32 9, i32 4>, i32 10)
2395  ret <4 x i32> %r
2396}
2397
2398define <4 x i64> @vpternlog_q_constv256_imm11() {
2399; CHECK-LABEL: @vpternlog_q_constv256_imm11(
2400; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -10, i64 -2, i64 -4>
2401;
2402  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 1, i64 0, i64 2>, <4 x i64> <i64 6, i64 9, i64 1, i64 1>, <4 x i64> <i64 1, i64 2, i64 8, i64 6>, i32 11)
2403  ret <4 x i64> %r
2404}
2405
2406define <16 x i32> @vpternlog_d_constv512_imm12() {
2407; CHECK-LABEL: @vpternlog_d_constv512_imm12(
2408; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 0, i32 0, i32 8, i32 8, i32 0, i32 2, i32 0, i32 0, i32 2, i32 8, i32 2, i32 1, i32 9, i32 0, i32 0>
2409;
2410  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 5, i32 4, i32 1, i32 3, i32 6, i32 9, i32 7, i32 5, i32 0, i32 3, i32 1, i32 8, i32 2, i32 8, i32 6>, <16 x i32> <i32 8, i32 0, i32 0, i32 8, i32 9, i32 2, i32 3, i32 3, i32 4, i32 2, i32 9, i32 2, i32 1, i32 9, i32 0, i32 6>, <16 x i32> <i32 1, i32 8, i32 4, i32 9, i32 1, i32 4, i32 1, i32 0, i32 9, i32 6, i32 9, i32 1, i32 0, i32 7, i32 4, i32 3>, i32 12)
2411  ret <16 x i32> %r
2412}
2413
2414define <2 x i64> @vpternlog_q_constv128_imm13() {
2415; CHECK-LABEL: @vpternlog_q_constv128_imm13(
2416; CHECK-NEXT:    ret <2 x i64> <i64 -10, i64 -8>
2417;
2418  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 6>, <2 x i64> <i64 1, i64 8>, <2 x i64> <i64 8, i64 7>, i32 13)
2419  ret <2 x i64> %r
2420}
2421
2422define <8 x i32> @vpternlog_d_constv256_imm14() {
2423; CHECK-LABEL: @vpternlog_d_constv256_imm14(
2424; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 1, i32 13, i32 2, i32 2, i32 6, i32 0, i32 8>
2425;
2426  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 6, i32 0, i32 5, i32 9, i32 1, i32 3, i32 1>, <8 x i32> <i32 4, i32 3, i32 9, i32 1, i32 3, i32 5, i32 2, i32 1>, <8 x i32> <i32 2, i32 2, i32 5, i32 3, i32 8, i32 6, i32 0, i32 8>, i32 14)
2427  ret <8 x i32> %r
2428}
2429
2430define <8 x i64> @vpternlog_q_constv512_imm15() {
2431; CHECK-LABEL: @vpternlog_q_constv512_imm15(
2432; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -4, i64 -10, i64 -10, i64 -5, i64 -7, i64 -4, i64 -6>
2433;
2434  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 3, i64 9, i64 9, i64 4, i64 6, i64 3, i64 5>, <8 x i64> <i64 0, i64 5, i64 5, i64 3, i64 4, i64 2, i64 5, i64 5>, <8 x i64> <i64 7, i64 5, i64 2, i64 6, i64 5, i64 2, i64 4, i64 1>, i32 15)
2435  ret <8 x i64> %r
2436}
2437
2438define <4 x i32> @vpternlog_d_constv128_imm16() {
2439; CHECK-LABEL: @vpternlog_d_constv128_imm16(
2440; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 8, i32 0, i32 4>
2441;
2442  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 8, i32 2, i32 7>, <4 x i32> <i32 5, i32 0, i32 0, i32 9>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>, i32 16)
2443  ret <4 x i32> %r
2444}
2445
2446define <4 x i64> @vpternlog_q_constv256_imm17() {
2447; CHECK-LABEL: @vpternlog_q_constv256_imm17(
2448; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -14, i64 -16, i64 -5>
2449;
2450  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 5, i64 2, i64 3>, <4 x i64> <i64 8, i64 5, i64 9, i64 0>, <4 x i64> <i64 0, i64 8, i64 6, i64 4>, i32 17)
2451  ret <4 x i64> %r
2452}
2453
2454define <16 x i32> @vpternlog_d_constv512_imm18() {
2455; CHECK-LABEL: @vpternlog_d_constv512_imm18(
2456; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 8, i32 0, i32 6, i32 1, i32 2, i32 10, i32 1, i32 0, i32 8, i32 0, i32 12, i32 0, i32 3, i32 1, i32 1>
2457;
2458  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 5, i32 7, i32 0, i32 1, i32 4, i32 9, i32 3, i32 7, i32 2, i32 0, i32 4, i32 3, i32 3, i32 7, i32 5>, <16 x i32> <i32 2, i32 7, i32 7, i32 1, i32 2, i32 5, i32 5, i32 6, i32 6, i32 7, i32 2, i32 1, i32 3, i32 4, i32 4, i32 6>, <16 x i32> <i32 8, i32 8, i32 7, i32 6, i32 2, i32 7, i32 2, i32 6, i32 1, i32 8, i32 0, i32 9, i32 0, i32 0, i32 6, i32 6>, i32 18)
2459  ret <16 x i32> %r
2460}
2461
2462define <2 x i64> @vpternlog_q_constv128_imm19() {
2463; CHECK-LABEL: @vpternlog_q_constv128_imm19(
2464; CHECK-NEXT:    ret <2 x i64> <i64 -3, i64 -1>
2465;
2466  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 4>, <2 x i64> <i64 2, i64 0>, <2 x i64> <i64 6, i64 8>, i32 19)
2467  ret <2 x i64> %r
2468}
2469
2470define <8 x i32> @vpternlog_d_constv256_imm20() {
2471; CHECK-LABEL: @vpternlog_d_constv256_imm20(
2472; CHECK-NEXT:    ret <8 x i32> <i32 8, i32 1, i32 6, i32 2, i32 1, i32 7, i32 8, i32 0>
2473;
2474  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 3, i32 5, i32 6, i32 1, i32 6, i32 8, i32 8>, <8 x i32> <i32 8, i32 2, i32 3, i32 4, i32 2, i32 1, i32 0, i32 8>, <8 x i32> <i32 5, i32 8, i32 1, i32 1, i32 2, i32 0, i32 7, i32 4>, i32 20)
2475  ret <8 x i32> %r
2476}
2477
2478define <8 x i64> @vpternlog_q_constv512_imm21() {
2479; CHECK-LABEL: @vpternlog_q_constv512_imm21(
2480; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -3, i64 -1, i64 -6, i64 -7, i64 -15, i64 -2, i64 -2>
2481;
2482  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 4, i64 9, i64 3, i64 3, i64 7, i64 3, i64 3>, <8 x i64> <i64 0, i64 3, i64 2, i64 1, i64 6, i64 6, i64 9, i64 4>, <8 x i64> <i64 6, i64 2, i64 0, i64 5, i64 4, i64 8, i64 1, i64 1>, i32 21)
2483  ret <8 x i64> %r
2484}
2485
2486define <4 x i32> @vpternlog_d_constv128_imm22() {
2487; CHECK-LABEL: @vpternlog_d_constv128_imm22(
2488; CHECK-NEXT:    ret <4 x i32> <i32 11, i32 0, i32 3, i32 14>
2489;
2490  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 9, i32 4, i32 2>, <4 x i32> <i32 8, i32 8, i32 6, i32 5>, <4 x i32> <i32 0, i32 1, i32 1, i32 9>, i32 22)
2491  ret <4 x i32> %r
2492}
2493
2494define <4 x i64> @vpternlog_q_constv256_imm23() {
2495; CHECK-LABEL: @vpternlog_q_constv256_imm23(
2496; CHECK-NEXT:    ret <4 x i64> <i64 -5, i64 -6, i64 -7, i64 -4>
2497;
2498  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 5, i64 6, i64 9>, <4 x i64> <i64 8, i64 8, i64 7, i64 3>, <4 x i64> <i64 6, i64 7, i64 0, i64 2>, i32 23)
2499  ret <4 x i64> %r
2500}
2501
2502define <16 x i32> @vpternlog_d_constv512_imm24() {
2503; CHECK-LABEL: @vpternlog_d_constv512_imm24(
2504; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 4, i32 8, i32 1, i32 0, i32 0, i32 2, i32 12, i32 0, i32 4, i32 0, i32 0, i32 0, i32 4, i32 0, i32 0>
2505;
2506  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 0, i32 9, i32 5, i32 6, i32 1, i32 4, i32 9, i32 5, i32 1, i32 0, i32 1, i32 5, i32 5, i32 9, i32 7>, <16 x i32> <i32 7, i32 6, i32 3, i32 6, i32 6, i32 9, i32 6, i32 6, i32 6, i32 6, i32 6, i32 7, i32 1, i32 1, i32 9, i32 7>, <16 x i32> <i32 5, i32 4, i32 4, i32 0, i32 6, i32 2, i32 6, i32 5, i32 1, i32 5, i32 1, i32 0, i32 4, i32 3, i32 5, i32 3>, i32 24)
2507  ret <16 x i32> %r
2508}
2509
2510define <2 x i64> @vpternlog_q_constv128_imm25() {
2511; CHECK-LABEL: @vpternlog_q_constv128_imm25(
2512; CHECK-NEXT:    ret <2 x i64> <i64 -7, i64 -8>
2513;
2514  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 3>, <2 x i64> <i64 2, i64 5>, <2 x i64> <i64 4, i64 3>, i32 25)
2515  ret <2 x i64> %r
2516}
2517
2518define <8 x i32> @vpternlog_d_constv256_imm26() {
2519; CHECK-LABEL: @vpternlog_d_constv256_imm26(
2520; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 1, i32 1, i32 10, i32 14, i32 0, i32 4, i32 2>
2521;
2522  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 4, i32 2, i32 9, i32 7, i32 6, i32 3, i32 3>, <8 x i32> <i32 3, i32 7, i32 2, i32 3, i32 9, i32 3, i32 6, i32 9>, <8 x i32> <i32 4, i32 1, i32 3, i32 3, i32 9, i32 6, i32 5, i32 0>, i32 26)
2523  ret <8 x i32> %r
2524}
2525
2526define <8 x i64> @vpternlog_q_constv512_imm27() {
2527; CHECK-LABEL: @vpternlog_q_constv512_imm27(
2528; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -7, i64 -12, i64 -2, i64 -9, i64 -2, i64 -14, i64 -3>
2529;
2530  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 8, i64 0, i64 1, i64 3, i64 9, i64 4>, <8 x i64> <i64 6, i64 6, i64 3, i64 7, i64 8, i64 1, i64 4, i64 2>, <8 x i64> <i64 6, i64 2, i64 8, i64 6, i64 0, i64 8, i64 9, i64 9>, i32 27)
2531  ret <8 x i64> %r
2532}
2533
2534define <4 x i32> @vpternlog_d_constv128_imm28() {
2535; CHECK-LABEL: @vpternlog_d_constv128_imm28(
2536; CHECK-NEXT:    ret <4 x i32> <i32 10, i32 15, i32 1, i32 2>
2537;
2538  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 9, i32 7, i32 3>, <4 x i32> <i32 9, i32 6, i32 6, i32 0>, <4 x i32> <i32 0, i32 6, i32 8, i32 5>, i32 28)
2539  ret <4 x i32> %r
2540}
2541
2542define <4 x i64> @vpternlog_q_constv256_imm29() {
2543; CHECK-LABEL: @vpternlog_q_constv256_imm29(
2544; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -3, i64 -9, i64 -4>
2545;
2546  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 2, i64 9, i64 3>, <4 x i64> <i64 1, i64 7, i64 8, i64 5>, <4 x i64> <i64 6, i64 1, i64 8, i64 7>, i32 29)
2547  ret <4 x i64> %r
2548}
2549
2550define <16 x i32> @vpternlog_d_constv512_imm30() {
2551; CHECK-LABEL: @vpternlog_d_constv512_imm30(
2552; CHECK-NEXT:    ret <16 x i32> <i32 15, i32 0, i32 14, i32 10, i32 7, i32 3, i32 3, i32 2, i32 15, i32 0, i32 12, i32 7, i32 5, i32 6, i32 10, i32 10>
2553;
2554  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 7, i32 0, i32 1, i32 1, i32 4, i32 6, i32 5, i32 1, i32 8, i32 3, i32 4, i32 2, i32 1, i32 8, i32 3>, <16 x i32> <i32 3, i32 7, i32 8, i32 9, i32 6, i32 5, i32 4, i32 7, i32 6, i32 8, i32 9, i32 0, i32 7, i32 6, i32 0, i32 0>, <16 x i32> <i32 5, i32 4, i32 6, i32 2, i32 4, i32 6, i32 1, i32 1, i32 8, i32 8, i32 7, i32 3, i32 2, i32 3, i32 2, i32 9>, i32 30)
2555  ret <16 x i32> %r
2556}
2557
2558define <2 x i64> @vpternlog_q_constv128_imm31() {
2559; CHECK-LABEL: @vpternlog_q_constv128_imm31(
2560; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -6>
2561;
2562  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 5>, <2 x i64> <i64 2, i64 1>, <2 x i64> <i64 7, i64 4>, i32 31)
2563  ret <2 x i64> %r
2564}
2565
2566define <8 x i32> @vpternlog_d_constv256_imm32() {
2567; CHECK-LABEL: @vpternlog_d_constv256_imm32(
2568; CHECK-NEXT:    ret <8 x i32> <i32 1, i32 0, i32 0, i32 0, i32 4, i32 4, i32 8, i32 0>
2569;
2570  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 0, i32 0, i32 4, i32 5, i32 7, i32 8, i32 9>, <8 x i32> <i32 6, i32 6, i32 0, i32 0, i32 1, i32 9, i32 3, i32 4>, <8 x i32> <i32 5, i32 9, i32 4, i32 0, i32 6, i32 5, i32 9, i32 6>, i32 32)
2571  ret <8 x i32> %r
2572}
2573
2574define <8 x i64> @vpternlog_q_constv512_imm33() {
2575; CHECK-LABEL: @vpternlog_q_constv512_imm33(
2576; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -15, i64 -14, i64 -4, i64 -8, i64 -13, i64 -5, i64 -3>
2577;
2578  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 8, i64 4, i64 7, i64 1, i64 0, i64 4, i64 1>, <8 x i64> <i64 0, i64 6, i64 0, i64 2, i64 3, i64 4, i64 4, i64 2>, <8 x i64> <i64 6, i64 0, i64 9, i64 6, i64 4, i64 8, i64 0, i64 3>, i32 33)
2579  ret <8 x i64> %r
2580}
2581
2582define <4 x i32> @vpternlog_d_constv128_imm34() {
2583; CHECK-LABEL: @vpternlog_d_constv128_imm34(
2584; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 0, i32 0, i32 4>
2585;
2586  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 5, i32 5, i32 8>, <4 x i32> <i32 7, i32 9, i32 7, i32 1>, <4 x i32> <i32 2, i32 1, i32 6, i32 5>, i32 34)
2587  ret <4 x i32> %r
2588}
2589
2590define <4 x i64> @vpternlog_q_constv256_imm35() {
2591; CHECK-LABEL: @vpternlog_q_constv256_imm35(
2592; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -10, i64 -10, i64 -1>
2593;
2594  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 1, i64 4, i64 3>, <4 x i64> <i64 6, i64 8, i64 9, i64 0>, <4 x i64> <i64 5, i64 0, i64 6, i64 7>, i32 35)
2595  ret <4 x i64> %r
2596}
2597
2598define <16 x i32> @vpternlog_d_constv512_imm36() {
2599; CHECK-LABEL: @vpternlog_d_constv512_imm36(
2600; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 1, i32 9, i32 0, i32 4, i32 1, i32 0, i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 6, i32 1, i32 0>
2601;
2602  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 5, i32 0, i32 2, i32 3, i32 9, i32 2, i32 0, i32 3, i32 6, i32 8, i32 4, i32 6, i32 8, i32 0, i32 6>, <16 x i32> <i32 8, i32 0, i32 9, i32 3, i32 6, i32 6, i32 8, i32 8, i32 0, i32 5, i32 8, i32 7, i32 6, i32 6, i32 1, i32 2>, <16 x i32> <i32 1, i32 1, i32 2, i32 7, i32 8, i32 7, i32 8, i32 2, i32 0, i32 5, i32 6, i32 3, i32 0, i32 1, i32 6, i32 2>, i32 36)
2603  ret <16 x i32> %r
2604}
2605
2606define <2 x i64> @vpternlog_q_constv128_imm37() {
2607; CHECK-LABEL: @vpternlog_q_constv128_imm37(
2608; CHECK-NEXT:    ret <2 x i64> <i64 -13, i64 -6>
2609;
2610  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 2>, <2 x i64> <i64 1, i64 5>, <2 x i64> <i64 4, i64 7>, i32 37)
2611  ret <2 x i64> %r
2612}
2613
2614define <8 x i32> @vpternlog_d_constv256_imm38() {
2615; CHECK-LABEL: @vpternlog_d_constv256_imm38(
2616; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 0, i32 12, i32 13, i32 3, i32 4, i32 14, i32 5>
2617;
2618  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 0, i32 9, i32 0, i32 6, i32 7, i32 7, i32 7, i32 8>, <8 x i32> <i32 2, i32 7, i32 9, i32 8, i32 4, i32 1, i32 9, i32 0>, <8 x i32> <i32 4, i32 7, i32 5, i32 5, i32 3, i32 4, i32 6, i32 5>, i32 38)
2619  ret <8 x i32> %r
2620}
2621
2622define <8 x i64> @vpternlog_q_constv512_imm39() {
2623; CHECK-LABEL: @vpternlog_q_constv512_imm39(
2624; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -7, i64 -2, i64 -4, i64 -8, i64 -5, i64 -2, i64 -7>
2625;
2626  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 4, i64 5, i64 3, i64 6, i64 4, i64 1, i64 6>, <8 x i64> <i64 2, i64 6, i64 9, i64 6, i64 7, i64 2, i64 9, i64 3>, <8 x i64> <i64 1, i64 7, i64 6, i64 2, i64 3, i64 9, i64 7, i64 0>, i32 39)
2627  ret <8 x i64> %r
2628}
2629
2630define <4 x i32> @vpternlog_d_constv128_imm40() {
2631; CHECK-LABEL: @vpternlog_d_constv128_imm40(
2632; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 4, i32 0, i32 2>
2633;
2634  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 5, i32 3, i32 2, i32 7>, <4 x i32> <i32 5, i32 4, i32 2, i32 4>, <4 x i32> <i32 2, i32 4, i32 0, i32 2>, i32 40)
2635  ret <4 x i32> %r
2636}
2637
2638define <4 x i64> @vpternlog_q_constv256_imm41() {
2639; CHECK-LABEL: @vpternlog_q_constv256_imm41(
2640; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -6, i64 -6, i64 -16>
2641;
2642  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 5, i64 5, i64 3>, <4 x i64> <i64 4, i64 3, i64 7, i64 5>, <4 x i64> <i64 6, i64 3, i64 6, i64 9>, i32 41)
2643  ret <4 x i64> %r
2644}
2645
2646define <16 x i32> @vpternlog_d_constv512_imm42() {
2647; CHECK-LABEL: @vpternlog_d_constv512_imm42(
2648; CHECK-NEXT:    ret <16 x i32> <i32 5, i32 5, i32 5, i32 6, i32 2, i32 7, i32 5, i32 1, i32 9, i32 2, i32 2, i32 8, i32 8, i32 4, i32 5, i32 6>
2649;
2650  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 0, i32 2, i32 8, i32 9, i32 5, i32 0, i32 8, i32 6, i32 6, i32 0, i32 2, i32 9, i32 8, i32 7, i32 3, i32 8>, <16 x i32> <i32 7, i32 2, i32 2, i32 3, i32 8, i32 7, i32 5, i32 4, i32 6, i32 1, i32 5, i32 5, i32 3, i32 3, i32 6, i32 0>, <16 x i32> <i32 5, i32 5, i32 5, i32 6, i32 2, i32 7, i32 5, i32 5, i32 9, i32 2, i32 2, i32 8, i32 8, i32 7, i32 5, i32 6>, i32 42)
2651  ret <16 x i32> %r
2652}
2653
2654define <2 x i64> @vpternlog_q_constv128_imm43() {
2655; CHECK-LABEL: @vpternlog_q_constv128_imm43(
2656; CHECK-NEXT:    ret <2 x i64> <i64 -12, i64 -4>
2657;
2658  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 3>, <2 x i64> <i64 8, i64 3>, <2 x i64> <i64 4, i64 9>, i32 43)
2659  ret <2 x i64> %r
2660}
2661
2662define <8 x i32> @vpternlog_d_constv256_imm44() {
2663; CHECK-LABEL: @vpternlog_d_constv256_imm44(
2664; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 4, i32 1, i32 1, i32 8, i32 4, i32 1, i32 2>
2665;
2666  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 0, i32 1, i32 7, i32 4, i32 5, i32 3, i32 8, i32 5>, <8 x i32> <i32 0, i32 5, i32 4, i32 1, i32 9, i32 6, i32 9, i32 6>, <8 x i32> <i32 3, i32 7, i32 1, i32 9, i32 3, i32 0, i32 9, i32 6>, i32 44)
2667  ret <8 x i32> %r
2668}
2669
2670define <8 x i64> @vpternlog_q_constv512_imm45() {
2671; CHECK-LABEL: @vpternlog_q_constv512_imm45(
2672; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -5, i64 -13, i64 -12, i64 -8, i64 -5, i64 -7, i64 -2>
2673;
2674  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 4, i64 9, i64 5, i64 4, i64 4, i64 3>, <8 x i64> <i64 9, i64 6, i64 3, i64 1, i64 9, i64 6, i64 0, i64 1>, <8 x i64> <i64 0, i64 5, i64 8, i64 2, i64 2, i64 2, i64 2, i64 3>, i32 45)
2675  ret <8 x i64> %r
2676}
2677
2678define <4 x i32> @vpternlog_d_constv128_imm46() {
2679; CHECK-LABEL: @vpternlog_d_constv128_imm46(
2680; CHECK-NEXT:    ret <4 x i32> <i32 9, i32 7, i32 4, i32 6>
2681;
2682  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 3, i32 9>, <4 x i32> <i32 1, i32 1, i32 7, i32 1>, <4 x i32> <i32 9, i32 7, i32 4, i32 6>, i32 46)
2683  ret <4 x i32> %r
2684}
2685
2686define <4 x i64> @vpternlog_q_constv256_imm47() {
2687; CHECK-LABEL: @vpternlog_q_constv256_imm47(
2688; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -5, i64 -1, i64 -1>
2689;
2690  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 4, i64 4, i64 1>, <4 x i64> <i64 8, i64 0, i64 9, i64 0>, <4 x i64> <i64 3, i64 1, i64 4, i64 3>, i32 47)
2691  ret <4 x i64> %r
2692}
2693
2694define <16 x i32> @vpternlog_d_constv512_imm48() {
2695; CHECK-LABEL: @vpternlog_d_constv512_imm48(
2696; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 0, i32 8, i32 8, i32 6, i32 0, i32 1, i32 3, i32 2, i32 1, i32 3, i32 2, i32 4, i32 8, i32 9, i32 0>
2697;
2698  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 7, i32 9, i32 9, i32 7, i32 5, i32 9, i32 3, i32 3, i32 5, i32 3, i32 2, i32 5, i32 8, i32 9, i32 4>, <16 x i32> <i32 7, i32 7, i32 1, i32 3, i32 9, i32 5, i32 8, i32 8, i32 1, i32 4, i32 0, i32 1, i32 3, i32 2, i32 2, i32 6>, <16 x i32> <i32 5, i32 0, i32 7, i32 5, i32 5, i32 0, i32 3, i32 9, i32 6, i32 6, i32 9, i32 4, i32 6, i32 7, i32 6, i32 1>, i32 48)
2699  ret <16 x i32> %r
2700}
2701
2702define <2 x i64> @vpternlog_q_constv128_imm49() {
2703; CHECK-LABEL: @vpternlog_q_constv128_imm49(
2704; CHECK-NEXT:    ret <2 x i64> <i64 -12, i64 -14>
2705;
2706  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 3, i64 4>, <2 x i64> <i64 8, i64 9>, i32 49)
2707  ret <2 x i64> %r
2708}
2709
2710define <8 x i32> @vpternlog_d_constv256_imm50() {
2711; CHECK-LABEL: @vpternlog_d_constv256_imm50(
2712; CHECK-NEXT:    ret <8 x i32> <i32 4, i32 11, i32 1, i32 5, i32 4, i32 6, i32 0, i32 0>
2713;
2714  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 9, i32 3, i32 6, i32 4, i32 4, i32 1, i32 1>, <8 x i32> <i32 1, i32 0, i32 6, i32 2, i32 1, i32 9, i32 7, i32 5>, <8 x i32> <i32 4, i32 3, i32 4, i32 3, i32 1, i32 6, i32 7, i32 4>, i32 50)
2715  ret <8 x i32> %r
2716}
2717
2718define <8 x i64> @vpternlog_q_constv512_imm51() {
2719; CHECK-LABEL: @vpternlog_q_constv512_imm51(
2720; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -3, i64 -4, i64 -2, i64 -6, i64 -1, i64 -2, i64 -8>
2721;
2722  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 0, i64 4, i64 1, i64 3, i64 3, i64 5, i64 0>, <8 x i64> <i64 1, i64 2, i64 3, i64 1, i64 5, i64 0, i64 1, i64 7>, <8 x i64> <i64 7, i64 6, i64 7, i64 8, i64 3, i64 7, i64 7, i64 8>, i32 51)
2723  ret <8 x i64> %r
2724}
2725
2726define <4 x i32> @vpternlog_d_constv128_imm52() {
2727; CHECK-LABEL: @vpternlog_d_constv128_imm52(
2728; CHECK-NEXT:    ret <4 x i32> <i32 9, i32 0, i32 6, i32 5>
2729;
2730  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 1, i32 4, i32 7>, <4 x i32> <i32 3, i32 7, i32 2, i32 2>, <4 x i32> <i32 2, i32 7, i32 8, i32 1>, i32 52)
2731  ret <4 x i32> %r
2732}
2733
2734define <4 x i64> @vpternlog_q_constv256_imm53() {
2735; CHECK-LABEL: @vpternlog_q_constv256_imm53(
2736; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -10, i64 -4, i64 -14>
2737;
2738  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 3, i64 0, i64 9>, <4 x i64> <i64 7, i64 1, i64 2, i64 9>, <4 x i64> <i64 5, i64 8, i64 3, i64 5>, i32 53)
2739  ret <4 x i64> %r
2740}
2741
2742define <16 x i32> @vpternlog_d_constv512_imm54() {
2743; CHECK-LABEL: @vpternlog_d_constv512_imm54(
2744; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 5, i32 7, i32 1, i32 12, i32 0, i32 8, i32 4, i32 6, i32 9, i32 13, i32 14, i32 2, i32 5, i32 15, i32 1>
2745;
2746  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 0, i32 5, i32 2, i32 3, i32 4, i32 4, i32 6, i32 7, i32 0, i32 9, i32 9, i32 0, i32 2, i32 1, i32 9>, <16 x i32> <i32 3, i32 6, i32 2, i32 3, i32 7, i32 6, i32 4, i32 3, i32 9, i32 9, i32 0, i32 7, i32 3, i32 3, i32 8, i32 8>, <16 x i32> <i32 4, i32 3, i32 1, i32 0, i32 8, i32 2, i32 8, i32 3, i32 8, i32 0, i32 4, i32 0, i32 1, i32 6, i32 6, i32 9>, i32 54)
2747  ret <16 x i32> %r
2748}
2749
2750define <2 x i64> @vpternlog_q_constv128_imm55() {
2751; CHECK-LABEL: @vpternlog_q_constv128_imm55(
2752; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -3>
2753;
2754  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 6, i64 0>, <2 x i64> <i64 4, i64 6>, <2 x i64> <i64 4, i64 2>, i32 55)
2755  ret <2 x i64> %r
2756}
2757
2758define <8 x i32> @vpternlog_d_constv256_imm56() {
2759; CHECK-LABEL: @vpternlog_d_constv256_imm56(
2760; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 5, i32 0, i32 1, i32 7, i32 9, i32 1, i32 0>
2761;
2762  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 5, i32 1, i32 4, i32 1, i32 9, i32 0, i32 4>, <8 x i32> <i32 9, i32 0, i32 9, i32 5, i32 6, i32 0, i32 3, i32 5>, <8 x i32> <i32 7, i32 5, i32 4, i32 1, i32 7, i32 7, i32 5, i32 6>, i32 56)
2763  ret <8 x i32> %r
2764}
2765
2766define <8 x i64> @vpternlog_q_constv512_imm57() {
2767; CHECK-LABEL: @vpternlog_q_constv512_imm57(
2768; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -5, i64 -6, i64 -9, i64 -4, i64 -7, i64 -5, i64 -5>
2769;
2770  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 0, i64 6, i64 6, i64 8, i64 7, i64 9, i64 8>, <8 x i64> <i64 9, i64 4, i64 5, i64 9, i64 0, i64 6, i64 6, i64 0>, <8 x i64> <i64 0, i64 0, i64 4, i64 1, i64 3, i64 6, i64 2, i64 4>, i32 57)
2771  ret <8 x i64> %r
2772}
2773
2774define <4 x i32> @vpternlog_d_constv128_imm58() {
2775; CHECK-LABEL: @vpternlog_d_constv128_imm58(
2776; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 1, i32 15, i32 6>
2777;
2778  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 5, i32 7, i32 7>, <4 x i32> <i32 9, i32 6, i32 0, i32 1>, <4 x i32> <i32 2, i32 1, i32 9, i32 7>, i32 58)
2779  ret <4 x i32> %r
2780}
2781
2782define <4 x i64> @vpternlog_q_constv256_imm59() {
2783; CHECK-LABEL: @vpternlog_q_constv256_imm59(
2784; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -9, i64 -7, i64 -10>
2785;
2786  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 2, i64 6, i64 6>, <4 x i64> <i64 8, i64 8, i64 7, i64 9>, <4 x i64> <i64 4, i64 5, i64 5, i64 6>, i32 59)
2787  ret <4 x i64> %r
2788}
2789
2790define <16 x i32> @vpternlog_d_constv512_imm60() {
2791; CHECK-LABEL: @vpternlog_d_constv512_imm60(
2792; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 4, i32 13, i32 0, i32 14, i32 0, i32 2, i32 0, i32 4, i32 0, i32 1, i32 3, i32 2, i32 11, i32 2, i32 15>
2793;
2794  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 7, i32 5, i32 7, i32 6, i32 5, i32 6, i32 7, i32 3, i32 9, i32 7, i32 6, i32 0, i32 3, i32 5, i32 8>, <16 x i32> <i32 5, i32 3, i32 8, i32 7, i32 8, i32 5, i32 4, i32 7, i32 7, i32 9, i32 6, i32 5, i32 2, i32 8, i32 7, i32 7>, <16 x i32> <i32 2, i32 1, i32 2, i32 1, i32 7, i32 3, i32 6, i32 3, i32 5, i32 1, i32 9, i32 4, i32 4, i32 1, i32 1, i32 8>, i32 60)
2795  ret <16 x i32> %r
2796}
2797
2798define <2 x i64> @vpternlog_q_constv128_imm61() {
2799; CHECK-LABEL: @vpternlog_q_constv128_imm61(
2800; CHECK-NEXT:    ret <2 x i64> splat (i64 -5)
2801;
2802  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 9>, <2 x i64> <i64 1, i64 0>, <2 x i64> <i64 5, i64 4>, i32 61)
2803  ret <2 x i64> %r
2804}
2805
2806define <8 x i32> @vpternlog_d_constv256_imm62() {
2807; CHECK-LABEL: @vpternlog_d_constv256_imm62(
2808; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 11, i32 15, i32 13, i32 4, i32 10, i32 4, i32 15>
2809;
2810  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 6, i32 0, i32 8, i32 2, i32 1, i32 3, i32 6>, <8 x i32> <i32 3, i32 4, i32 8, i32 0, i32 6, i32 3, i32 7, i32 9>, <8 x i32> <i32 0, i32 9, i32 7, i32 5, i32 6, i32 8, i32 2, i32 0>, i32 62)
2811  ret <8 x i32> %r
2812}
2813
2814define <8 x i64> @vpternlog_q_constv512_imm63() {
2815; CHECK-LABEL: @vpternlog_q_constv512_imm63(
2816; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -10, i64 -1, i64 -2, i64 -4>
2817;
2818  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 4, i64 6, i64 0, i64 9, i64 8, i64 3, i64 3>, <8 x i64> <i64 4, i64 0, i64 8, i64 5, i64 9, i64 4, i64 1, i64 7>, <8 x i64> <i64 2, i64 7, i64 4, i64 5, i64 5, i64 6, i64 6, i64 4>, i32 63)
2819  ret <8 x i64> %r
2820}
2821
2822define <4 x i32> @vpternlog_d_constv128_imm64() {
2823; CHECK-LABEL: @vpternlog_d_constv128_imm64(
2824; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 0, i32 2, i32 0>
2825;
2826  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 3, i32 3, i32 4>, <4 x i32> <i32 6, i32 4, i32 7, i32 6>, <4 x i32> <i32 5, i32 5, i32 9, i32 4>, i32 64)
2827  ret <4 x i32> %r
2828}
2829
2830define <4 x i64> @vpternlog_q_constv256_imm65() {
2831; CHECK-LABEL: @vpternlog_q_constv256_imm65(
2832; CHECK-NEXT:    ret <4 x i64> <i64 -15, i64 -16, i64 -4, i64 -12>
2833;
2834  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 7, i64 0, i64 4, i64 9>, <4 x i64> <i64 1, i64 9, i64 7, i64 2>, <4 x i64> <i64 8, i64 6, i64 1, i64 3>, i32 65)
2835  ret <4 x i64> %r
2836}
2837
2838define <16 x i32> @vpternlog_d_constv512_imm66() {
2839; CHECK-LABEL: @vpternlog_d_constv512_imm66(
2840; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 0, i32 9, i32 4, i32 6, i32 0, i32 2, i32 8, i32 2, i32 1, i32 10, i32 0, i32 9, i32 0, i32 4, i32 5>
2841;
2842  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 8, i32 8, i32 0, i32 0, i32 8, i32 6, i32 6, i32 5, i32 4, i32 9, i32 6, i32 1, i32 3, i32 5, i32 3>, <16 x i32> <i32 4, i32 1, i32 8, i32 3, i32 8, i32 3, i32 2, i32 1, i32 4, i32 0, i32 8, i32 7, i32 1, i32 0, i32 6, i32 1>, <16 x i32> <i32 0, i32 8, i32 1, i32 5, i32 6, i32 8, i32 0, i32 9, i32 7, i32 1, i32 3, i32 7, i32 8, i32 2, i32 0, i32 4>, i32 66)
2843  ret <16 x i32> %r
2844}
2845
2846define <2 x i64> @vpternlog_q_constv128_imm67() {
2847; CHECK-LABEL: @vpternlog_q_constv128_imm67(
2848; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -6>
2849;
2850  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 5>, <2 x i64> <i64 5, i64 0>, <2 x i64> <i64 5, i64 1>, i32 67)
2851  ret <2 x i64> %r
2852}
2853
2854define <8 x i32> @vpternlog_d_constv256_imm68() {
2855; CHECK-LABEL: @vpternlog_d_constv256_imm68(
2856; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 1, i32 0, i32 0, i32 4, i32 8, i32 2>
2857;
2858  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 1, i32 4, i32 1, i32 4, i32 6, i32 6, i32 2>, <8 x i32> <i32 2, i32 1, i32 1, i32 2, i32 1, i32 7, i32 9, i32 2>, <8 x i32> <i32 3, i32 5, i32 4, i32 3, i32 7, i32 3, i32 7, i32 5>, i32 68)
2859  ret <8 x i32> %r
2860}
2861
2862define <8 x i64> @vpternlog_q_constv512_imm69() {
2863; CHECK-LABEL: @vpternlog_q_constv512_imm69(
2864; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -1, i64 -5, i64 -8, i64 -10, i64 -10, i64 -14, i64 -14>
2865;
2866  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 0, i64 2, i64 7, i64 3, i64 8, i64 8, i64 4>, <8 x i64> <i64 0, i64 5, i64 6, i64 0, i64 2, i64 7, i64 7, i64 1>, <8 x i64> <i64 9, i64 0, i64 4, i64 2, i64 8, i64 9, i64 5, i64 9>, i32 69)
2867  ret <8 x i64> %r
2868}
2869
2870define <4 x i32> @vpternlog_d_constv128_imm70() {
2871; CHECK-LABEL: @vpternlog_d_constv128_imm70(
2872; CHECK-NEXT:    ret <4 x i32> <i32 4, i32 10, i32 4, i32 4>
2873;
2874  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 1, i32 9, i32 2>, <4 x i32> <i32 6, i32 2, i32 5, i32 3>, <4 x i32> <i32 2, i32 9, i32 1, i32 7>, i32 70)
2875  ret <4 x i32> %r
2876}
2877
2878define <4 x i64> @vpternlog_q_constv256_imm71() {
2879; CHECK-LABEL: @vpternlog_q_constv256_imm71(
2880; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -9, i64 -7, i64 -1>
2881;
2882  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 8, i64 6, i64 0>, <4 x i64> <i64 0, i64 4, i64 8, i64 8>, <4 x i64> <i64 1, i64 1, i64 1, i64 6>, i32 71)
2883  ret <4 x i64> %r
2884}
2885
2886define <16 x i32> @vpternlog_d_constv512_imm72() {
2887; CHECK-LABEL: @vpternlog_d_constv512_imm72(
2888; CHECK-NEXT:    ret <16 x i32> <i32 2, i32 4, i32 0, i32 8, i32 0, i32 4, i32 0, i32 0, i32 5, i32 2, i32 4, i32 0, i32 0, i32 8, i32 0, i32 0>
2889;
2890  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 8, i32 8, i32 1, i32 1, i32 1, i32 1, i32 4, i32 1, i32 7, i32 8, i32 5, i32 8, i32 8, i32 1, i32 2>, <16 x i32> <i32 2, i32 4, i32 2, i32 8, i32 9, i32 6, i32 1, i32 8, i32 5, i32 6, i32 4, i32 2, i32 0, i32 8, i32 0, i32 0>, <16 x i32> <i32 3, i32 5, i32 4, i32 9, i32 1, i32 5, i32 1, i32 3, i32 4, i32 5, i32 5, i32 1, i32 7, i32 7, i32 1, i32 8>, i32 72)
2891  ret <16 x i32> %r
2892}
2893
2894define <2 x i64> @vpternlog_q_constv128_imm73() {
2895; CHECK-LABEL: @vpternlog_q_constv128_imm73(
2896; CHECK-NEXT:    ret <2 x i64> <i64 -8, i64 -7>
2897;
2898  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 2>, <2 x i64> <i64 3, i64 1>, <2 x i64> <i64 7, i64 7>, i32 73)
2899  ret <2 x i64> %r
2900}
2901
2902define <8 x i32> @vpternlog_d_constv256_imm74() {
2903; CHECK-LABEL: @vpternlog_d_constv256_imm74(
2904; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 3, i32 1, i32 4, i32 4, i32 8, i32 6, i32 6>
2905;
2906  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 4, i32 5, i32 3, i32 4, i32 0, i32 0, i32 5>, <8 x i32> <i32 2, i32 6, i32 5, i32 8, i32 4, i32 5, i32 0, i32 5>, <8 x i32> <i32 2, i32 7, i32 4, i32 4, i32 0, i32 8, i32 6, i32 3>, i32 74)
2907  ret <8 x i32> %r
2908}
2909
2910define <8 x i64> @vpternlog_q_constv512_imm75() {
2911; CHECK-LABEL: @vpternlog_q_constv512_imm75(
2912; CHECK-NEXT:    ret <8 x i64> <i64 -7, i64 -8, i64 -1, i64 -9, i64 -7, i64 -6, i64 -4, i64 -1>
2913;
2914  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 1, i64 1, i64 9, i64 6, i64 7, i64 3, i64 0>, <8 x i64> <i64 0, i64 6, i64 1, i64 1, i64 2, i64 6, i64 2, i64 4>, <8 x i64> <i64 1, i64 8, i64 4, i64 8, i64 2, i64 4, i64 7, i64 5>, i32 75)
2915  ret <8 x i64> %r
2916}
2917
2918define <4 x i32> @vpternlog_d_constv128_imm76() {
2919; CHECK-LABEL: @vpternlog_d_constv128_imm76(
2920; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 1, i32 2, i32 2>
2921;
2922  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 0, i32 0, i32 3>, <4 x i32> <i32 7, i32 1, i32 2, i32 2>, <4 x i32> <i32 6, i32 7, i32 8, i32 4>, i32 76)
2923  ret <4 x i32> %r
2924}
2925
2926define <4 x i64> @vpternlog_q_constv256_imm77() {
2927; CHECK-LABEL: @vpternlog_q_constv256_imm77(
2928; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -3, i64 -1, i64 -6>
2929;
2930  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 4, i64 6, i64 5>, <4 x i64> <i64 5, i64 5, i64 7, i64 8>, <4 x i64> <i64 8, i64 2, i64 1, i64 1>, i32 77)
2931  ret <4 x i64> %r
2932}
2933
2934define <16 x i32> @vpternlog_d_constv512_imm78() {
2935; CHECK-LABEL: @vpternlog_d_constv512_imm78(
2936; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 2, i32 4, i32 2, i32 10, i32 9, i32 14, i32 15, i32 14, i32 2, i32 5, i32 6, i32 4, i32 8, i32 7, i32 7>
2937;
2938  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 3, i32 3, i32 5, i32 2, i32 6, i32 8, i32 2, i32 9, i32 5, i32 2, i32 1, i32 5, i32 7, i32 0, i32 3>, <16 x i32> <i32 0, i32 2, i32 4, i32 2, i32 2, i32 9, i32 8, i32 7, i32 8, i32 2, i32 7, i32 3, i32 4, i32 0, i32 5, i32 7>, <16 x i32> <i32 2, i32 0, i32 4, i32 3, i32 8, i32 2, i32 6, i32 9, i32 7, i32 4, i32 2, i32 7, i32 0, i32 8, i32 6, i32 4>, i32 78)
2939  ret <16 x i32> %r
2940}
2941
2942define <2 x i64> @vpternlog_q_constv128_imm79() {
2943; CHECK-LABEL: @vpternlog_q_constv128_imm79(
2944; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -9>
2945;
2946  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 8>, <2 x i64> <i64 6, i64 2>, <2 x i64> <i64 1, i64 2>, i32 79)
2947  ret <2 x i64> %r
2948}
2949
2950define <8 x i32> @vpternlog_d_constv256_imm80() {
2951; CHECK-LABEL: @vpternlog_d_constv256_imm80(
2952; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 8, i32 8, i32 2, i32 4, i32 8, i32 4, i32 0>
2953;
2954  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 9, i32 9, i32 3, i32 5, i32 9, i32 7, i32 1>, <8 x i32> <i32 3, i32 1, i32 8, i32 2, i32 1, i32 6, i32 0, i32 1>, <8 x i32> <i32 7, i32 7, i32 3, i32 5, i32 9, i32 7, i32 3, i32 7>, i32 80)
2955  ret <8 x i32> %r
2956}
2957
2958define <8 x i64> @vpternlog_q_constv512_imm81() {
2959; CHECK-LABEL: @vpternlog_q_constv512_imm81(
2960; CHECK-NEXT:    ret <8 x i64> <i64 -8, i64 -13, i64 -16, i64 -8, i64 -5, i64 -8, i64 -7, i64 -8>
2961;
2962  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 0, i64 1, i64 6, i64 7, i64 8, i64 0, i64 2>, <8 x i64> <i64 5, i64 8, i64 6, i64 1, i64 1, i64 4, i64 2, i64 7>, <8 x i64> <i64 7, i64 4, i64 9, i64 6, i64 4, i64 3, i64 4, i64 6>, i32 81)
2963  ret <8 x i64> %r
2964}
2965
2966define <4 x i32> @vpternlog_d_constv128_imm82() {
2967; CHECK-LABEL: @vpternlog_d_constv128_imm82(
2968; CHECK-NEXT:    ret <4 x i32> <i32 3, i32 1, i32 3, i32 7>
2969;
2970  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 2, i32 7, i32 6>, <4 x i32> <i32 9, i32 4, i32 1, i32 4>, <4 x i32> <i32 2, i32 7, i32 4, i32 1>, i32 82)
2971  ret <4 x i32> %r
2972}
2973
2974define <4 x i64> @vpternlog_q_constv256_imm83() {
2975; CHECK-LABEL: @vpternlog_q_constv256_imm83(
2976; CHECK-NEXT:    ret <4 x i64> <i64 -5, i64 -4, i64 -4, i64 -13>
2977;
2978  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 0, i64 0, i64 4>, <4 x i64> <i64 4, i64 3, i64 3, i64 8>, <4 x i64> <i64 1, i64 6, i64 5, i64 6>, i32 83)
2979  ret <4 x i64> %r
2980}
2981
2982define <16 x i32> @vpternlog_d_constv512_imm84() {
2983; CHECK-LABEL: @vpternlog_d_constv512_imm84(
2984; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 8, i32 2, i32 0, i32 0, i32 6, i32 3, i32 2, i32 10, i32 1, i32 4, i32 3, i32 8, i32 3, i32 1, i32 3>
2985;
2986  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 9, i32 0, i32 4, i32 1, i32 6, i32 4, i32 5, i32 7, i32 4, i32 4, i32 4, i32 9, i32 3, i32 0, i32 0>, <16 x i32> <i32 1, i32 1, i32 2, i32 4, i32 3, i32 8, i32 7, i32 3, i32 8, i32 5, i32 4, i32 7, i32 0, i32 9, i32 1, i32 3>, <16 x i32> <i32 5, i32 1, i32 0, i32 5, i32 3, i32 8, i32 4, i32 5, i32 5, i32 6, i32 3, i32 4, i32 5, i32 8, i32 2, i32 8>, i32 84)
2987  ret <16 x i32> %r
2988}
2989
2990define <2 x i64> @vpternlog_q_constv128_imm85() {
2991; CHECK-LABEL: @vpternlog_q_constv128_imm85(
2992; CHECK-NEXT:    ret <2 x i64> <i64 -10, i64 -7>
2993;
2994  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 8>, <2 x i64> <i64 0, i64 9>, <2 x i64> <i64 9, i64 6>, i32 85)
2995  ret <2 x i64> %r
2996}
2997
2998define <8 x i32> @vpternlog_d_constv256_imm86() {
2999; CHECK-LABEL: @vpternlog_d_constv256_imm86(
3000; CHECK-NEXT:    ret <8 x i32> <i32 13, i32 7, i32 13, i32 12, i32 7, i32 1, i32 6, i32 7>
3001;
3002  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 5, i32 8, i32 5, i32 6, i32 1, i32 6, i32 1>, <8 x i32> <i32 0, i32 3, i32 7, i32 5, i32 5, i32 5, i32 6, i32 6>, <8 x i32> <i32 9, i32 0, i32 2, i32 9, i32 0, i32 4, i32 0, i32 0>, i32 86)
3003  ret <8 x i32> %r
3004}
3005
3006define <8 x i64> @vpternlog_q_constv512_imm87() {
3007; CHECK-LABEL: @vpternlog_q_constv512_imm87(
3008; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -2, i64 -1, i64 -7, i64 -5, i64 -2, i64 -5, i64 -5>
3009;
3010  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 3, i64 5, i64 6, i64 7, i64 8, i64 0, i64 7>, <8 x i64> <i64 0, i64 6, i64 0, i64 0, i64 1, i64 3, i64 4, i64 6>, <8 x i64> <i64 8, i64 9, i64 8, i64 7, i64 4, i64 5, i64 4, i64 4>, i32 87)
3011  ret <8 x i64> %r
3012}
3013
3014define <4 x i32> @vpternlog_d_constv128_imm88() {
3015; CHECK-LABEL: @vpternlog_d_constv128_imm88(
3016; CHECK-NEXT:    ret <4 x i32> <i32 8, i32 2, i32 3, i32 12>
3017;
3018  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 2, i32 0, i32 8>, <4 x i32> <i32 0, i32 8, i32 3, i32 4>, <4 x i32> <i32 5, i32 5, i32 3, i32 5>, i32 88)
3019  ret <4 x i32> %r
3020}
3021
3022define <4 x i64> @vpternlog_q_constv256_imm89() {
3023; CHECK-LABEL: @vpternlog_q_constv256_imm89(
3024; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -3, i64 -8, i64 -4>
3025;
3026  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 4, i64 0, i64 0>, <4 x i64> <i64 5, i64 5, i64 2, i64 6>, <4 x i64> <i64 4, i64 3, i64 5, i64 5>, i32 89)
3027  ret <4 x i64> %r
3028}
3029
3030define <16 x i32> @vpternlog_d_constv512_imm90() {
3031; CHECK-LABEL: @vpternlog_d_constv512_imm90(
3032; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 3, i32 13, i32 9, i32 11, i32 1, i32 3, i32 2, i32 15, i32 7, i32 1, i32 12, i32 13, i32 9, i32 12, i32 12>
3033;
3034  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 0, i32 8, i32 9, i32 2, i32 1, i32 2, i32 5, i32 6, i32 5, i32 3, i32 9, i32 4, i32 8, i32 5, i32 5>, <16 x i32> <i32 2, i32 9, i32 6, i32 8, i32 3, i32 3, i32 4, i32 0, i32 2, i32 7, i32 7, i32 2, i32 6, i32 8, i32 2, i32 8>, <16 x i32> <i32 2, i32 3, i32 5, i32 0, i32 9, i32 0, i32 1, i32 7, i32 9, i32 2, i32 2, i32 5, i32 9, i32 1, i32 9, i32 9>, i32 90)
3035  ret <16 x i32> %r
3036}
3037
3038define <2 x i64> @vpternlog_q_constv128_imm91() {
3039; CHECK-LABEL: @vpternlog_q_constv128_imm91(
3040; CHECK-NEXT:    ret <2 x i64> splat (i64 -1)
3041;
3042  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 5>, <2 x i64> <i64 0, i64 2>, <2 x i64> <i64 4, i64 2>, i32 91)
3043  ret <2 x i64> %r
3044}
3045
3046define <8 x i32> @vpternlog_d_constv256_imm92() {
3047; CHECK-LABEL: @vpternlog_d_constv256_imm92(
3048; CHECK-NEXT:    ret <8 x i32> <i32 5, i32 13, i32 4, i32 11, i32 7, i32 9, i32 12, i32 4>
3049;
3050  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 8, i32 1, i32 8, i32 7, i32 4, i32 9, i32 9>, <8 x i32> <i32 5, i32 5, i32 4, i32 3, i32 6, i32 9, i32 5, i32 4>, <8 x i32> <i32 2, i32 1, i32 7, i32 3, i32 8, i32 7, i32 1, i32 9>, i32 92)
3051  ret <8 x i32> %r
3052}
3053
3054define <8 x i64> @vpternlog_q_constv512_imm93() {
3055; CHECK-LABEL: @vpternlog_q_constv512_imm93(
3056; CHECK-NEXT:    ret <8 x i64> <i64 -5, i64 -9, i64 -8, i64 -5, i64 -6, i64 -1, i64 -1, i64 -3>
3057;
3058  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 2, i64 4, i64 9, i64 9, i64 0, i64 9, i64 3>, <8 x i64> <i64 3, i64 5, i64 8, i64 9, i64 1, i64 5, i64 5, i64 6>, <8 x i64> <i64 7, i64 8, i64 7, i64 4, i64 5, i64 4, i64 4, i64 6>, i32 93)
3059  ret <8 x i64> %r
3060}
3061
3062define <4 x i32> @vpternlog_d_constv128_imm94() {
3063; CHECK-LABEL: @vpternlog_d_constv128_imm94(
3064; CHECK-NEXT:    ret <4 x i32> <i32 15, i32 13, i32 12, i32 7>
3065;
3066  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 4, i32 4, i32 0>, <4 x i32> <i32 8, i32 9, i32 4, i32 5>, <4 x i32> <i32 1, i32 1, i32 8, i32 2>, i32 94)
3067  ret <4 x i32> %r
3068}
3069
3070define <4 x i64> @vpternlog_q_constv256_imm95() {
3071; CHECK-LABEL: @vpternlog_q_constv256_imm95(
3072; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -1, i64 -5, i64 -1>
3073;
3074  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 5, i64 7, i64 4>, <4 x i64> <i64 5, i64 6, i64 1, i64 1>, <4 x i64> <i64 1, i64 8, i64 4, i64 8>, i32 95)
3075  ret <4 x i64> %r
3076}
3077
3078define <16 x i32> @vpternlog_d_constv512_imm96() {
3079; CHECK-LABEL: @vpternlog_d_constv512_imm96(
3080; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 4, i32 4, i32 2, i32 9, i32 0, i32 2, i32 0, i32 0, i32 4, i32 2, i32 0, i32 0, i32 0, i32 0, i32 9>
3081;
3082  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 6, i32 4, i32 6, i32 9, i32 0, i32 3, i32 8, i32 9, i32 5, i32 2, i32 0, i32 0, i32 2, i32 4, i32 9>, <16 x i32> <i32 5, i32 4, i32 5, i32 2, i32 9, i32 3, i32 2, i32 7, i32 6, i32 0, i32 2, i32 4, i32 8, i32 5, i32 5, i32 8>, <16 x i32> <i32 5, i32 0, i32 8, i32 8, i32 4, i32 5, i32 8, i32 2, i32 4, i32 4, i32 5, i32 5, i32 3, i32 1, i32 6, i32 5>, i32 96)
3083  ret <16 x i32> %r
3084}
3085
3086define <2 x i64> @vpternlog_q_constv128_imm97() {
3087; CHECK-LABEL: @vpternlog_q_constv128_imm97(
3088; CHECK-NEXT:    ret <2 x i64> splat (i64 -14)
3089;
3090  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 3>, <2 x i64> <i64 8, i64 6>, <2 x i64> <i64 6, i64 8>, i32 97)
3091  ret <2 x i64> %r
3092}
3093
3094define <8 x i32> @vpternlog_d_constv256_imm98() {
3095; CHECK-LABEL: @vpternlog_d_constv256_imm98(
3096; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 4, i32 2, i32 8, i32 14, i32 6, i32 0, i32 8>
3097;
3098  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 4, i32 2, i32 9, i32 9, i32 6, i32 5, i32 0>, <8 x i32> <i32 1, i32 4, i32 5, i32 1, i32 8, i32 5, i32 4, i32 6>, <8 x i32> <i32 6, i32 0, i32 6, i32 9, i32 6, i32 2, i32 4, i32 8>, i32 98)
3099  ret <8 x i32> %r
3100}
3101
3102define <8 x i64> @vpternlog_q_constv512_imm99() {
3103; CHECK-LABEL: @vpternlog_q_constv512_imm99(
3104; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -16, i64 -5, i64 -3, i64 -6, i64 -4, i64 -10, i64 -2>
3105;
3106  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 9, i64 5, i64 0, i64 8, i64 0, i64 2, i64 0>, <8 x i64> <i64 9, i64 6, i64 0, i64 2, i64 5, i64 3, i64 9, i64 1>, <8 x i64> <i64 3, i64 2, i64 1, i64 0, i64 9, i64 7, i64 7, i64 8>, i32 99)
3107  ret <8 x i64> %r
3108}
3109
3110define <4 x i32> @vpternlog_d_constv128_imm100() {
3111; CHECK-LABEL: @vpternlog_d_constv128_imm100(
3112; CHECK-NEXT:    ret <4 x i32> <i32 9, i32 0, i32 3, i32 6>
3113;
3114  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 2, i32 3, i32 5>, <4 x i32> <i32 9, i32 2, i32 2, i32 7>, <4 x i32> <i32 4, i32 7, i32 1, i32 9>, i32 100)
3115  ret <4 x i32> %r
3116}
3117
3118define <4 x i64> @vpternlog_q_constv256_imm101() {
3119; CHECK-LABEL: @vpternlog_q_constv256_imm101(
3120; CHECK-NEXT:    ret <4 x i64> <i64 -12, i64 -4, i64 -8, i64 -8>
3121;
3122  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 6, i64 2, i64 6>, <4 x i64> <i64 4, i64 0, i64 4, i64 1>, <4 x i64> <i64 9, i64 5, i64 5, i64 1>, i32 101)
3123  ret <4 x i64> %r
3124}
3125
3126define <16 x i32> @vpternlog_d_constv512_imm102() {
3127; CHECK-LABEL: @vpternlog_d_constv512_imm102(
3128; CHECK-NEXT:    ret <16 x i32> <i32 6, i32 5, i32 1, i32 3, i32 4, i32 5, i32 11, i32 15, i32 2, i32 2, i32 6, i32 0, i32 5, i32 2, i32 7, i32 4>
3129;
3130  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 6, i32 3, i32 9, i32 4, i32 9, i32 8, i32 8, i32 3, i32 3, i32 8, i32 3, i32 4, i32 9, i32 2, i32 6, i32 5>, <16 x i32> <i32 2, i32 7, i32 7, i32 0, i32 1, i32 4, i32 2, i32 7, i32 7, i32 1, i32 1, i32 6, i32 4, i32 0, i32 1, i32 3>, <16 x i32> <i32 4, i32 2, i32 6, i32 3, i32 5, i32 1, i32 9, i32 8, i32 5, i32 3, i32 7, i32 6, i32 1, i32 2, i32 6, i32 7>, i32 102)
3131  ret <16 x i32> %r
3132}
3133
3134define <2 x i64> @vpternlog_q_constv128_imm103() {
3135; CHECK-LABEL: @vpternlog_q_constv128_imm103(
3136; CHECK-NEXT:    ret <2 x i64> splat (i64 -1)
3137;
3138  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 2>, <2 x i64> <i64 2, i64 2>, <2 x i64> <i64 5, i64 1>, i32 103)
3139  ret <2 x i64> %r
3140}
3141
3142define <8 x i32> @vpternlog_d_constv256_imm104() {
3143; CHECK-LABEL: @vpternlog_d_constv256_imm104(
3144; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 1, i32 4, i32 0, i32 2, i32 1, i32 0, i32 5>
3145;
3146  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 3, i32 6, i32 5, i32 8, i32 1, i32 5, i32 5>, <8 x i32> <i32 6, i32 7, i32 8, i32 8, i32 6, i32 9, i32 3, i32 7>, <8 x i32> <i32 8, i32 2, i32 4, i32 0, i32 2, i32 4, i32 9, i32 8>, i32 104)
3147  ret <8 x i32> %r
3148}
3149
3150define <8 x i64> @vpternlog_q_constv512_imm105() {
3151; CHECK-LABEL: @vpternlog_q_constv512_imm105(
3152; CHECK-NEXT:    ret <8 x i64> <i64 -15, i64 -2, i64 -11, i64 -12, i64 -3, i64 -3, i64 -6, i64 -8>
3153;
3154  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 1, i64 5, i64 6, i64 1, i64 4, i64 1, i64 2>, <8 x i64> <i64 8, i64 7, i64 7, i64 5, i64 1, i64 2, i64 0, i64 5>, <8 x i64> <i64 7, i64 7, i64 8, i64 8, i64 2, i64 4, i64 4, i64 0>, i32 105)
3155  ret <8 x i64> %r
3156}
3157
3158define <4 x i32> @vpternlog_d_constv128_imm106() {
3159; CHECK-LABEL: @vpternlog_d_constv128_imm106(
3160; CHECK-NEXT:    ret <4 x i32> <i32 5, i32 4, i32 3, i32 0>
3161;
3162  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 7, i32 9, i32 4>, <4 x i32> <i32 7, i32 1, i32 4, i32 6>, <4 x i32> <i32 4, i32 5, i32 3, i32 4>, i32 106)
3163  ret <4 x i32> %r
3164}
3165
3166define <4 x i64> @vpternlog_q_constv256_imm107() {
3167; CHECK-LABEL: @vpternlog_q_constv256_imm107(
3168; CHECK-NEXT:    ret <4 x i64> <i64 -10, i64 -5, i64 -5, i64 -6>
3169;
3170  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 4, i64 4, i64 0, i64 1>, <4 x i64> <i64 9, i64 0, i64 4, i64 4>, <4 x i64> <i64 6, i64 1, i64 8, i64 8>, i32 107)
3171  ret <4 x i64> %r
3172}
3173
3174define <16 x i32> @vpternlog_d_constv512_imm108() {
3175; CHECK-LABEL: @vpternlog_d_constv512_imm108(
3176; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 3, i32 9, i32 3, i32 8, i32 15, i32 1, i32 2, i32 5, i32 5, i32 8, i32 4, i32 10, i32 4, i32 1, i32 0>
3177;
3178  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 7, i32 3, i32 0, i32 0, i32 6, i32 6, i32 2, i32 2, i32 5, i32 0, i32 2, i32 3, i32 4, i32 6, i32 5>, <16 x i32> <i32 9, i32 1, i32 9, i32 3, i32 8, i32 9, i32 5, i32 0, i32 5, i32 0, i32 8, i32 4, i32 9, i32 4, i32 7, i32 0>, <16 x i32> <i32 8, i32 2, i32 0, i32 4, i32 7, i32 6, i32 5, i32 2, i32 4, i32 5, i32 7, i32 8, i32 7, i32 9, i32 6, i32 8>, i32 108)
3179  ret <16 x i32> %r
3180}
3181
3182define <2 x i64> @vpternlog_q_constv128_imm109() {
3183; CHECK-LABEL: @vpternlog_q_constv128_imm109(
3184; CHECK-NEXT:    ret <2 x i64> <i64 -3, i64 -8>
3185;
3186  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 7>, <2 x i64> <i64 8, i64 2>, <2 x i64> <i64 7, i64 2>, i32 109)
3187  ret <2 x i64> %r
3188}
3189
3190define <8 x i32> @vpternlog_d_constv256_imm110() {
3191; CHECK-LABEL: @vpternlog_d_constv256_imm110(
3192; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 5, i32 7, i32 0, i32 7, i32 1, i32 3, i32 3>
3193;
3194  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 0, i32 9, i32 1, i32 4, i32 5, i32 8, i32 6>, <8 x i32> <i32 7, i32 1, i32 4, i32 1, i32 5, i32 1, i32 1, i32 7>, <8 x i32> <i32 0, i32 4, i32 7, i32 1, i32 3, i32 0, i32 2, i32 4>, i32 110)
3195  ret <8 x i32> %r
3196}
3197
3198define <8 x i64> @vpternlog_q_constv512_imm111() {
3199; CHECK-LABEL: @vpternlog_q_constv512_imm111(
3200; CHECK-NEXT:    ret <8 x i64> <i64 -4, i64 -1, i64 -3, i64 -9, i64 -6, i64 -1, i64 -5, i64 -1>
3201;
3202  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 8, i64 6, i64 9, i64 7, i64 9, i64 4, i64 2>, <8 x i64> <i64 6, i64 9, i64 5, i64 0, i64 1, i64 9, i64 8, i64 0>, <8 x i64> <i64 6, i64 1, i64 8, i64 3, i64 3, i64 2, i64 8, i64 6>, i32 111)
3203  ret <8 x i64> %r
3204}
3205
3206define <4 x i32> @vpternlog_d_constv128_imm112() {
3207; CHECK-LABEL: @vpternlog_d_constv128_imm112(
3208; CHECK-NEXT:    ret <4 x i32> <i32 8, i32 8, i32 5, i32 1>
3209;
3210  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 8, i32 5, i32 1>, <4 x i32> <i32 7, i32 5, i32 6, i32 0>, <4 x i32> <i32 0, i32 4, i32 0, i32 0>, i32 112)
3211  ret <4 x i32> %r
3212}
3213
3214define <4 x i64> @vpternlog_q_constv256_imm113() {
3215; CHECK-LABEL: @vpternlog_q_constv256_imm113(
3216; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -1, i64 -7, i64 -2>
3217;
3218  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 6, i64 1, i64 6>, <4 x i64> <i64 7, i64 2, i64 0, i64 7>, <4 x i64> <i64 6, i64 4, i64 6, i64 0>, i32 113)
3219  ret <4 x i64> %r
3220}
3221
3222define <16 x i32> @vpternlog_d_constv512_imm114() {
3223; CHECK-LABEL: @vpternlog_d_constv512_imm114(
3224; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 9, i32 3, i32 9, i32 14, i32 1, i32 9, i32 4, i32 7, i32 6, i32 3, i32 3, i32 6, i32 13, i32 11, i32 4>
3225;
3226  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 9, i32 3, i32 9, i32 8, i32 2, i32 9, i32 4, i32 7, i32 2, i32 2, i32 5, i32 7, i32 5, i32 3, i32 6>, <16 x i32> <i32 0, i32 1, i32 9, i32 7, i32 9, i32 2, i32 3, i32 7, i32 0, i32 1, i32 4, i32 4, i32 9, i32 2, i32 2, i32 3>, <16 x i32> <i32 2, i32 0, i32 0, i32 4, i32 7, i32 3, i32 2, i32 1, i32 7, i32 7, i32 7, i32 7, i32 3, i32 8, i32 9, i32 3>, i32 114)
3227  ret <16 x i32> %r
3228}
3229
3230define <2 x i64> @vpternlog_q_constv128_imm115() {
3231; CHECK-LABEL: @vpternlog_q_constv128_imm115(
3232; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -4>
3233;
3234  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 0>, <2 x i64> <i64 4, i64 3>, <2 x i64> <i64 3, i64 7>, i32 115)
3235  ret <2 x i64> %r
3236}
3237
3238define <8 x i32> @vpternlog_d_constv256_imm116() {
3239; CHECK-LABEL: @vpternlog_d_constv256_imm116(
3240; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 13, i32 3, i32 2, i32 9, i32 9, i32 14, i32 13>
3241;
3242  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 9, i32 3, i32 2, i32 9, i32 0, i32 6, i32 5>, <8 x i32> <i32 1, i32 5, i32 8, i32 0, i32 6, i32 9, i32 8, i32 8>, <8 x i32> <i32 9, i32 8, i32 9, i32 1, i32 6, i32 0, i32 4, i32 7>, i32 116)
3243  ret <8 x i32> %r
3244}
3245
3246define <8 x i64> @vpternlog_q_constv512_imm117() {
3247; CHECK-LABEL: @vpternlog_q_constv512_imm117(
3248; CHECK-NEXT:    ret <8 x i64> <i64 -8, i64 -2, i64 -3, i64 -1, i64 -10, i64 -4, i64 -9, i64 -4>
3249;
3250  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 5, i64 9, i64 7, i64 2, i64 8, i64 7, i64 8>, <8 x i64> <i64 2, i64 1, i64 1, i64 2, i64 0, i64 5, i64 1, i64 9>, <8 x i64> <i64 7, i64 5, i64 2, i64 4, i64 9, i64 3, i64 8, i64 3>, i32 117)
3251  ret <8 x i64> %r
3252}
3253
3254define <4 x i32> @vpternlog_d_constv128_imm118() {
3255; CHECK-LABEL: @vpternlog_d_constv128_imm118(
3256; CHECK-NEXT:    ret <4 x i32> <i32 4, i32 6, i32 1, i32 14>
3257;
3258  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 5, i32 3, i32 0, i32 4>, <4 x i32> <i32 5, i32 1, i32 7, i32 2>, <4 x i32> <i32 1, i32 7, i32 6, i32 8>, i32 118)
3259  ret <4 x i32> %r
3260}
3261
3262define <4 x i64> @vpternlog_q_constv256_imm119() {
3263; CHECK-LABEL: @vpternlog_q_constv256_imm119(
3264; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -1, i64 -4, i64 -1>
3265;
3266  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 5, i64 6, i64 3>, <4 x i64> <i64 9, i64 9, i64 3, i64 0>, <4 x i64> <i64 2, i64 0, i64 3, i64 5>, i32 119)
3267  ret <4 x i64> %r
3268}
3269
3270define <16 x i32> @vpternlog_d_constv512_imm120() {
3271; CHECK-LABEL: @vpternlog_d_constv512_imm120(
3272; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 1, i32 9, i32 10, i32 0, i32 4, i32 8, i32 5, i32 1, i32 3, i32 5, i32 6, i32 7, i32 3, i32 7, i32 3>
3273;
3274  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 1, i32 9, i32 8, i32 0, i32 4, i32 8, i32 5, i32 0, i32 2, i32 5, i32 7, i32 2, i32 2, i32 3, i32 1>, <16 x i32> <i32 2, i32 5, i32 7, i32 2, i32 5, i32 0, i32 3, i32 0, i32 5, i32 1, i32 4, i32 1, i32 7, i32 3, i32 6, i32 6>, <16 x i32> <i32 4, i32 8, i32 0, i32 2, i32 8, i32 1, i32 4, i32 7, i32 1, i32 3, i32 0, i32 9, i32 5, i32 1, i32 5, i32 2>, i32 120)
3275  ret <16 x i32> %r
3276}
3277
3278define <2 x i64> @vpternlog_q_constv128_imm121() {
3279; CHECK-LABEL: @vpternlog_q_constv128_imm121(
3280; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -1>
3281;
3282  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 6>, <2 x i64> <i64 1, i64 0>, <2 x i64> <i64 1, i64 4>, i32 121)
3283  ret <2 x i64> %r
3284}
3285
3286define <8 x i32> @vpternlog_d_constv256_imm122() {
3287; CHECK-LABEL: @vpternlog_d_constv256_imm122(
3288; CHECK-NEXT:    ret <8 x i32> <i32 9, i32 15, i32 8, i32 7, i32 14, i32 9, i32 15, i32 14>
3289;
3290  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 7, i32 9, i32 1, i32 6, i32 9, i32 8, i32 7>, <8 x i32> <i32 0, i32 5, i32 1, i32 2, i32 5, i32 7, i32 7, i32 5>, <8 x i32> <i32 9, i32 8, i32 1, i32 7, i32 8, i32 0, i32 7, i32 9>, i32 122)
3291  ret <8 x i32> %r
3292}
3293
3294define <8 x i64> @vpternlog_q_constv512_imm123() {
3295; CHECK-LABEL: @vpternlog_q_constv512_imm123(
3296; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -2, i64 -1, i64 -1, i64 -1, i64 -10, i64 -9>
3297;
3298  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 5, i64 4, i64 4, i64 8, i64 2, i64 4, i64 0>, <8 x i64> <i64 8, i64 0, i64 1, i64 0, i64 0, i64 0, i64 9, i64 8>, <8 x i64> <i64 4, i64 0, i64 6, i64 2, i64 4, i64 2, i64 2, i64 0>, i32 123)
3299  ret <8 x i64> %r
3300}
3301
3302define <4 x i32> @vpternlog_d_constv128_imm124() {
3303; CHECK-LABEL: @vpternlog_d_constv128_imm124(
3304; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 3, i32 12, i32 6>
3305;
3306  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 2, i32 4, i32 4>, <4 x i32> <i32 3, i32 1, i32 8, i32 6>, <4 x i32> <i32 5, i32 6, i32 1, i32 1>, i32 124)
3307  ret <4 x i32> %r
3308}
3309
3310define <4 x i64> @vpternlog_q_constv256_imm125() {
3311; CHECK-LABEL: @vpternlog_q_constv256_imm125(
3312; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -1, i64 -9, i64 -2>
3313;
3314  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 7, i64 0, i64 1, i64 3>, <4 x i64> <i64 5, i64 3, i64 1, i64 1>, <4 x i64> <i64 1, i64 0, i64 8, i64 3>, i32 125)
3315  ret <4 x i64> %r
3316}
3317
3318define <16 x i32> @vpternlog_d_constv512_imm126() {
3319; CHECK-LABEL: @vpternlog_d_constv512_imm126(
3320; CHECK-NEXT:    ret <16 x i32> <i32 6, i32 4, i32 7, i32 15, i32 9, i32 3, i32 15, i32 7, i32 14, i32 13, i32 2, i32 4, i32 13, i32 15, i32 3, i32 3>
3321;
3322  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 2, i32 5, i32 6, i32 8, i32 3, i32 7, i32 2, i32 0, i32 4, i32 7, i32 5, i32 5, i32 9, i32 5, i32 0>, <16 x i32> <i32 1, i32 6, i32 4, i32 9, i32 9, i32 0, i32 0, i32 1, i32 8, i32 1, i32 5, i32 5, i32 1, i32 6, i32 7, i32 1>, <16 x i32> <i32 7, i32 6, i32 3, i32 8, i32 1, i32 2, i32 8, i32 7, i32 6, i32 8, i32 7, i32 1, i32 8, i32 9, i32 6, i32 2>, i32 126)
3323  ret <16 x i32> %r
3324}
3325
3326define <2 x i64> @vpternlog_q_constv128_imm127() {
3327; CHECK-LABEL: @vpternlog_q_constv128_imm127(
3328; CHECK-NEXT:    ret <2 x i64> splat (i64 -1)
3329;
3330  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 3, i64 0>, <2 x i64> <i64 1, i64 3>, <2 x i64> <i64 0, i64 7>, i32 127)
3331  ret <2 x i64> %r
3332}
3333
3334define <8 x i32> @vpternlog_d_constv256_imm128() {
3335; CHECK-LABEL: @vpternlog_d_constv256_imm128(
3336; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0>
3337;
3338  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 0, i32 5, i32 2, i32 7, i32 1, i32 0, i32 6>, <8 x i32> <i32 6, i32 7, i32 2, i32 1, i32 7, i32 0, i32 3, i32 8>, <8 x i32> <i32 8, i32 6, i32 2, i32 2, i32 9, i32 3, i32 1, i32 2>, i32 128)
3339  ret <8 x i32> %r
3340}
3341
3342define <8 x i64> @vpternlog_q_constv512_imm129() {
3343; CHECK-LABEL: @vpternlog_q_constv512_imm129(
3344; CHECK-NEXT:    ret <8 x i64> <i64 -8, i64 -3, i64 -6, i64 -16, i64 -6, i64 -7, i64 -4, i64 -8>
3345;
3346  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 0, i64 2, i64 2, i64 6, i64 2, i64 5, i64 2>, <8 x i64> <i64 5, i64 2, i64 2, i64 5, i64 3, i64 4, i64 4, i64 5>, <8 x i64> <i64 0, i64 2, i64 7, i64 9, i64 6, i64 0, i64 6, i64 4>, i32 129)
3347  ret <8 x i64> %r
3348}
3349
3350define <4 x i32> @vpternlog_d_constv128_imm130() {
3351; CHECK-LABEL: @vpternlog_d_constv128_imm130(
3352; CHECK-NEXT:    ret <4 x i32> <i32 4, i32 2, i32 2, i32 0>
3353;
3354  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 6, i32 4, i32 6>, <4 x i32> <i32 3, i32 3, i32 9, i32 5>, <4 x i32> <i32 6, i32 7, i32 6, i32 1>, i32 130)
3355  ret <4 x i32> %r
3356}
3357
3358define <4 x i64> @vpternlog_q_constv256_imm131() {
3359; CHECK-LABEL: @vpternlog_q_constv256_imm131(
3360; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -7, i64 -8, i64 -7>
3361;
3362  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 7, i64 5, i64 2>, <4 x i64> <i64 7, i64 1, i64 2, i64 4>, <4 x i64> <i64 2, i64 9, i64 9, i64 7>, i32 131)
3363  ret <4 x i64> %r
3364}
3365
3366define <16 x i32> @vpternlog_d_constv512_imm132() {
3367; CHECK-LABEL: @vpternlog_d_constv512_imm132(
3368; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 0, i32 0, i32 0, i32 6, i32 6, i32 0, i32 6, i32 1, i32 0, i32 0, i32 1, i32 6, i32 3, i32 1, i32 8>
3369;
3370  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 7, i32 3, i32 0, i32 5, i32 3, i32 9, i32 0, i32 0, i32 6, i32 6, i32 6, i32 1, i32 5, i32 6, i32 6>, <16 x i32> <i32 4, i32 4, i32 0, i32 0, i32 6, i32 6, i32 8, i32 6, i32 5, i32 2, i32 8, i32 7, i32 7, i32 3, i32 5, i32 8>, <16 x i32> <i32 4, i32 1, i32 0, i32 4, i32 5, i32 3, i32 6, i32 0, i32 4, i32 1, i32 9, i32 0, i32 8, i32 5, i32 2, i32 4>, i32 132)
3371  ret <16 x i32> %r
3372}
3373
3374define <2 x i64> @vpternlog_q_constv128_imm133() {
3375; CHECK-LABEL: @vpternlog_q_constv128_imm133(
3376; CHECK-NEXT:    ret <2 x i64> splat (i64 -14)
3377;
3378  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 8>, <2 x i64> <i64 2, i64 8>, <2 x i64> <i64 5, i64 5>, i32 133)
3379  ret <2 x i64> %r
3380}
3381
3382define <8 x i32> @vpternlog_d_constv256_imm134() {
3383; CHECK-LABEL: @vpternlog_d_constv256_imm134(
3384; CHECK-NEXT:    ret <8 x i32> <i32 12, i32 3, i32 8, i32 2, i32 0, i32 11, i32 8, i32 4>
3385;
3386  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 4, i32 7, i32 5, i32 2, i32 5, i32 4, i32 1>, <8 x i32> <i32 8, i32 0, i32 0, i32 2, i32 2, i32 7, i32 1, i32 6>, <8 x i32> <i32 5, i32 7, i32 9, i32 0, i32 0, i32 9, i32 9, i32 2>, i32 134)
3387  ret <8 x i32> %r
3388}
3389
3390define <8 x i64> @vpternlog_q_constv512_imm135() {
3391; CHECK-LABEL: @vpternlog_q_constv512_imm135(
3392; CHECK-NEXT:    ret <8 x i64> <i64 -6, i64 -11, i64 -3, i64 -4, i64 -6, i64 -5, i64 -5, i64 -5>
3393;
3394  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 8, i64 6, i64 7, i64 5, i64 4, i64 4, i64 7>, <8 x i64> <i64 5, i64 2, i64 4, i64 4, i64 0, i64 0, i64 4, i64 3>, <8 x i64> <i64 3, i64 7, i64 6, i64 7, i64 0, i64 9, i64 0, i64 3>, i32 135)
3395  ret <8 x i64> %r
3396}
3397
3398define <4 x i32> @vpternlog_d_constv128_imm136() {
3399; CHECK-LABEL: @vpternlog_d_constv128_imm136(
3400; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 4, i32 0, i32 0>
3401;
3402  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 9, i32 2>, <4 x i32> <i32 2, i32 4, i32 1, i32 1>, <4 x i32> <i32 4, i32 6, i32 4, i32 6>, i32 136)
3403  ret <4 x i32> %r
3404}
3405
3406define <4 x i64> @vpternlog_q_constv256_imm137() {
3407; CHECK-LABEL: @vpternlog_q_constv256_imm137(
3408; CHECK-NEXT:    ret <4 x i64> <i64 -3, i64 -1, i64 -6, i64 -2>
3409;
3410  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 1, i64 1, i64 4>, <4 x i64> <i64 8, i64 3, i64 0, i64 4>, <4 x i64> <i64 8, i64 3, i64 5, i64 5>, i32 137)
3411  ret <4 x i64> %r
3412}
3413
3414define <16 x i32> @vpternlog_d_constv512_imm138() {
3415; CHECK-LABEL: @vpternlog_d_constv512_imm138(
3416; CHECK-NEXT:    ret <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 1, i32 2, i32 0, i32 4, i32 6, i32 8, i32 3, i32 2, i32 1, i32 7, i32 5, i32 5>
3417;
3418  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 5, i32 8, i32 5, i32 5, i32 9, i32 5, i32 3, i32 0, i32 8, i32 9, i32 4, i32 9, i32 8, i32 5, i32 0, i32 3>, <16 x i32> <i32 0, i32 2, i32 0, i32 8, i32 7, i32 4, i32 5, i32 5, i32 8, i32 8, i32 6, i32 4, i32 0, i32 7, i32 1, i32 1>, <16 x i32> <i32 6, i32 2, i32 6, i32 2, i32 1, i32 2, i32 2, i32 4, i32 6, i32 8, i32 3, i32 2, i32 1, i32 7, i32 5, i32 7>, i32 138)
3419  ret <16 x i32> %r
3420}
3421
3422define <2 x i64> @vpternlog_q_constv128_imm139() {
3423; CHECK-LABEL: @vpternlog_q_constv128_imm139(
3424; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -6>
3425;
3426  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 4>, <2 x i64> <i64 1, i64 1>, <2 x i64> <i64 7, i64 6>, i32 139)
3427  ret <2 x i64> %r
3428}
3429
3430define <8 x i32> @vpternlog_d_constv256_imm140() {
3431; CHECK-LABEL: @vpternlog_d_constv256_imm140(
3432; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 7, i32 8, i32 4, i32 1, i32 5, i32 8, i32 2>
3433;
3434  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 5, i32 7, i32 7, i32 2, i32 1, i32 1, i32 4>, <8 x i32> <i32 6, i32 7, i32 9, i32 4, i32 3, i32 5, i32 8, i32 6>, <8 x i32> <i32 7, i32 7, i32 8, i32 7, i32 4, i32 7, i32 2, i32 1>, i32 140)
3435  ret <8 x i32> %r
3436}
3437
3438define <8 x i64> @vpternlog_q_constv512_imm141() {
3439; CHECK-LABEL: @vpternlog_q_constv512_imm141(
3440; CHECK-NEXT:    ret <8 x i64> <i64 -6, i64 -4, i64 -15, i64 -8, i64 -5, i64 -9, i64 -1, i64 -7>
3441;
3442  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 5, i64 7, i64 6, i64 4, i64 9, i64 5, i64 5>, <8 x i64> <i64 0, i64 5, i64 1, i64 2, i64 3, i64 3, i64 7, i64 1>, <8 x i64> <i64 4, i64 6, i64 9, i64 5, i64 5, i64 3, i64 5, i64 3>, i32 141)
3443  ret <8 x i64> %r
3444}
3445
3446define <4 x i32> @vpternlog_d_constv128_imm142() {
3447; CHECK-LABEL: @vpternlog_d_constv128_imm142(
3448; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 4, i32 5, i32 0>
3449;
3450  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 1, i32 9, i32 7>, <4 x i32> <i32 7, i32 4, i32 5, i32 2>, <4 x i32> <i32 2, i32 5, i32 1, i32 0>, i32 142)
3451  ret <4 x i32> %r
3452}
3453
3454define <4 x i64> @vpternlog_q_constv256_imm143() {
3455; CHECK-LABEL: @vpternlog_q_constv256_imm143(
3456; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -9, i64 -9, i64 -4>
3457;
3458  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 8, i64 8, i64 3>, <4 x i64> <i64 2, i64 5, i64 8, i64 0>, <4 x i64> <i64 2, i64 3, i64 0, i64 9>, i32 143)
3459  ret <4 x i64> %r
3460}
3461
3462define <16 x i32> @vpternlog_d_constv512_imm144() {
3463; CHECK-LABEL: @vpternlog_d_constv512_imm144(
3464; CHECK-NEXT:    ret <16 x i32> <i32 2, i32 0, i32 2, i32 2, i32 0, i32 0, i32 0, i32 6, i32 2, i32 0, i32 6, i32 0, i32 0, i32 3, i32 4, i32 0>
3465;
3466  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 6, i32 9, i32 2, i32 2, i32 9, i32 5, i32 0, i32 7, i32 2, i32 0, i32 6, i32 7, i32 3, i32 3, i32 5, i32 6>, <16 x i32> <i32 8, i32 8, i32 1, i32 5, i32 3, i32 5, i32 9, i32 6, i32 8, i32 3, i32 6, i32 6, i32 7, i32 4, i32 9, i32 5>, <16 x i32> <i32 4, i32 7, i32 1, i32 5, i32 8, i32 8, i32 2, i32 7, i32 8, i32 0, i32 7, i32 9, i32 4, i32 0, i32 0, i32 2>, i32 144)
3467  ret <16 x i32> %r
3468}
3469
3470define <2 x i64> @vpternlog_q_constv128_imm145() {
3471; CHECK-LABEL: @vpternlog_q_constv128_imm145(
3472; CHECK-NEXT:    ret <2 x i64> <i64 -15, i64 -4>
3473;
3474  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 1, i64 2>, <2 x i64> <i64 9, i64 3>, <2 x i64> <i64 7, i64 0>, i32 145)
3475  ret <2 x i64> %r
3476}
3477
3478define <8 x i32> @vpternlog_d_constv256_imm146() {
3479; CHECK-LABEL: @vpternlog_d_constv256_imm146(
3480; CHECK-NEXT:    ret <8 x i32> <i32 2, i32 10, i32 2, i32 3, i32 4, i32 8, i32 10, i32 0>
3481;
3482  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 8, i32 4, i32 3, i32 4, i32 9, i32 8, i32 3>, <8 x i32> <i32 8, i32 5, i32 5, i32 1, i32 2, i32 5, i32 5, i32 7>, <8 x i32> <i32 6, i32 6, i32 3, i32 1, i32 0, i32 0, i32 3, i32 4>, i32 146)
3483  ret <8 x i32> %r
3484}
3485
3486define <8 x i64> @vpternlog_q_constv512_imm147() {
3487; CHECK-LABEL: @vpternlog_q_constv512_imm147(
3488; CHECK-NEXT:    ret <8 x i64> <i64 -4, i64 -2, i64 -3, i64 -8, i64 -10, i64 -5, i64 -10, i64 -1>
3489;
3490  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 1, i64 2, i64 1, i64 8, i64 1, i64 4, i64 6>, <8 x i64> <i64 3, i64 1, i64 0, i64 6, i64 1, i64 5, i64 9, i64 0>, <8 x i64> <i64 6, i64 6, i64 7, i64 5, i64 8, i64 3, i64 0, i64 0>, i32 147)
3491  ret <8 x i64> %r
3492}
3493
3494define <4 x i32> @vpternlog_d_constv128_imm148() {
3495; CHECK-LABEL: @vpternlog_d_constv128_imm148(
3496; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 7, i32 8, i32 5>
3497;
3498  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 3, i32 1, i32 7>, <4 x i32> <i32 2, i32 4, i32 9, i32 0>, <4 x i32> <i32 7, i32 0, i32 6, i32 2>, i32 148)
3499  ret <4 x i32> %r
3500}
3501
3502define <4 x i64> @vpternlog_q_constv256_imm149() {
3503; CHECK-LABEL: @vpternlog_q_constv256_imm149(
3504; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -10, i64 -1, i64 -5>
3505;
3506  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 8, i64 6, i64 1>, <4 x i64> <i64 8, i64 8, i64 3, i64 9>, <4 x i64> <i64 0, i64 1, i64 2, i64 5>, i32 149)
3507  ret <4 x i64> %r
3508}
3509
3510define <16 x i32> @vpternlog_d_constv512_imm150() {
3511; CHECK-LABEL: @vpternlog_d_constv512_imm150(
3512; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 5, i32 2, i32 11, i32 2, i32 0, i32 8, i32 1, i32 2, i32 7, i32 0, i32 3, i32 5, i32 14, i32 6, i32 9>
3513;
3514  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 5, i32 7, i32 7, i32 0, i32 7, i32 0, i32 8, i32 6, i32 1, i32 6, i32 6, i32 7, i32 1, i32 0, i32 9>, <16 x i32> <i32 2, i32 8, i32 0, i32 8, i32 3, i32 0, i32 0, i32 0, i32 0, i32 6, i32 5, i32 6, i32 1, i32 9, i32 6, i32 0>, <16 x i32> <i32 2, i32 8, i32 5, i32 4, i32 1, i32 7, i32 8, i32 9, i32 4, i32 0, i32 3, i32 3, i32 3, i32 6, i32 0, i32 0>, i32 150)
3515  ret <16 x i32> %r
3516}
3517
3518define <2 x i64> @vpternlog_q_constv128_imm151() {
3519; CHECK-LABEL: @vpternlog_q_constv128_imm151(
3520; CHECK-NEXT:    ret <2 x i64> <i64 -3, i64 -1>
3521;
3522  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 0>, <2 x i64> <i64 3, i64 0>, <2 x i64> <i64 2, i64 2>, i32 151)
3523  ret <2 x i64> %r
3524}
3525
3526define <8 x i32> @vpternlog_d_constv256_imm152() {
3527; CHECK-LABEL: @vpternlog_d_constv256_imm152(
3528; CHECK-NEXT:    ret <8 x i32> <i32 4, i32 3, i32 12, i32 2, i32 8, i32 4, i32 3, i32 1>
3529;
3530  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 7, i32 8, i32 6, i32 8, i32 4, i32 1, i32 8>, <8 x i32> <i32 5, i32 9, i32 5, i32 6, i32 3, i32 8, i32 7, i32 3>, <8 x i32> <i32 6, i32 5, i32 6, i32 2, i32 0, i32 0, i32 3, i32 9>, i32 152)
3531  ret <8 x i32> %r
3532}
3533
3534define <8 x i64> @vpternlog_q_constv512_imm153() {
3535; CHECK-LABEL: @vpternlog_q_constv512_imm153(
3536; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -4, i64 -2, i64 -6, i64 -12, i64 -15, i64 -6, i64 -6>
3537;
3538  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 4, i64 8, i64 4, i64 0, i64 0, i64 1, i64 4>, <8 x i64> <i64 3, i64 3, i64 6, i64 5, i64 3, i64 9, i64 3, i64 2>, <8 x i64> <i64 2, i64 0, i64 7, i64 0, i64 8, i64 7, i64 6, i64 7>, i32 153)
3539  ret <8 x i64> %r
3540}
3541
3542define <4 x i32> @vpternlog_d_constv128_imm154() {
3543; CHECK-LABEL: @vpternlog_d_constv128_imm154(
3544; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 9, i32 3, i32 6>
3545;
3546  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 0, i32 2, i32 8>, <4 x i32> <i32 9, i32 6, i32 3, i32 9>, <4 x i32> <i32 0, i32 9, i32 3, i32 6>, i32 154)
3547  ret <4 x i32> %r
3548}
3549
3550define <4 x i64> @vpternlog_q_constv256_imm155() {
3551; CHECK-LABEL: @vpternlog_q_constv256_imm155(
3552; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -2, i64 -4, i64 -5>
3553;
3554  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 9, i64 1, i64 9>, <4 x i64> <i64 9, i64 5, i64 3, i64 6>, <4 x i64> <i64 1, i64 6, i64 8, i64 2>, i32 155)
3555  ret <4 x i64> %r
3556}
3557
3558define <16 x i32> @vpternlog_d_constv512_imm156() {
3559; CHECK-LABEL: @vpternlog_d_constv512_imm156(
3560; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 1, i32 8, i32 9, i32 1, i32 5, i32 9, i32 3, i32 12, i32 1, i32 1, i32 5, i32 14, i32 9, i32 8, i32 9>
3561;
3562  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 1, i32 1, i32 0, i32 1, i32 4, i32 4, i32 9, i32 7, i32 7, i32 7, i32 8, i32 8, i32 1, i32 9>, <16 x i32> <i32 9, i32 7, i32 8, i32 8, i32 1, i32 5, i32 9, i32 3, i32 5, i32 7, i32 6, i32 7, i32 6, i32 9, i32 8, i32 0>, <16 x i32> <i32 3, i32 0, i32 1, i32 0, i32 3, i32 1, i32 7, i32 6, i32 6, i32 9, i32 8, i32 5, i32 4, i32 8, i32 7, i32 2>, i32 156)
3563  ret <16 x i32> %r
3564}
3565
3566define <2 x i64> @vpternlog_q_constv128_imm157() {
3567; CHECK-LABEL: @vpternlog_q_constv128_imm157(
3568; CHECK-NEXT:    ret <2 x i64> splat (i64 -1)
3569;
3570  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 1>, <2 x i64> <i64 3, i64 7>, <2 x i64> <i64 3, i64 3>, i32 157)
3571  ret <2 x i64> %r
3572}
3573
3574define <8 x i32> @vpternlog_d_constv256_imm158() {
3575; CHECK-LABEL: @vpternlog_d_constv256_imm158(
3576; CHECK-NEXT:    ret <8 x i32> <i32 1, i32 2, i32 7, i32 5, i32 13, i32 10, i32 15, i32 6>
3577;
3578  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 5, i32 6, i32 3, i32 7, i32 7, i32 5, i32 2>, <8 x i32> <i32 3, i32 6, i32 4, i32 5, i32 8, i32 4, i32 3, i32 6>, <8 x i32> <i32 5, i32 1, i32 5, i32 7, i32 2, i32 9, i32 9, i32 6>, i32 158)
3579  ret <8 x i32> %r
3580}
3581
3582define <8 x i64> @vpternlog_q_constv512_imm159() {
3583; CHECK-LABEL: @vpternlog_q_constv512_imm159(
3584; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -5, i64 -3, i64 -1, i64 -8, i64 -2, i64 -8, i64 -1>
3585;
3586  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 7, i64 2, i64 7, i64 7, i64 7, i64 1>, <8 x i64> <i64 3, i64 7, i64 3, i64 4, i64 6, i64 1, i64 9, i64 8>, <8 x i64> <i64 3, i64 3, i64 9, i64 9, i64 9, i64 0, i64 6, i64 8>, i32 159)
3587  ret <8 x i64> %r
3588}
3589
3590define <4 x i32> @vpternlog_d_constv128_imm160() {
3591; CHECK-LABEL: @vpternlog_d_constv128_imm160(
3592; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 1, i32 0, i32 4>
3593;
3594  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 1, i32 0, i32 4>, <4 x i32> <i32 7, i32 0, i32 0, i32 1>, <4 x i32> <i32 7, i32 3, i32 1, i32 5>, i32 160)
3595  ret <4 x i32> %r
3596}
3597
3598define <4 x i64> @vpternlog_q_constv256_imm161() {
3599; CHECK-LABEL: @vpternlog_q_constv256_imm161(
3600; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -4, i64 -6, i64 -6>
3601;
3602  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 1, i64 4, i64 2, i64 3>, <4 x i64> <i64 0, i64 2, i64 1, i64 2>, <4 x i64> <i64 6, i64 7, i64 7, i64 6>, i32 161)
3603  ret <4 x i64> %r
3604}
3605
3606define <16 x i32> @vpternlog_d_constv512_imm162() {
3607; CHECK-LABEL: @vpternlog_d_constv512_imm162(
3608; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 4, i32 6, i32 4, i32 0, i32 9, i32 2, i32 4, i32 1, i32 0, i32 9, i32 3, i32 4, i32 0, i32 7, i32 0>
3609;
3610  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 5, i32 0, i32 5, i32 8, i32 5, i32 3, i32 6, i32 6, i32 9, i32 8, i32 7, i32 1, i32 2, i32 8, i32 3>, <16 x i32> <i32 2, i32 5, i32 9, i32 1, i32 5, i32 7, i32 3, i32 5, i32 8, i32 3, i32 8, i32 1, i32 3, i32 5, i32 0, i32 8>, <16 x i32> <i32 8, i32 4, i32 7, i32 4, i32 5, i32 9, i32 2, i32 5, i32 9, i32 2, i32 9, i32 3, i32 4, i32 5, i32 7, i32 0>, i32 162)
3611  ret <16 x i32> %r
3612}
3613
3614define <2 x i64> @vpternlog_q_constv128_imm163() {
3615; CHECK-LABEL: @vpternlog_q_constv128_imm163(
3616; CHECK-NEXT:    ret <2 x i64> <i64 -6, i64 -3>
3617;
3618  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 3>, <2 x i64> <i64 7, i64 2>, <2 x i64> <i64 7, i64 5>, i32 163)
3619  ret <2 x i64> %r
3620}
3621
3622define <8 x i32> @vpternlog_d_constv256_imm164() {
3623; CHECK-LABEL: @vpternlog_d_constv256_imm164(
3624; CHECK-NEXT:    ret <8 x i32> <i32 5, i32 1, i32 8, i32 0, i32 7, i32 0, i32 6, i32 2>
3625;
3626  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 1, i32 8, i32 9, i32 6, i32 4, i32 6, i32 2>, <8 x i32> <i32 2, i32 8, i32 0, i32 9, i32 1, i32 0, i32 6, i32 6>, <8 x i32> <i32 5, i32 9, i32 8, i32 2, i32 6, i32 0, i32 6, i32 6>, i32 164)
3627  ret <8 x i32> %r
3628}
3629
3630define <8 x i64> @vpternlog_q_constv512_imm165() {
3631; CHECK-LABEL: @vpternlog_q_constv512_imm165(
3632; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -4, i64 -6, i64 -13, i64 -7, i64 -4, i64 -5, i64 -5>
3633;
3634  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 6, i64 4, i64 5, i64 0, i64 3, i64 5, i64 6>, <8 x i64> <i64 6, i64 7, i64 2, i64 8, i64 6, i64 2, i64 5, i64 8>, <8 x i64> <i64 6, i64 5, i64 1, i64 9, i64 6, i64 0, i64 1, i64 2>, i32 165)
3635  ret <8 x i64> %r
3636}
3637
3638define <4 x i32> @vpternlog_d_constv128_imm166() {
3639; CHECK-LABEL: @vpternlog_d_constv128_imm166(
3640; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 5, i32 2, i32 5>
3641;
3642  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 0, i32 4, i32 6>, <4 x i32> <i32 5, i32 0, i32 7, i32 7>, <4 x i32> <i32 6, i32 5, i32 1, i32 4>, i32 166)
3643  ret <4 x i32> %r
3644}
3645
3646define <4 x i64> @vpternlog_q_constv256_imm167() {
3647; CHECK-LABEL: @vpternlog_q_constv256_imm167(
3648; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -6, i64 -7, i64 -3>
3649;
3650  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 1, i64 6, i64 2>, <4 x i64> <i64 0, i64 4, i64 0, i64 2>, <4 x i64> <i64 6, i64 6, i64 1, i64 1>, i32 167)
3651  ret <4 x i64> %r
3652}
3653
3654define <16 x i32> @vpternlog_d_constv512_imm168() {
3655; CHECK-LABEL: @vpternlog_d_constv512_imm168(
3656; CHECK-NEXT:    ret <16 x i32> <i32 0, i32 0, i32 8, i32 1, i32 6, i32 0, i32 0, i32 6, i32 0, i32 1, i32 1, i32 0, i32 2, i32 1, i32 0, i32 5>
3657;
3658  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 8, i32 9, i32 5, i32 6, i32 0, i32 4, i32 6, i32 6, i32 3, i32 3, i32 5, i32 7, i32 4, i32 4, i32 7>, <16 x i32> <i32 9, i32 8, i32 0, i32 1, i32 6, i32 9, i32 4, i32 8, i32 4, i32 5, i32 0, i32 7, i32 3, i32 9, i32 2, i32 4>, <16 x i32> <i32 2, i32 4, i32 8, i32 3, i32 6, i32 0, i32 3, i32 6, i32 1, i32 9, i32 1, i32 8, i32 2, i32 1, i32 0, i32 5>, i32 168)
3659  ret <16 x i32> %r
3660}
3661
3662define <2 x i64> @vpternlog_q_constv128_imm169() {
3663; CHECK-LABEL: @vpternlog_q_constv128_imm169(
3664; CHECK-NEXT:    ret <2 x i64> <i64 -5, i64 -1>
3665;
3666  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 7>, <2 x i64> <i64 5, i64 7>, <2 x i64> <i64 3, i64 7>, i32 169)
3667  ret <2 x i64> %r
3668}
3669
3670define <8 x i32> @vpternlog_d_constv256_imm170() {
3671; CHECK-LABEL: @vpternlog_d_constv256_imm170(
3672; CHECK-NEXT:    ret <8 x i32> <i32 5, i32 4, i32 1, i32 5, i32 6, i32 6, i32 5, i32 2>
3673;
3674  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 5, i32 8, i32 4, i32 3, i32 2, i32 4, i32 0>, <8 x i32> <i32 9, i32 0, i32 2, i32 6, i32 5, i32 8, i32 5, i32 3>, <8 x i32> <i32 5, i32 4, i32 1, i32 5, i32 6, i32 6, i32 5, i32 2>, i32 170)
3675  ret <8 x i32> %r
3676}
3677
3678define <8 x i64> @vpternlog_q_constv512_imm171() {
3679; CHECK-LABEL: @vpternlog_q_constv512_imm171(
3680; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -9, i64 -1, i64 -1, i64 -3, i64 -6, i64 -2, i64 -6>
3681;
3682  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 8, i64 5, i64 0, i64 6, i64 5, i64 6, i64 5>, <8 x i64> <i64 9, i64 4, i64 1, i64 0, i64 6, i64 5, i64 3, i64 9>, <8 x i64> <i64 9, i64 6, i64 5, i64 2, i64 4, i64 8, i64 6, i64 8>, i32 171)
3683  ret <8 x i64> %r
3684}
3685
3686define <4 x i32> @vpternlog_d_constv128_imm172() {
3687; CHECK-LABEL: @vpternlog_d_constv128_imm172(
3688; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 2, i32 11, i32 13>
3689;
3690  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 6, i32 3, i32 7>, <4 x i32> <i32 4, i32 4, i32 9, i32 8>, <4 x i32> <i32 3, i32 3, i32 3, i32 5>, i32 172)
3691  ret <4 x i32> %r
3692}
3693
3694define <4 x i64> @vpternlog_q_constv256_imm173() {
3695; CHECK-LABEL: @vpternlog_q_constv256_imm173(
3696; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -10, i64 -4, i64 -11>
3697;
3698  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 1, i64 1, i64 3>, <4 x i64> <i64 5, i64 2, i64 0, i64 4>, <4 x i64> <i64 0, i64 8, i64 2, i64 9>, i32 173)
3699  ret <4 x i64> %r
3700}
3701
3702define <16 x i32> @vpternlog_d_constv512_imm174() {
3703; CHECK-LABEL: @vpternlog_d_constv512_imm174(
3704; CHECK-NEXT:    ret <16 x i32> <i32 3, i32 9, i32 6, i32 5, i32 6, i32 13, i32 11, i32 4, i32 9, i32 2, i32 9, i32 4, i32 7, i32 1, i32 3, i32 8>
3705;
3706  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 9, i32 6, i32 5, i32 9, i32 4, i32 3, i32 6, i32 5, i32 3, i32 7, i32 8, i32 7, i32 7, i32 5>, <16 x i32> <i32 0, i32 5, i32 7, i32 6, i32 4, i32 4, i32 3, i32 7, i32 0, i32 2, i32 9, i32 1, i32 7, i32 5, i32 4, i32 8>, <16 x i32> <i32 3, i32 9, i32 6, i32 5, i32 6, i32 9, i32 9, i32 4, i32 9, i32 0, i32 9, i32 4, i32 5, i32 1, i32 3, i32 0>, i32 174)
3707  ret <16 x i32> %r
3708}
3709
3710define <2 x i64> @vpternlog_q_constv128_imm175() {
3711; CHECK-LABEL: @vpternlog_q_constv128_imm175(
3712; CHECK-NEXT:    ret <2 x i64> <i64 -7, i64 -5>
3713;
3714  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 6, i64 6>, <2 x i64> <i64 2, i64 1>, <2 x i64> <i64 8, i64 3>, i32 175)
3715  ret <2 x i64> %r
3716}
3717
3718define <8 x i32> @vpternlog_d_constv256_imm176() {
3719; CHECK-LABEL: @vpternlog_d_constv256_imm176(
3720; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 0, i32 6, i32 3, i32 1, i32 4, i32 4, i32 1>
3721;
3722  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 0, i32 7, i32 3, i32 1, i32 4, i32 4, i32 3>, <8 x i32> <i32 6, i32 4, i32 1, i32 4, i32 8, i32 1, i32 8, i32 3>, <8 x i32> <i32 0, i32 1, i32 0, i32 7, i32 8, i32 5, i32 0, i32 1>, i32 176)
3723  ret <8 x i32> %r
3724}
3725
3726define <8 x i64> @vpternlog_q_constv512_imm177() {
3727; CHECK-LABEL: @vpternlog_q_constv512_imm177(
3728; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -11, i64 -12, i64 -2, i64 -6, i64 -4, i64 -8, i64 -9>
3729;
3730  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 0, i64 7, i64 8, i64 4, i64 8, i64 7>, <8 x i64> <i64 1, i64 9, i64 9, i64 1, i64 4, i64 3, i64 5, i64 0>, <8 x i64> <i64 8, i64 7, i64 2, i64 2, i64 5, i64 2, i64 7, i64 9>, i32 177)
3731  ret <8 x i64> %r
3732}
3733
3734define <4 x i32> @vpternlog_d_constv128_imm178() {
3735; CHECK-LABEL: @vpternlog_d_constv128_imm178(
3736; CHECK-NEXT:    ret <4 x i32> <i32 15, i32 9, i32 2, i32 4>
3737;
3738  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 9, i32 2, i32 1>, <4 x i32> <i32 1, i32 1, i32 5, i32 3>, <4 x i32> <i32 9, i32 1, i32 5, i32 6>, i32 178)
3739  ret <4 x i32> %r
3740}
3741
3742define <4 x i64> @vpternlog_q_constv256_imm179() {
3743; CHECK-LABEL: @vpternlog_q_constv256_imm179(
3744; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -1, i64 -9, i64 -2>
3745;
3746  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 9, i64 9, i64 4>, <4 x i64> <i64 6, i64 8, i64 9, i64 1>, <4 x i64> <i64 1, i64 9, i64 5, i64 8>, i32 179)
3747  ret <4 x i64> %r
3748}
3749
3750define <16 x i32> @vpternlog_d_constv512_imm180() {
3751; CHECK-LABEL: @vpternlog_d_constv512_imm180(
3752; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 8, i32 7, i32 10, i32 0, i32 5, i32 2, i32 3, i32 4, i32 8, i32 12, i32 9, i32 9, i32 8, i32 6, i32 2>
3753;
3754  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 9, i32 7, i32 2, i32 6, i32 5, i32 2, i32 2, i32 5, i32 8, i32 4, i32 8, i32 8, i32 0, i32 7, i32 2>, <16 x i32> <i32 7, i32 9, i32 6, i32 8, i32 6, i32 0, i32 6, i32 5, i32 1, i32 0, i32 9, i32 1, i32 7, i32 8, i32 7, i32 1>, <16 x i32> <i32 8, i32 8, i32 7, i32 0, i32 0, i32 9, i32 6, i32 4, i32 4, i32 6, i32 7, i32 4, i32 6, i32 0, i32 6, i32 7>, i32 180)
3755  ret <16 x i32> %r
3756}
3757
3758define <2 x i64> @vpternlog_q_constv128_imm181() {
3759; CHECK-LABEL: @vpternlog_q_constv128_imm181(
3760; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -12>
3761;
3762  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 2>, <2 x i64> <i64 4, i64 3>, <2 x i64> <i64 1, i64 9>, i32 181)
3763  ret <2 x i64> %r
3764}
3765
3766define <8 x i32> @vpternlog_d_constv256_imm182() {
3767; CHECK-LABEL: @vpternlog_d_constv256_imm182(
3768; CHECK-NEXT:    ret <8 x i32> <i32 13, i32 9, i32 12, i32 10, i32 5, i32 13, i32 6, i32 14>
3769;
3770  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 3, i32 8, i32 9, i32 0, i32 5, i32 5, i32 6>, <8 x i32> <i32 1, i32 2, i32 7, i32 3, i32 1, i32 1, i32 7, i32 8>, <8 x i32> <i32 8, i32 8, i32 3, i32 8, i32 4, i32 9, i32 4, i32 6>, i32 182)
3771  ret <8 x i32> %r
3772}
3773
3774define <8 x i64> @vpternlog_q_constv512_imm183() {
3775; CHECK-LABEL: @vpternlog_q_constv512_imm183(
3776; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -4, i64 -2, i64 -4, i64 -4, i64 -1, i64 -1, i64 -5>
3777;
3778  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 2, i64 5, i64 2, i64 5, i64 8, i64 0, i64 7>, <8 x i64> <i64 9, i64 3, i64 3, i64 7, i64 3, i64 3, i64 1, i64 5>, <8 x i64> <i64 2, i64 1, i64 0, i64 9, i64 6, i64 0, i64 6, i64 9>, i32 183)
3779  ret <8 x i64> %r
3780}
3781
3782define <4 x i32> @vpternlog_d_constv128_imm184() {
3783; CHECK-LABEL: @vpternlog_d_constv128_imm184(
3784; CHECK-NEXT:    ret <4 x i32> <i32 5, i32 5, i32 0, i32 0>
3785;
3786  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 2, i32 8, i32 2>, <4 x i32> <i32 6, i32 7, i32 8, i32 6>, <4 x i32> <i32 4, i32 5, i32 0, i32 1>, i32 184)
3787  ret <4 x i32> %r
3788}
3789
3790define <4 x i64> @vpternlog_q_constv256_imm185() {
3791; CHECK-LABEL: @vpternlog_q_constv256_imm185(
3792; CHECK-NEXT:    ret <4 x i64> <i64 -15, i64 -10, i64 -1, i64 -3>
3793;
3794  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 3, i64 7, i64 0>, <4 x i64> <i64 9, i64 1, i64 2, i64 1>, <4 x i64> <i64 7, i64 8, i64 6, i64 3>, i32 185)
3795  ret <4 x i64> %r
3796}
3797
3798define <16 x i32> @vpternlog_d_constv512_imm186() {
3799; CHECK-LABEL: @vpternlog_d_constv512_imm186(
3800; CHECK-NEXT:    ret <16 x i32> <i32 8, i32 7, i32 5, i32 2, i32 9, i32 4, i32 6, i32 2, i32 3, i32 0, i32 3, i32 9, i32 7, i32 7, i32 5, i32 9>
3801;
3802  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 6, i32 7, i32 2, i32 8, i32 0, i32 6, i32 0, i32 3, i32 4, i32 3, i32 9, i32 7, i32 2, i32 5, i32 0>, <16 x i32> <i32 5, i32 0, i32 2, i32 3, i32 2, i32 7, i32 8, i32 6, i32 9, i32 7, i32 5, i32 0, i32 9, i32 4, i32 7, i32 7>, <16 x i32> <i32 8, i32 7, i32 0, i32 2, i32 9, i32 4, i32 4, i32 2, i32 3, i32 0, i32 1, i32 8, i32 1, i32 7, i32 5, i32 9>, i32 186)
3803  ret <16 x i32> %r
3804}
3805
3806define <2 x i64> @vpternlog_q_constv128_imm187() {
3807; CHECK-LABEL: @vpternlog_q_constv128_imm187(
3808; CHECK-NEXT:    ret <2 x i64> <i64 -2, i64 -4>
3809;
3810  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 0>, <2 x i64> <i64 1, i64 3>, <2 x i64> <i64 2, i64 4>, i32 187)
3811  ret <2 x i64> %r
3812}
3813
3814define <8 x i32> @vpternlog_d_constv256_imm188() {
3815; CHECK-LABEL: @vpternlog_d_constv256_imm188(
3816; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 6, i32 7, i32 7, i32 1, i32 5, i32 6, i32 11>
3817;
3818  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 2, i32 7, i32 1, i32 4, i32 3, i32 7, i32 9>, <8 x i32> <i32 7, i32 6, i32 4, i32 7, i32 5, i32 6, i32 1, i32 3>, <8 x i32> <i32 8, i32 2, i32 6, i32 5, i32 2, i32 8, i32 0, i32 9>, i32 188)
3819  ret <8 x i32> %r
3820}
3821
3822define <8 x i64> @vpternlog_q_constv512_imm189() {
3823; CHECK-LABEL: @vpternlog_q_constv512_imm189(
3824; CHECK-NEXT:    ret <8 x i64> <i64 -9, i64 -2, i64 -2, i64 -1, i64 -1, i64 -3, i64 -2, i64 -2>
3825;
3826  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 0, i64 4, i64 7, i64 6, i64 1, i64 8, i64 9, i64 0>, <8 x i64> <i64 7, i64 6, i64 9, i64 7, i64 5, i64 4, i64 5, i64 6>, <8 x i64> <i64 9, i64 7, i64 4, i64 7, i64 1, i64 6, i64 8, i64 1>, i32 189)
3827  ret <8 x i64> %r
3828}
3829
3830define <4 x i32> @vpternlog_d_constv128_imm190() {
3831; CHECK-LABEL: @vpternlog_d_constv128_imm190(
3832; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 8, i32 13, i32 7>
3833;
3834  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 4, i32 9, i32 9, i32 3>, <4 x i32> <i32 2, i32 1, i32 5, i32 4>, <4 x i32> <i32 5, i32 0, i32 5, i32 6>, i32 190)
3835  ret <4 x i32> %r
3836}
3837
3838define <4 x i64> @vpternlog_q_constv256_imm191() {
3839; CHECK-LABEL: @vpternlog_q_constv256_imm191(
3840; CHECK-NEXT:    ret <4 x i64> splat (i64 -1)
3841;
3842  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 0, i64 6, i64 0>, <4 x i64> <i64 9, i64 8, i64 4, i64 0>, <4 x i64> <i64 3, i64 9, i64 7, i64 2>, i32 191)
3843  ret <4 x i64> %r
3844}
3845
3846define <16 x i32> @vpternlog_d_constv512_imm192() {
3847; CHECK-LABEL: @vpternlog_d_constv512_imm192(
3848; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 2, i32 2, i32 0, i32 4, i32 5, i32 0, i32 8, i32 1, i32 0, i32 4, i32 0, i32 0, i32 0, i32 4, i32 0>
3849;
3850  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 2, i32 2, i32 0, i32 4, i32 7, i32 4, i32 8, i32 5, i32 1, i32 4, i32 2, i32 0, i32 9, i32 6, i32 8>, <16 x i32> <i32 9, i32 3, i32 3, i32 8, i32 7, i32 5, i32 1, i32 8, i32 9, i32 2, i32 4, i32 8, i32 0, i32 6, i32 4, i32 5>, <16 x i32> <i32 0, i32 1, i32 3, i32 8, i32 9, i32 8, i32 0, i32 3, i32 2, i32 1, i32 6, i32 9, i32 9, i32 6, i32 1, i32 5>, i32 192)
3851  ret <16 x i32> %r
3852}
3853
3854define <2 x i64> @vpternlog_q_constv128_imm193() {
3855; CHECK-LABEL: @vpternlog_q_constv128_imm193(
3856; CHECK-NEXT:    ret <2 x i64> <i64 -15, i64 -6>
3857;
3858  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 9, i64 4>, <2 x i64> <i64 5, i64 1>, <2 x i64> <i64 6, i64 1>, i32 193)
3859  ret <2 x i64> %r
3860}
3861
3862define <8 x i32> @vpternlog_d_constv256_imm194() {
3863; CHECK-LABEL: @vpternlog_d_constv256_imm194(
3864; CHECK-NEXT:    ret <8 x i32> <i32 4, i32 4, i32 5, i32 0, i32 6, i32 8, i32 0, i32 1>
3865;
3866  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 6, i32 7, i32 8, i32 4, i32 3, i32 3, i32 5>, <8 x i32> <i32 2, i32 5, i32 5, i32 1, i32 5, i32 4, i32 4, i32 9>, <8 x i32> <i32 4, i32 4, i32 5, i32 1, i32 3, i32 8, i32 0, i32 1>, i32 194)
3867  ret <8 x i32> %r
3868}
3869
3870define <8 x i64> @vpternlog_q_constv512_imm195() {
3871; CHECK-LABEL: @vpternlog_q_constv512_imm195(
3872; CHECK-NEXT:    ret <8 x i64> <i64 -4, i64 -5, i64 -1, i64 -5, i64 -1, i64 -5, i64 -3, i64 -1>
3873;
3874  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 6, i64 5, i64 1, i64 5, i64 4, i64 4, i64 2, i64 5>, <8 x i64> <i64 5, i64 1, i64 1, i64 1, i64 4, i64 0, i64 0, i64 5>, <8 x i64> <i64 1, i64 4, i64 0, i64 5, i64 5, i64 3, i64 1, i64 5>, i32 195)
3875  ret <8 x i64> %r
3876}
3877
3878define <4 x i32> @vpternlog_d_constv128_imm196() {
3879; CHECK-LABEL: @vpternlog_d_constv128_imm196(
3880; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 3, i32 8, i32 4>
3881;
3882  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 9, i32 6, i32 6, i32 6>, <4 x i32> <i32 1, i32 3, i32 9, i32 5>, <4 x i32> <i32 5, i32 4, i32 1, i32 5>, i32 196)
3883  ret <4 x i32> %r
3884}
3885
3886define <4 x i64> @vpternlog_q_constv256_imm197() {
3887; CHECK-LABEL: @vpternlog_q_constv256_imm197(
3888; CHECK-NEXT:    ret <4 x i64> <i64 -8, i64 -2, i64 -10, i64 -8>
3889;
3890  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 2, i64 8, i64 9>, <4 x i64> <i64 8, i64 7, i64 7, i64 8>, <4 x i64> <i64 7, i64 1, i64 1, i64 7>, i32 197)
3891  ret <4 x i64> %r
3892}
3893
3894define <16 x i32> @vpternlog_d_constv512_imm198() {
3895; CHECK-LABEL: @vpternlog_d_constv512_imm198(
3896; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 12, i32 7, i32 0, i32 3, i32 8, i32 8, i32 6, i32 4, i32 6, i32 7, i32 6, i32 7, i32 1, i32 0, i32 1>
3897;
3898  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 1, i32 2, i32 6, i32 7, i32 1, i32 3, i32 5, i32 0, i32 0, i32 7, i32 3, i32 5, i32 7, i32 7, i32 8, i32 9>, <16 x i32> <i32 5, i32 9, i32 6, i32 0, i32 5, i32 8, i32 8, i32 2, i32 7, i32 6, i32 7, i32 4, i32 7, i32 1, i32 5, i32 1>, <16 x i32> <i32 3, i32 5, i32 3, i32 1, i32 6, i32 2, i32 4, i32 4, i32 3, i32 0, i32 0, i32 3, i32 5, i32 1, i32 5, i32 9>, i32 198)
3899  ret <16 x i32> %r
3900}
3901
3902define <2 x i64> @vpternlog_q_constv128_imm199() {
3903; CHECK-LABEL: @vpternlog_q_constv128_imm199(
3904; CHECK-NEXT:    ret <2 x i64> <i64 -9, i64 -5>
3905;
3906  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 6>, <2 x i64> <i64 2, i64 3>, <2 x i64> <i64 4, i64 0>, i32 199)
3907  ret <2 x i64> %r
3908}
3909
3910define <8 x i32> @vpternlog_d_constv256_imm200() {
3911; CHECK-LABEL: @vpternlog_d_constv256_imm200(
3912; CHECK-NEXT:    ret <8 x i32> <i32 0, i32 5, i32 0, i32 1, i32 1, i32 5, i32 1, i32 9>
3913;
3914  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 4, i32 7, i32 4, i32 2, i32 8, i32 7, i32 1, i32 3>, <8 x i32> <i32 3, i32 5, i32 1, i32 5, i32 5, i32 5, i32 1, i32 9>, <8 x i32> <i32 8, i32 8, i32 4, i32 3, i32 9, i32 9, i32 9, i32 9>, i32 200)
3915  ret <8 x i32> %r
3916}
3917
3918define <8 x i64> @vpternlog_q_constv512_imm201() {
3919; CHECK-LABEL: @vpternlog_q_constv512_imm201(
3920; CHECK-NEXT:    ret <8 x i64> <i64 -5, i64 -8, i64 -13, i64 -1, i64 -2, i64 -1, i64 -15, i64 -4>
3921;
3922  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 2, i64 8, i64 1, i64 9, i64 0, i64 2, i64 3>, <8 x i64> <i64 5, i64 0, i64 5, i64 7, i64 8, i64 8, i64 8, i64 4>, <8 x i64> <i64 0, i64 7, i64 1, i64 6, i64 1, i64 8, i64 6, i64 4>, i32 201)
3923  ret <8 x i64> %r
3924}
3925
3926define <4 x i32> @vpternlog_d_constv128_imm202() {
3927; CHECK-LABEL: @vpternlog_d_constv128_imm202(
3928; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 8, i32 8, i32 2>
3929;
3930  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 1, i32 8, i32 6, i32 2>, <4 x i32> <i32 7, i32 8, i32 8, i32 3>, <4 x i32> <i32 0, i32 8, i32 8, i32 2>, i32 202)
3931  ret <4 x i32> %r
3932}
3933
3934define <4 x i64> @vpternlog_q_constv256_imm203() {
3935; CHECK-LABEL: @vpternlog_q_constv256_imm203(
3936; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -8, i64 -3, i64 -15>
3937;
3938  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 0, i64 6, i64 6, i64 6>, <4 x i64> <i64 3, i64 9, i64 4, i64 9>, <4 x i64> <i64 6, i64 8, i64 0, i64 7>, i32 203)
3939  ret <4 x i64> %r
3940}
3941
3942define <16 x i32> @vpternlog_d_constv512_imm204() {
3943; CHECK-LABEL: @vpternlog_d_constv512_imm204(
3944; CHECK-NEXT:    ret <16 x i32> <i32 9, i32 7, i32 8, i32 1, i32 3, i32 8, i32 0, i32 8, i32 1, i32 5, i32 1, i32 2, i32 0, i32 4, i32 3, i32 7>
3945;
3946  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 8, i32 0, i32 3, i32 7, i32 8, i32 9, i32 0, i32 5, i32 0, i32 5, i32 4, i32 8, i32 6, i32 3, i32 4, i32 5>, <16 x i32> <i32 9, i32 7, i32 8, i32 1, i32 3, i32 8, i32 0, i32 8, i32 1, i32 5, i32 1, i32 2, i32 0, i32 4, i32 3, i32 7>, <16 x i32> <i32 3, i32 8, i32 5, i32 5, i32 4, i32 9, i32 4, i32 1, i32 1, i32 4, i32 7, i32 4, i32 6, i32 7, i32 1, i32 1>, i32 204)
3947  ret <16 x i32> %r
3948}
3949
3950define <2 x i64> @vpternlog_q_constv128_imm205() {
3951; CHECK-LABEL: @vpternlog_q_constv128_imm205(
3952; CHECK-NEXT:    ret <2 x i64> <i64 -9, i64 -8>
3953;
3954  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 3>, <2 x i64> <i64 5, i64 0>, <2 x i64> <i64 4, i64 4>, i32 205)
3955  ret <2 x i64> %r
3956}
3957
3958define <8 x i32> @vpternlog_d_constv256_imm206() {
3959; CHECK-LABEL: @vpternlog_d_constv256_imm206(
3960; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 7, i32 6, i32 9, i32 13, i32 1, i32 13, i32 13>
3961;
3962  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 6, i32 9, i32 7, i32 2, i32 3, i32 0, i32 3>, <8 x i32> <i32 6, i32 7, i32 6, i32 9, i32 8, i32 1, i32 9, i32 9>, <8 x i32> <i32 2, i32 3, i32 3, i32 7, i32 7, i32 0, i32 4, i32 6>, i32 206)
3963  ret <8 x i32> %r
3964}
3965
3966define <8 x i64> @vpternlog_q_constv512_imm207() {
3967; CHECK-LABEL: @vpternlog_q_constv512_imm207(
3968; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -8, i64 -1, i64 -9, i64 -2, i64 -1, i64 -1, i64 -2>
3969;
3970  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 4, i64 7, i64 4, i64 9, i64 3, i64 3, i64 0, i64 5>, <8 x i64> <i64 4, i64 0, i64 4, i64 7, i64 6, i64 7, i64 5, i64 4>, <8 x i64> <i64 8, i64 4, i64 7, i64 5, i64 9, i64 6, i64 6, i64 0>, i32 207)
3971  ret <8 x i64> %r
3972}
3973
3974define <4 x i32> @vpternlog_d_constv128_imm208() {
3975; CHECK-LABEL: @vpternlog_d_constv128_imm208(
3976; CHECK-NEXT:    ret <4 x i32> <i32 3, i32 6, i32 7, i32 9>
3977;
3978  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 3, i32 6, i32 7, i32 9>, <4 x i32> <i32 3, i32 7, i32 7, i32 5>, <4 x i32> <i32 2, i32 4, i32 0, i32 5>, i32 208)
3979  ret <4 x i32> %r
3980}
3981
3982define <4 x i64> @vpternlog_q_constv256_imm209() {
3983; CHECK-LABEL: @vpternlog_q_constv256_imm209(
3984; CHECK-NEXT:    ret <4 x i64> <i64 -6, i64 -11, i64 -7, i64 -4>
3985;
3986  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 4, i64 5, i64 1>, <4 x i64> <i64 3, i64 2, i64 1, i64 2>, <4 x i64> <i64 7, i64 8, i64 6, i64 3>, i32 209)
3987  ret <4 x i64> %r
3988}
3989
3990define <16 x i32> @vpternlog_d_constv512_imm210() {
3991; CHECK-LABEL: @vpternlog_d_constv512_imm210(
3992; CHECK-NEXT:    ret <16 x i32> <i32 13, i32 6, i32 0, i32 2, i32 7, i32 9, i32 1, i32 4, i32 13, i32 1, i32 9, i32 5, i32 9, i32 8, i32 4, i32 4>
3993;
3994  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 9, i32 5, i32 0, i32 3, i32 2, i32 1, i32 1, i32 4, i32 9, i32 5, i32 8, i32 5, i32 8, i32 8, i32 4, i32 5>, <16 x i32> <i32 0, i32 4, i32 5, i32 6, i32 2, i32 1, i32 4, i32 5, i32 3, i32 9, i32 8, i32 9, i32 6, i32 4, i32 2, i32 4>, <16 x i32> <i32 4, i32 7, i32 1, i32 5, i32 5, i32 8, i32 4, i32 5, i32 4, i32 5, i32 1, i32 0, i32 7, i32 0, i32 0, i32 1>, i32 210)
3995  ret <16 x i32> %r
3996}
3997
3998define <2 x i64> @vpternlog_q_constv128_imm211() {
3999; CHECK-LABEL: @vpternlog_q_constv128_imm211(
4000; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -13>
4001;
4002  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 8, i64 8>, <2 x i64> <i64 0, i64 4>, <2 x i64> <i64 2, i64 9>, i32 211)
4003  ret <2 x i64> %r
4004}
4005
4006define <8 x i32> @vpternlog_d_constv256_imm212() {
4007; CHECK-LABEL: @vpternlog_d_constv256_imm212(
4008; CHECK-NEXT:    ret <8 x i32> <i32 11, i32 7, i32 4, i32 4, i32 8, i32 9, i32 9, i32 2>
4009;
4010  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 9, i32 8, i32 6, i32 4, i32 8, i32 9, i32 9, i32 3>, <8 x i32> <i32 2, i32 7, i32 5, i32 5, i32 3, i32 2, i32 1, i32 6>, <8 x i32> <i32 4, i32 8, i32 3, i32 1, i32 7, i32 6, i32 4, i32 7>, i32 212)
4011  ret <8 x i32> %r
4012}
4013
4014define <8 x i64> @vpternlog_q_constv512_imm213() {
4015; CHECK-LABEL: @vpternlog_q_constv512_imm213(
4016; CHECK-NEXT:    ret <8 x i64> <i64 -9, i64 -8, i64 -8, i64 -1, i64 -4, i64 -9, i64 -1, i64 -2>
4017;
4018  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 0, i64 8, i64 8, i64 2, i64 8, i64 1, i64 8>, <8 x i64> <i64 8, i64 7, i64 1, i64 5, i64 0, i64 6, i64 2, i64 1>, <8 x i64> <i64 8, i64 7, i64 7, i64 0, i64 3, i64 8, i64 0, i64 1>, i32 213)
4019  ret <8 x i64> %r
4020}
4021
4022define <4 x i32> @vpternlog_d_constv128_imm214() {
4023; CHECK-LABEL: @vpternlog_d_constv128_imm214(
4024; CHECK-NEXT:    ret <4 x i32> <i32 3, i32 15, i32 7, i32 1>
4025;
4026  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 6, i32 7, i32 7>, <4 x i32> <i32 3, i32 1, i32 1, i32 0>, <4 x i32> <i32 6, i32 8, i32 1, i32 6>, i32 214)
4027  ret <4 x i32> %r
4028}
4029
4030define <4 x i64> @vpternlog_q_constv256_imm215() {
4031; CHECK-LABEL: @vpternlog_q_constv256_imm215(
4032; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -2, i64 -1, i64 -3>
4033;
4034  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 6, i64 4, i64 3, i64 2>, <4 x i64> <i64 3, i64 5, i64 5, i64 8>, <4 x i64> <i64 2, i64 5, i64 8, i64 6>, i32 215)
4035  ret <4 x i64> %r
4036}
4037
4038define <16 x i32> @vpternlog_d_constv512_imm216() {
4039; CHECK-LABEL: @vpternlog_d_constv512_imm216(
4040; CHECK-NEXT:    ret <16 x i32> <i32 4, i32 9, i32 9, i32 1, i32 0, i32 8, i32 8, i32 8, i32 8, i32 0, i32 0, i32 13, i32 4, i32 9, i32 1, i32 0>
4041;
4042  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 9, i32 9, i32 1, i32 4, i32 8, i32 8, i32 8, i32 8, i32 2, i32 0, i32 9, i32 6, i32 9, i32 1, i32 1>, <16 x i32> <i32 4, i32 8, i32 8, i32 0, i32 0, i32 0, i32 9, i32 4, i32 0, i32 1, i32 1, i32 5, i32 5, i32 8, i32 9, i32 0>, <16 x i32> <i32 6, i32 2, i32 2, i32 2, i32 6, i32 3, i32 4, i32 3, i32 6, i32 6, i32 2, i32 5, i32 6, i32 6, i32 4, i32 1>, i32 216)
4043  ret <16 x i32> %r
4044}
4045
4046define <2 x i64> @vpternlog_q_constv128_imm217() {
4047; CHECK-LABEL: @vpternlog_q_constv128_imm217(
4048; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -9>
4049;
4050  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 7>, <2 x i64> <i64 0, i64 6>, <2 x i64> <i64 0, i64 8>, i32 217)
4051  ret <2 x i64> %r
4052}
4053
4054define <8 x i32> @vpternlog_d_constv256_imm218() {
4055; CHECK-LABEL: @vpternlog_d_constv256_imm218(
4056; CHECK-NEXT:    ret <8 x i32> <i32 6, i32 6, i32 7, i32 9, i32 13, i32 4, i32 4, i32 4>
4057;
4058  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 6, i32 0, i32 7, i32 1, i32 5, i32 0, i32 4, i32 3>, <8 x i32> <i32 0, i32 6, i32 5, i32 7, i32 6, i32 9, i32 1, i32 0>, <8 x i32> <i32 0, i32 6, i32 1, i32 8, i32 8, i32 4, i32 0, i32 7>, i32 218)
4059  ret <8 x i32> %r
4060}
4061
4062define <8 x i64> @vpternlog_q_constv512_imm219() {
4063; CHECK-LABEL: @vpternlog_q_constv512_imm219(
4064; CHECK-NEXT:    ret <8 x i64> <i64 -3, i64 -6, i64 -1, i64 -1, i64 -7, i64 -2, i64 -1, i64 -1>
4065;
4066  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 1, i64 2, i64 0, i64 6, i64 7, i64 1, i64 4, i64 4>, <8 x i64> <i64 7, i64 7, i64 1, i64 1, i64 1, i64 6, i64 6, i64 1>, <8 x i64> <i64 4, i64 2, i64 3, i64 1, i64 7, i64 7, i64 3, i64 9>, i32 219)
4067  ret <8 x i64> %r
4068}
4069
4070define <4 x i32> @vpternlog_d_constv128_imm220() {
4071; CHECK-LABEL: @vpternlog_d_constv128_imm220(
4072; CHECK-NEXT:    ret <4 x i32> <i32 2, i32 4, i32 10, i32 6>
4073;
4074  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 2, i32 4, i32 3, i32 6>, <4 x i32> <i32 0, i32 4, i32 8, i32 4>, <4 x i32> <i32 5, i32 9, i32 9, i32 8>, i32 220)
4075  ret <4 x i32> %r
4076}
4077
4078define <4 x i64> @vpternlog_q_constv256_imm221() {
4079; CHECK-LABEL: @vpternlog_q_constv256_imm221(
4080; CHECK-NEXT:    ret <4 x i64> <i64 -9, i64 -5, i64 -6, i64 -9>
4081;
4082  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 7, i64 2, i64 2>, <4 x i64> <i64 5, i64 3, i64 8, i64 2>, <4 x i64> <i64 9, i64 5, i64 5, i64 8>, i32 221)
4083  ret <4 x i64> %r
4084}
4085
4086define <16 x i32> @vpternlog_d_constv512_imm222() {
4087; CHECK-LABEL: @vpternlog_d_constv512_imm222(
4088; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 14, i32 15, i32 7, i32 2, i32 7, i32 14, i32 3, i32 11, i32 6, i32 6, i32 14, i32 15, i32 7, i32 7, i32 5>
4089;
4090  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 2, i32 3, i32 7, i32 2, i32 5, i32 2, i32 9, i32 0, i32 7, i32 7, i32 1, i32 7, i32 9, i32 0, i32 6, i32 6>, <16 x i32> <i32 0, i32 6, i32 8, i32 7, i32 2, i32 6, i32 6, i32 2, i32 9, i32 6, i32 6, i32 2, i32 7, i32 3, i32 1, i32 5>, <16 x i32> <i32 3, i32 9, i32 0, i32 0, i32 7, i32 3, i32 5, i32 1, i32 4, i32 1, i32 7, i32 9, i32 4, i32 4, i32 0, i32 7>, i32 222)
4091  ret <16 x i32> %r
4092}
4093
4094define <2 x i64> @vpternlog_q_constv128_imm223() {
4095; CHECK-LABEL: @vpternlog_q_constv128_imm223(
4096; CHECK-NEXT:    ret <2 x i64> splat (i64 -1)
4097;
4098  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 4, i64 3>, <2 x i64> <i64 7, i64 9>, <2 x i64> <i64 5, i64 0>, i32 223)
4099  ret <2 x i64> %r
4100}
4101
4102define <8 x i32> @vpternlog_d_constv256_imm224() {
4103; CHECK-LABEL: @vpternlog_d_constv256_imm224(
4104; CHECK-NEXT:    ret <8 x i32> <i32 8, i32 1, i32 1, i32 0, i32 0, i32 5, i32 1, i32 1>
4105;
4106  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 8, i32 7, i32 7, i32 8, i32 0, i32 7, i32 9, i32 1>, <8 x i32> <i32 8, i32 9, i32 8, i32 0, i32 8, i32 1, i32 5, i32 7>, <8 x i32> <i32 2, i32 8, i32 9, i32 2, i32 8, i32 5, i32 3, i32 0>, i32 224)
4107  ret <8 x i32> %r
4108}
4109
4110define <8 x i64> @vpternlog_q_constv512_imm225() {
4111; CHECK-LABEL: @vpternlog_q_constv512_imm225(
4112; CHECK-NEXT:    ret <8 x i64> <i64 -6, i64 -9, i64 -12, i64 -14, i64 -10, i64 -9, i64 -7, i64 -4>
4113;
4114  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 3, i64 1, i64 1, i64 7, i64 4, i64 7, i64 1, i64 0>, <8 x i64> <i64 0, i64 8, i64 8, i64 8, i64 8, i64 7, i64 1, i64 2>, <8 x i64> <i64 6, i64 1, i64 2, i64 2, i64 5, i64 8, i64 6, i64 3>, i32 225)
4115  ret <8 x i64> %r
4116}
4117
4118define <4 x i32> @vpternlog_d_constv128_imm226() {
4119; CHECK-LABEL: @vpternlog_d_constv128_imm226(
4120; CHECK-NEXT:    ret <4 x i32> <i32 1, i32 2, i32 2, i32 1>
4121;
4122  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 2, i32 3, i32 7>, <4 x i32> <i32 8, i32 6, i32 4, i32 9>, <4 x i32> <i32 9, i32 4, i32 2, i32 1>, i32 226)
4123  ret <4 x i32> %r
4124}
4125
4126define <4 x i64> @vpternlog_q_constv256_imm227() {
4127; CHECK-LABEL: @vpternlog_q_constv256_imm227(
4128; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -2, i64 -5, i64 -6>
4129;
4130  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 5, i64 6, i64 3, i64 2>, <4 x i64> <i64 2, i64 7, i64 7, i64 5>, <4 x i64> <i64 1, i64 0, i64 4, i64 2>, i32 227)
4131  ret <4 x i64> %r
4132}
4133
4134define <16 x i32> @vpternlog_d_constv512_imm228() {
4135; CHECK-LABEL: @vpternlog_d_constv512_imm228(
4136; CHECK-NEXT:    ret <16 x i32> <i32 1, i32 6, i32 0, i32 5, i32 0, i32 3, i32 4, i32 3, i32 5, i32 2, i32 2, i32 2, i32 2, i32 9, i32 2, i32 1>
4137;
4138  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 6, i32 2, i32 9, i32 0, i32 2, i32 8, i32 6, i32 1, i32 2, i32 2, i32 8, i32 0, i32 0, i32 2, i32 0>, <16 x i32> <i32 5, i32 7, i32 0, i32 5, i32 4, i32 3, i32 7, i32 3, i32 5, i32 1, i32 3, i32 2, i32 3, i32 9, i32 4, i32 3>, <16 x i32> <i32 4, i32 3, i32 8, i32 3, i32 7, i32 4, i32 3, i32 0, i32 2, i32 7, i32 5, i32 5, i32 1, i32 4, i32 7, i32 6>, i32 228)
4139  ret <16 x i32> %r
4140}
4141
4142define <2 x i64> @vpternlog_q_constv128_imm229() {
4143; CHECK-LABEL: @vpternlog_q_constv128_imm229(
4144; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -3>
4145;
4146  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 0, i64 2>, <2 x i64> <i64 9, i64 4>, <2 x i64> <i64 0, i64 0>, i32 229)
4147  ret <2 x i64> %r
4148}
4149
4150define <8 x i32> @vpternlog_d_constv256_imm230() {
4151; CHECK-LABEL: @vpternlog_d_constv256_imm230(
4152; CHECK-NEXT:    ret <8 x i32> <i32 15, i32 6, i32 1, i32 3, i32 7, i32 1, i32 3, i32 1>
4153;
4154  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 7, i32 6, i32 1, i32 3, i32 7, i32 6, i32 9, i32 6>, <8 x i32> <i32 9, i32 7, i32 0, i32 4, i32 7, i32 0, i32 0, i32 8>, <8 x i32> <i32 6, i32 1, i32 1, i32 7, i32 5, i32 1, i32 3, i32 9>, i32 230)
4155  ret <8 x i32> %r
4156}
4157
4158define <8 x i64> @vpternlog_q_constv512_imm231() {
4159; CHECK-LABEL: @vpternlog_q_constv512_imm231(
4160; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -7, i64 -9, i64 -2, i64 -2, i64 -11, i64 -1, i64 -1>
4161;
4162  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 9, i64 3, i64 9, i64 0, i64 3, i64 9, i64 6, i64 1>, <8 x i64> <i64 9, i64 5, i64 3, i64 3, i64 2, i64 3, i64 4, i64 7>, <8 x i64> <i64 7, i64 5, i64 0, i64 1, i64 6, i64 3, i64 7, i64 1>, i32 231)
4163  ret <8 x i64> %r
4164}
4165
4166define <4 x i32> @vpternlog_d_constv128_imm232() {
4167; CHECK-LABEL: @vpternlog_d_constv128_imm232(
4168; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 2, i32 3, i32 7>
4169;
4170  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 0, i32 7, i32 7, i32 7>, <4 x i32> <i32 9, i32 8, i32 0, i32 6>, <4 x i32> <i32 4, i32 2, i32 3, i32 5>, i32 232)
4171  ret <4 x i32> %r
4172}
4173
4174define <4 x i64> @vpternlog_q_constv256_imm233() {
4175; CHECK-LABEL: @vpternlog_q_constv256_imm233(
4176; CHECK-NEXT:    ret <4 x i64> <i64 -2, i64 -15, i64 -8, i64 -9>
4177;
4178  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 3, i64 4, i64 1, i64 5>, <4 x i64> <i64 2, i64 3, i64 0, i64 5>, <4 x i64> <i64 0, i64 9, i64 6, i64 9>, i32 233)
4179  ret <4 x i64> %r
4180}
4181
4182define <16 x i32> @vpternlog_d_constv512_imm234() {
4183; CHECK-LABEL: @vpternlog_d_constv512_imm234(
4184; CHECK-NEXT:    ret <16 x i32> <i32 5, i32 5, i32 11, i32 9, i32 8, i32 4, i32 9, i32 3, i32 5, i32 9, i32 9, i32 4, i32 15, i32 3, i32 5, i32 15>
4185;
4186  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 4, i32 4, i32 2, i32 3, i32 9, i32 4, i32 8, i32 1, i32 1, i32 4, i32 7, i32 7, i32 9, i32 3, i32 4, i32 8>, <16 x i32> <i32 9, i32 4, i32 2, i32 9, i32 8, i32 0, i32 3, i32 9, i32 5, i32 8, i32 9, i32 0, i32 8, i32 7, i32 7, i32 9>, <16 x i32> <i32 5, i32 1, i32 9, i32 9, i32 8, i32 4, i32 9, i32 3, i32 5, i32 9, i32 9, i32 4, i32 7, i32 1, i32 5, i32 7>, i32 234)
4187  ret <16 x i32> %r
4188}
4189
4190define <2 x i64> @vpternlog_q_constv128_imm235() {
4191; CHECK-LABEL: @vpternlog_q_constv128_imm235(
4192; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -14>
4193;
4194  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 5>, <2 x i64> <i64 2, i64 8>, <2 x i64> <i64 8, i64 2>, i32 235)
4195  ret <2 x i64> %r
4196}
4197
4198define <8 x i32> @vpternlog_d_constv256_imm236() {
4199; CHECK-LABEL: @vpternlog_d_constv256_imm236(
4200; CHECK-NEXT:    ret <8 x i32> <i32 9, i32 5, i32 7, i32 5, i32 9, i32 5, i32 4, i32 3>
4201;
4202  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 4, i32 9, i32 5, i32 9, i32 3, i32 9, i32 0>, <8 x i32> <i32 9, i32 5, i32 6, i32 5, i32 9, i32 5, i32 4, i32 3>, <8 x i32> <i32 5, i32 5, i32 1, i32 7, i32 5, i32 8, i32 4, i32 2>, i32 236)
4203  ret <8 x i32> %r
4204}
4205
4206define <8 x i64> @vpternlog_q_constv512_imm237() {
4207; CHECK-LABEL: @vpternlog_q_constv512_imm237(
4208; CHECK-NEXT:    ret <8 x i64> <i64 -2, i64 -9, i64 -1, i64 -9, i64 -2, i64 -8, i64 -9, i64 -1>
4209;
4210  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 5, i64 3, i64 5, i64 9, i64 0, i64 0, i64 8, i64 5>, <8 x i64> <i64 6, i64 3, i64 7, i64 6, i64 8, i64 8, i64 7, i64 7>, <8 x i64> <i64 2, i64 9, i64 4, i64 5, i64 1, i64 7, i64 2, i64 1>, i32 237)
4211  ret <8 x i64> %r
4212}
4213
4214define <4 x i32> @vpternlog_d_constv128_imm238() {
4215; CHECK-LABEL: @vpternlog_d_constv128_imm238(
4216; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 5, i32 15, i32 11>
4217;
4218  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 8, i32 9, i32 1, i32 4>, <4 x i32> <i32 7, i32 1, i32 7, i32 3>, <4 x i32> <i32 5, i32 4, i32 8, i32 9>, i32 238)
4219  ret <4 x i32> %r
4220}
4221
4222define <4 x i64> @vpternlog_q_constv256_imm239() {
4223; CHECK-LABEL: @vpternlog_q_constv256_imm239(
4224; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -5, i64 -1, i64 -9>
4225;
4226  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 8, i64 4, i64 5, i64 8>, <4 x i64> <i64 1, i64 0, i64 9, i64 6>, <4 x i64> <i64 8, i64 0, i64 5, i64 4>, i32 239)
4227  ret <4 x i64> %r
4228}
4229
4230define <16 x i32> @vpternlog_d_constv512_imm240() {
4231; CHECK-LABEL: @vpternlog_d_constv512_imm240(
4232; CHECK-NEXT:    ret <16 x i32> <i32 3, i32 8, i32 5, i32 3, i32 1, i32 4, i32 7, i32 7, i32 8, i32 7, i32 7, i32 7, i32 2, i32 0, i32 9, i32 8>
4233;
4234  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 3, i32 8, i32 5, i32 3, i32 1, i32 4, i32 7, i32 7, i32 8, i32 7, i32 7, i32 7, i32 2, i32 0, i32 9, i32 8>, <16 x i32> <i32 8, i32 0, i32 7, i32 3, i32 9, i32 2, i32 3, i32 4, i32 7, i32 5, i32 8, i32 3, i32 8, i32 1, i32 8, i32 6>, <16 x i32> <i32 0, i32 8, i32 4, i32 1, i32 1, i32 6, i32 2, i32 7, i32 8, i32 9, i32 0, i32 0, i32 9, i32 5, i32 1, i32 3>, i32 240)
4235  ret <16 x i32> %r
4236}
4237
4238define <2 x i64> @vpternlog_q_constv128_imm241() {
4239; CHECK-LABEL: @vpternlog_q_constv128_imm241(
4240; CHECK-NEXT:    ret <2 x i64> <i64 -9, i64 -2>
4241;
4242  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 7, i64 6>, <2 x i64> <i64 8, i64 7>, <2 x i64> <i64 1, i64 4>, i32 241)
4243  ret <2 x i64> %r
4244}
4245
4246define <8 x i32> @vpternlog_d_constv256_imm242() {
4247; CHECK-LABEL: @vpternlog_d_constv256_imm242(
4248; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 6, i32 4, i32 6, i32 15, i32 9, i32 11, i32 5>
4249;
4250  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 3, i32 6, i32 0, i32 0, i32 9, i32 1, i32 9, i32 5>, <8 x i32> <i32 1, i32 3, i32 3, i32 9, i32 8, i32 3, i32 4, i32 4>, <8 x i32> <i32 5, i32 3, i32 5, i32 6, i32 7, i32 9, i32 7, i32 0>, i32 242)
4251  ret <8 x i32> %r
4252}
4253
4254define <8 x i64> @vpternlog_q_constv512_imm243() {
4255; CHECK-LABEL: @vpternlog_q_constv512_imm243(
4256; CHECK-NEXT:    ret <8 x i64> <i64 -10, i64 -5, i64 -6, i64 -5, i64 -2, i64 -1, i64 -1, i64 -10>
4257;
4258  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 3, i64 6, i64 6, i64 7, i64 0>, <8 x i64> <i64 9, i64 5, i64 5, i64 4, i64 3, i64 2, i64 5, i64 9>, <8 x i64> <i64 0, i64 7, i64 0, i64 1, i64 4, i64 5, i64 5, i64 6>, i32 243)
4259  ret <8 x i64> %r
4260}
4261
4262define <4 x i32> @vpternlog_d_constv128_imm244() {
4263; CHECK-LABEL: @vpternlog_d_constv128_imm244(
4264; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 5, i32 9, i32 7>
4265;
4266  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 7, i32 5, i32 8, i32 7>, <4 x i32> <i32 3, i32 1, i32 1, i32 2>, <4 x i32> <i32 9, i32 3, i32 0, i32 3>, i32 244)
4267  ret <4 x i32> %r
4268}
4269
4270define <4 x i64> @vpternlog_q_constv256_imm245() {
4271; CHECK-LABEL: @vpternlog_q_constv256_imm245(
4272; CHECK-NEXT:    ret <4 x i64> <i64 -7, i64 -1, i64 -5, i64 -10>
4273;
4274  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 9, i64 3, i64 9, i64 6>, <4 x i64> <i64 3, i64 6, i64 1, i64 7>, <4 x i64> <i64 7, i64 3, i64 4, i64 9>, i32 245)
4275  ret <4 x i64> %r
4276}
4277
4278define <16 x i32> @vpternlog_d_constv512_imm246() {
4279; CHECK-LABEL: @vpternlog_d_constv512_imm246(
4280; CHECK-NEXT:    ret <16 x i32> <i32 7, i32 3, i32 15, i32 3, i32 7, i32 7, i32 6, i32 5, i32 9, i32 7, i32 13, i32 4, i32 5, i32 13, i32 3, i32 15>
4281;
4282  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 7, i32 1, i32 9, i32 2, i32 5, i32 6, i32 6, i32 4, i32 9, i32 5, i32 8, i32 4, i32 0, i32 5, i32 3, i32 6>, <16 x i32> <i32 6, i32 5, i32 6, i32 4, i32 6, i32 2, i32 2, i32 7, i32 3, i32 6, i32 3, i32 0, i32 2, i32 8, i32 7, i32 9>, <16 x i32> <i32 7, i32 7, i32 1, i32 5, i32 4, i32 5, i32 4, i32 6, i32 2, i32 1, i32 6, i32 0, i32 7, i32 1, i32 6, i32 4>, i32 246)
4283  ret <16 x i32> %r
4284}
4285
4286define <2 x i64> @vpternlog_q_constv128_imm247() {
4287; CHECK-LABEL: @vpternlog_q_constv128_imm247(
4288; CHECK-NEXT:    ret <2 x i64> splat (i64 -1)
4289;
4290  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 2, i64 6>, <2 x i64> <i64 7, i64 7>, <2 x i64> <i64 0, i64 8>, i32 247)
4291  ret <2 x i64> %r
4292}
4293
4294define <8 x i32> @vpternlog_d_constv256_imm248() {
4295; CHECK-LABEL: @vpternlog_d_constv256_imm248(
4296; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 7, i32 12, i32 3, i32 6, i32 6, i32 6, i32 5>
4297;
4298  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 1, i32 2, i32 4, i32 3, i32 2, i32 6, i32 6, i32 5>, <8 x i32> <i32 6, i32 5, i32 8, i32 4, i32 4, i32 5, i32 4, i32 4>, <8 x i32> <i32 6, i32 7, i32 8, i32 3, i32 4, i32 4, i32 7, i32 6>, i32 248)
4299  ret <8 x i32> %r
4300}
4301
4302define <8 x i64> @vpternlog_q_constv512_imm249() {
4303; CHECK-LABEL: @vpternlog_q_constv512_imm249(
4304; CHECK-NEXT:    ret <8 x i64> <i64 -1, i64 -1, i64 -9, i64 -1, i64 -1, i64 -3, i64 -3, i64 -1>
4305;
4306  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 7, i64 5, i64 7, i64 2, i64 2, i64 4, i64 1, i64 3>, <8 x i64> <i64 4, i64 1, i64 8, i64 6, i64 0, i64 7, i64 2, i64 5>, <8 x i64> <i64 3, i64 5, i64 4, i64 6, i64 0, i64 1, i64 0, i64 7>, i32 249)
4307  ret <8 x i64> %r
4308}
4309
4310define <4 x i32> @vpternlog_d_constv128_imm250() {
4311; CHECK-LABEL: @vpternlog_d_constv128_imm250(
4312; CHECK-NEXT:    ret <4 x i32> <i32 7, i32 9, i32 3, i32 5>
4313;
4314  %r = tail call <4 x i32> @llvm.x86.avx512.pternlog.d.128(<4 x i32> <i32 6, i32 1, i32 3, i32 5>, <4 x i32> <i32 8, i32 4, i32 0, i32 9>, <4 x i32> <i32 3, i32 8, i32 3, i32 5>, i32 250)
4315  ret <4 x i32> %r
4316}
4317
4318define <4 x i64> @vpternlog_q_constv256_imm251() {
4319; CHECK-LABEL: @vpternlog_q_constv256_imm251(
4320; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -5, i64 -1, i64 -1>
4321;
4322  %r = tail call <4 x i64> @llvm.x86.avx512.pternlog.q.256(<4 x i64> <i64 2, i64 8, i64 4, i64 3>, <4 x i64> <i64 1, i64 5, i64 8, i64 1>, <4 x i64> <i64 1, i64 9, i64 9, i64 4>, i32 251)
4323  ret <4 x i64> %r
4324}
4325
4326define <16 x i32> @vpternlog_d_constv512_imm252() {
4327; CHECK-LABEL: @vpternlog_d_constv512_imm252(
4328; CHECK-NEXT:    ret <16 x i32> <i32 11, i32 13, i32 6, i32 3, i32 11, i32 6, i32 7, i32 3, i32 7, i32 7, i32 7, i32 8, i32 9, i32 15, i32 5, i32 7>
4329;
4330  %r = tail call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> <i32 2, i32 9, i32 6, i32 2, i32 3, i32 0, i32 3, i32 3, i32 3, i32 3, i32 5, i32 0, i32 9, i32 6, i32 4, i32 7>, <16 x i32> <i32 9, i32 4, i32 6, i32 1, i32 9, i32 6, i32 6, i32 0, i32 5, i32 7, i32 6, i32 8, i32 9, i32 9, i32 5, i32 1>, <16 x i32> <i32 2, i32 8, i32 3, i32 8, i32 7, i32 7, i32 2, i32 3, i32 0, i32 6, i32 5, i32 8, i32 0, i32 2, i32 6, i32 1>, i32 252)
4331  ret <16 x i32> %r
4332}
4333
4334define <2 x i64> @vpternlog_q_constv128_imm253() {
4335; CHECK-LABEL: @vpternlog_q_constv128_imm253(
4336; CHECK-NEXT:    ret <2 x i64> <i64 -1, i64 -9>
4337;
4338  %r = tail call <2 x i64> @llvm.x86.avx512.pternlog.q.128(<2 x i64> <i64 5, i64 6>, <2 x i64> <i64 6, i64 1>, <2 x i64> <i64 5, i64 9>, i32 253)
4339  ret <2 x i64> %r
4340}
4341
4342define <8 x i32> @vpternlog_d_constv256_imm254() {
4343; CHECK-LABEL: @vpternlog_d_constv256_imm254(
4344; CHECK-NEXT:    ret <8 x i32> <i32 7, i32 15, i32 3, i32 13, i32 15, i32 7, i32 9, i32 15>
4345;
4346  %r = tail call <8 x i32> @llvm.x86.avx512.pternlog.d.256(<8 x i32> <i32 5, i32 6, i32 1, i32 9, i32 4, i32 1, i32 9, i32 7>, <8 x i32> <i32 2, i32 9, i32 1, i32 5, i32 7, i32 1, i32 0, i32 9>, <8 x i32> <i32 1, i32 6, i32 2, i32 8, i32 8, i32 7, i32 0, i32 7>, i32 254)
4347  ret <8 x i32> %r
4348}
4349
4350define <8 x i64> @vpternlog_q_constv512_imm255() {
4351; CHECK-LABEL: @vpternlog_q_constv512_imm255(
4352; CHECK-NEXT:    ret <8 x i64> splat (i64 -1)
4353;
4354  %r = tail call <8 x i64> @llvm.x86.avx512.pternlog.q.512(<8 x i64> <i64 2, i64 3, i64 6, i64 0, i64 0, i64 6, i64 9, i64 3>, <8 x i64> <i64 4, i64 2, i64 1, i64 5, i64 3, i64 1, i64 5, i64 0>, <8 x i64> <i64 1, i64 5, i64 4, i64 4, i64 9, i64 7, i64 2, i64 5>, i32 255)
4355  ret <8 x i64> %r
4356}
4357