13978f37cSDhruv Chawla; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2*0f152a55SDhruv Chawla; RUN: opt < %s -passes=infer-alignment -S | FileCheck %s 33978f37cSDhruv Chawla 43978f37cSDhruv Chawladefine void @non_pow2_size(i177 %X) { 53978f37cSDhruv Chawla; CHECK-LABEL: define void @non_pow2_size 63978f37cSDhruv Chawla; CHECK-SAME: (i177 [[X:%.*]]) { 7*0f152a55SDhruv Chawla; CHECK-NEXT: [[A:%.*]] = alloca i177, align 8 8*0f152a55SDhruv Chawla; CHECK-NEXT: [[L1:%.*]] = load i177, ptr [[A]], align 8 9*0f152a55SDhruv Chawla; CHECK-NEXT: store i177 [[X]], ptr [[A]], align 8 103978f37cSDhruv Chawla; CHECK-NEXT: ret void 113978f37cSDhruv Chawla; 123978f37cSDhruv Chawla %A = alloca i177, align 1 133978f37cSDhruv Chawla %L1 = load i177, ptr %A, align 1 143978f37cSDhruv Chawla store i177 %X, ptr %A, align 1 153978f37cSDhruv Chawla ret void 163978f37cSDhruv Chawla} 173978f37cSDhruv Chawla 183978f37cSDhruv Chawla; TODO: For non-byte-sized vectors, current implementation assumes there is 193978f37cSDhruv Chawla; padding to the next byte boundary between elements. 203978f37cSDhruv Chawla@vector_i4 = constant [16 x <2 x i4>] zeroinitializer, align 8 213978f37cSDhruv Chawla 223978f37cSDhruv Chawladefine void @load_vector_i4(i4 %X) { 233978f37cSDhruv Chawla; CHECK-LABEL: define void @load_vector_i4 243978f37cSDhruv Chawla; CHECK-SAME: (i4 [[X:%.*]]) { 253978f37cSDhruv Chawla; CHECK-NEXT: [[PTR_0:%.*]] = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 1 263978f37cSDhruv Chawla; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 2 273978f37cSDhruv Chawla; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 4 283978f37cSDhruv Chawla; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 8 293978f37cSDhruv Chawla; CHECK-NEXT: [[RES_0:%.*]] = load i4, ptr [[PTR_0]], align 1 30*0f152a55SDhruv Chawla; CHECK-NEXT: [[RES_1:%.*]] = load i4, ptr [[PTR_1]], align 2 31*0f152a55SDhruv Chawla; CHECK-NEXT: [[RES_2:%.*]] = load i4, ptr [[PTR_2]], align 4 32*0f152a55SDhruv Chawla; CHECK-NEXT: [[RES_3:%.*]] = load i4, ptr [[PTR_3]], align 8 333978f37cSDhruv Chawla; CHECK-NEXT: store i4 [[X]], ptr [[PTR_0]], align 1 34*0f152a55SDhruv Chawla; CHECK-NEXT: store i4 [[X]], ptr [[PTR_1]], align 2 35*0f152a55SDhruv Chawla; CHECK-NEXT: store i4 [[X]], ptr [[PTR_2]], align 4 36*0f152a55SDhruv Chawla; CHECK-NEXT: store i4 [[X]], ptr [[PTR_3]], align 8 373978f37cSDhruv Chawla; CHECK-NEXT: ret void 383978f37cSDhruv Chawla; 393978f37cSDhruv Chawla %ptr.0 = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 1 403978f37cSDhruv Chawla %ptr.1 = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 2 413978f37cSDhruv Chawla %ptr.2 = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 4 423978f37cSDhruv Chawla %ptr.3 = getelementptr [16 x <2 x i4>], ptr @vector_i4, i64 0, i64 8 433978f37cSDhruv Chawla 443978f37cSDhruv Chawla %res.0 = load i4, ptr %ptr.0, align 1 453978f37cSDhruv Chawla %res.1 = load i4, ptr %ptr.1, align 1 463978f37cSDhruv Chawla %res.2 = load i4, ptr %ptr.2, align 1 473978f37cSDhruv Chawla %res.3 = load i4, ptr %ptr.3, align 1 483978f37cSDhruv Chawla 493978f37cSDhruv Chawla store i4 %X, ptr %ptr.0, align 1 503978f37cSDhruv Chawla store i4 %X, ptr %ptr.1, align 1 513978f37cSDhruv Chawla store i4 %X, ptr %ptr.2, align 1 523978f37cSDhruv Chawla store i4 %X, ptr %ptr.3, align 1 533978f37cSDhruv Chawla 543978f37cSDhruv Chawla ret void 553978f37cSDhruv Chawla} 56