xref: /llvm-project/llvm/test/Transforms/CodeGenPrepare/RISCV/fpclass-test.ll (revision 38a44bdc93db5b00310230f6542df39017b9a41b) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt -codegenprepare -S -mtriple=riscv64 < %s | FileCheck %s
3
4define i1 @test_is_inf_or_nan(double %arg) {
5; CHECK-LABEL: define i1 @test_is_inf_or_nan(
6; CHECK-SAME: double [[ARG:%.*]]) {
7; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 519)
8; CHECK-NEXT:    ret i1 [[TMP1]]
9;
10  %abs = tail call double @llvm.fabs.f64(double %arg)
11  %ret = fcmp ueq double %abs, 0x7FF0000000000000
12  ret i1 %ret
13}
14
15define i1 @test_is_not_inf_or_nan(double %arg) {
16; CHECK-LABEL: define i1 @test_is_not_inf_or_nan(
17; CHECK-SAME: double [[ARG:%.*]]) {
18; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 504)
19; CHECK-NEXT:    ret i1 [[TMP1]]
20;
21  %abs = tail call double @llvm.fabs.f64(double %arg)
22  %ret = fcmp one double %abs, 0x7FF0000000000000
23  ret i1 %ret
24}
25
26define i1 @test_is_inf(double %arg) {
27; CHECK-LABEL: define i1 @test_is_inf(
28; CHECK-SAME: double [[ARG:%.*]]) {
29; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 516)
30; CHECK-NEXT:    ret i1 [[TMP1]]
31;
32  %abs = tail call double @llvm.fabs.f64(double %arg)
33  %ret = fcmp oeq double %abs, 0x7FF0000000000000
34  ret i1 %ret
35}
36
37define i1 @test_is_not_inf(double %arg) {
38; CHECK-LABEL: define i1 @test_is_not_inf(
39; CHECK-SAME: double [[ARG:%.*]]) {
40; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f64(double [[ARG]], i32 507)
41; CHECK-NEXT:    ret i1 [[TMP1]]
42;
43  %abs = tail call double @llvm.fabs.f64(double %arg)
44  %ret = fcmp une double %abs, 0x7FF0000000000000
45  ret i1 %ret
46}
47
48define <vscale x 4 x i1> @test_vec_is_inf_or_nan(<vscale x 4 x double> %arg) {
49; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_inf_or_nan(
50; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
51; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 519)
52; CHECK-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
53;
54  %abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
55  %ret = fcmp ueq <vscale x 4 x double> %abs, splat (double 0x7FF0000000000000)
56  ret <vscale x 4 x i1> %ret
57}
58
59define <vscale x 4 x i1> @test_vec_is_not_inf_or_nan(<vscale x 4 x double> %arg) {
60; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_not_inf_or_nan(
61; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
62; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 504)
63; CHECK-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
64;
65  %abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
66  %ret = fcmp one <vscale x 4 x double> %abs, splat (double 0x7FF0000000000000)
67  ret <vscale x 4 x i1> %ret
68}
69
70define <vscale x 4 x i1> @test_vec_is_inf(<vscale x 4 x double> %arg) {
71; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_inf(
72; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
73; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 516)
74; CHECK-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
75;
76  %abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
77  %ret = fcmp oeq <vscale x 4 x double> %abs, splat (double 0x7FF0000000000000)
78  ret <vscale x 4 x i1> %ret
79}
80
81define <vscale x 4 x i1> @test_vec_is_not_inf(<vscale x 4 x double> %arg) {
82; CHECK-LABEL: define <vscale x 4 x i1> @test_vec_is_not_inf(
83; CHECK-SAME: <vscale x 4 x double> [[ARG:%.*]]) {
84; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> [[ARG]], i32 507)
85; CHECK-NEXT:    ret <vscale x 4 x i1> [[TMP1]]
86;
87  %abs = tail call <vscale x 4 x double> @llvm.fabs.nxv4f64(<vscale x 4 x double> %arg)
88  %ret = fcmp une <vscale x 4 x double> %abs, splat (double 0x7FF0000000000000)
89  ret <vscale x 4 x i1> %ret
90}
91
92define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
93; CHECK-LABEL: define i1 @test_fp128_is_inf_or_nan(
94; CHECK-SAME: fp128 [[ARG:%.*]]) {
95; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 519)
96; CHECK-NEXT:    ret i1 [[TMP1]]
97;
98  %abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
99  %ret = fcmp ueq fp128 %abs, 0xL00000000000000007FFF000000000000
100  ret i1 %ret
101}
102
103define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
104; CHECK-LABEL: define i1 @test_fp128_is_not_inf_or_nan(
105; CHECK-SAME: fp128 [[ARG:%.*]]) {
106; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 504)
107; CHECK-NEXT:    ret i1 [[TMP1]]
108;
109  %abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
110  %ret = fcmp one fp128 %abs, 0xL00000000000000007FFF000000000000
111  ret i1 %ret
112}
113
114define i1 @test_fp128_is_inf(fp128 %arg) {
115; CHECK-LABEL: define i1 @test_fp128_is_inf(
116; CHECK-SAME: fp128 [[ARG:%.*]]) {
117; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 516)
118; CHECK-NEXT:    ret i1 [[TMP1]]
119;
120  %abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
121  %ret = fcmp oeq fp128 %abs, 0xL00000000000000007FFF000000000000
122  ret i1 %ret
123}
124
125define i1 @test_fp128_is_not_inf(fp128 %arg) {
126; CHECK-LABEL: define i1 @test_fp128_is_not_inf(
127; CHECK-SAME: fp128 [[ARG:%.*]]) {
128; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.is.fpclass.f128(fp128 [[ARG]], i32 507)
129; CHECK-NEXT:    ret i1 [[TMP1]]
130;
131  %abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
132  %ret = fcmp une fp128 %abs, 0xL00000000000000007FFF000000000000
133  ret i1 %ret
134}
135