1// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s 2 3// Check that EncoderMethod for RegisterOperand is working correctly 4 5include "llvm/Target/Target.td" 6 7def ArchInstrInfo : InstrInfo { } 8 9def Arch : Target { 10 let InstructionSet = ArchInstrInfo; 11} 12 13def Reg : Register<"reg">; 14 15def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>; 16 17def RegOperand : RegisterOperand<RegClass> { 18 let EncoderMethod = "barEncoder"; 19} 20 21def foo1 : Instruction { 22 let Size = 1; 23 24 let OutOperandList = (outs); 25 let InOperandList = (ins RegOperand:$bar); 26 27 bits<8> bar; 28 bits<8> Inst = bar; 29} 30 31// CHECK: case ::foo1: { 32// CHECK: op = barEncoder 33// CHECK: op &= UINT64_C(255); 34// CHECK: Value |= op; 35// CHECK: break; 36// CHECK: } 37 38 39// Also check that it works from a complex operand. 40 41def RegPair : Operand<i32> { 42 let MIOperandInfo = (ops RegOperand, RegOperand); 43} 44 45def foo2 : Instruction { 46 let Size = 1; 47 48 let OutOperandList = (outs); 49 let InOperandList = (ins (RegPair $r1, $r2):$r12); 50 51 bits<4> r1; 52 bits<4> r2; 53 bits<8> Inst; 54 let Inst{3-0} = r1; 55 let Inst{7-4} = r2; 56} 57 58// CHECK: case ::foo2: { 59// CHECK: op = barEncoder 60// CHECK: op &= UINT64_C(15); 61// CHECK: Value |= op; 62// CHECK: op = barEncoder 63// CHECK: op &= UINT64_C(15); 64// CHECK: Value |= op; 65// CHECK: break; 66// CHECK: } 67