xref: /llvm-project/llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir (revision d24a2fd38e42f58d6f34f3e985d9387139c12478)
1# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
2
3---
4name: invalid_reg_sequence
5tracksRegLiveness: true
6body:             |
7  bb.0:
8    %0:vgpr_32 = IMPLICIT_DEF
9    %1:vgpr_32 = IMPLICIT_DEF
10
11    ; No operands
12    ; CHECK: *** Bad machine code: Too few operands ***
13    REG_SEQUENCE
14
15    ; Only dest operand
16    ; CHECK: *** Bad machine code: Too few operands ***
17    %2:vreg_64 = REG_SEQUENCE
18
19    ; Missing destination
20    ; CHECK: *** Bad machine code: Explicit definition marked as use ***
21    REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
22
23    ; Missing subreg operand
24    ; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE ***
25    %3:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1
26
27    ; Missing register operand
28    ; CHECK: *** Bad machine code: Invalid number of operands for REG_SEQUENCE ***
29    %4:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %subreg.sub1
30
31    ; Physreg destination
32    ; CHECK: *** Bad machine code: REG_SEQUENCE does not support physical register results ***
33    $vgpr0_vgpr1 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
34
35    ; Subreg in destination
36    ; CHECK: *** Bad machine code: Invalid subreg result for REG_SEQUENCE ***
37    %5.sub0_sub1:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
38
39    ; All operands are registers
40    ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
41    %6:vreg_64 = REG_SEQUENCE %0, %1
42
43    ; Register and subreg index operand order swapped
44    ; CHECK: *** Bad machine code: Invalid register operand for REG_SEQUENCE ***
45    ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
46    %7:vreg_64 = REG_SEQUENCE %subreg.sub0, %0, %subreg.sub1, %1
47
48    ; Invalid subreg index constants
49    ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
50    ; CHECK: - instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.99999
51    ; CHECK-NEXT: operand 2:   0
52
53    ; CHECK: *** Bad machine code: Invalid subregister index operand for REG_SEQUENCE ***
54    ; CHECK: instruction: %8:vreg_64 = REG_SEQUENCE %0:vgpr_32, %subreg.0, %1:vgpr_32, %subreg.99999
55    ; CHECK-NEXT: operand 4:   99999
56    %8:vreg_64 = REG_SEQUENCE %0, 0, %1, 99999
57
58...
59