1# RUN: llvm-mc %s -triple=riscv64 -mattr=+zdinx,+zhinx -M no-aliases \ 2# RUN: | FileCheck -check-prefixes=CHECK-INST %s 3# RUN: llvm-mc %s -triple=riscv64 -mattr=+zdinx,+zhinx \ 4# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s 5# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zdinx,+zhinx < %s \ 6# RUN: | llvm-objdump -M no-aliases --mattr=+zdinx,+zhinx -d -r - \ 7# RUN: | FileCheck -check-prefixes=CHECK-INST %s 8# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zdinx,+zhinx < %s \ 9# RUN: | llvm-objdump --mattr=+zdinx,+zhinx -d -r - \ 10# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s 11 12# This test aims to check what the default rounding mode is for a given 13# instruction if it's not specified, and ensures that it isn't printed when 14# aliases are enabled but is printed otherwise. Instructions aren't listed 15# exhaustively, but special attention is given to the fcvt instructions given 16# that those that never round often default to frm=0b000 for historical 17# reasons. 18# 19# These test cases are copied from fp-default-round-mode.s, but changed to use 20# GPRs. 21 22# Zfinx instructions 23 24# CHECK-INST: fmadd.s a0, a1, a2, a3, dyn{{$}} 25# CHECK-ALIAS: fmadd.s a0, a1, a2, a3{{$}} 26fmadd.s a0, a1, a2, a3 27 28# CHECK-INST: fadd.s a0, a1, a2, dyn{{$}} 29# CHECK-ALIAS: fadd.s a0, a1, a2{{$}} 30fadd.s a0, a1, a2 31 32# CHECK-INST: fcvt.w.s a0, a0, dyn{{$}} 33# CHECK-ALIAS: fcvt.w.s a0, a0{{$}} 34fcvt.w.s a0, a0 35 36# CHECK-INST: fcvt.wu.s a0, a0, dyn{{$}} 37# CHECK-ALIAS: fcvt.wu.s a0, a0{{$}} 38fcvt.wu.s a0, a0 39 40# CHECK-INST: fcvt.s.w a0, a0, dyn{{$}} 41# CHECK-ALIAS: fcvt.s.w a0, a0{{$}} 42fcvt.s.w a0, a0 43 44# CHECK-INST: fcvt.s.wu a0, a0, dyn{{$}} 45# CHECK-ALIAS: fcvt.s.wu a0, a0{{$}} 46fcvt.s.wu a0, a0 47 48# CHECK-INST: fcvt.l.s a0, a0, dyn{{$}} 49# CHECK-ALIAS: fcvt.l.s a0, a0{{$}} 50fcvt.l.s a0, a0 51 52# CHECK-INST: fcvt.lu.s a0, a0, dyn{{$}} 53# CHECK-ALIAS: fcvt.lu.s a0, a0{{$}} 54fcvt.lu.s a0, a0 55 56# CHECK-INST: fcvt.s.l a0, a0, dyn{{$}} 57# CHECK-ALIAS: fcvt.s.l a0, a0{{$}} 58fcvt.s.l a0, a0 59 60# CHECK-INST: fcvt.s.lu a0, a0, dyn{{$}} 61# CHECK-ALIAS: fcvt.s.lu a0, a0{{$}} 62fcvt.s.lu a0, a0 63 64# Zdinx instructions 65 66# CHECK-INST: fmadd.d a0, a1, a2, a3, dyn{{$}} 67# CHECK-ALIAS: fmadd.d a0, a1, a2, a3{{$}} 68fmadd.d a0, a1, a2, a3 69 70# CHECK-INST: fadd.d a0, a1, a2, dyn{{$}} 71# CHECK-ALIAS: fadd.d a0, a1, a2{{$}} 72fadd.d a0, a1, a2 73 74# CHECK-INST: fcvt.s.d a0, a0, dyn{{$}} 75# CHECK-ALIAS: fcvt.s.d a0, a0{{$}} 76fcvt.s.d a0, a0 77 78# For historical reasons defaults to frm==0b000 (rne) but doesn't print this 79# default rounding mode. 80# CHECK-INST: fcvt.d.s a0, a0{{$}} 81# CHECK-ALIAS: fcvt.d.s a0, a0{{$}} 82fcvt.d.s a0, a0 83# CHECK-INST: fcvt.d.s a0, a0{{$}} 84# CHECK-ALIAS: fcvt.d.s a0, a0{{$}} 85fcvt.d.s a0, a0, rne 86 87# CHECK-INST: fcvt.w.d a0, a0, dyn{{$}} 88# CHECK-ALIAS: fcvt.w.d a0, a0{{$}} 89fcvt.w.d a0, a0 90 91# CHECK-INST: fcvt.wu.d a0, a0, dyn{{$}} 92# CHECK-ALIAS: fcvt.wu.d a0, a0{{$}} 93fcvt.wu.d a0, a0 94 95# For historical reasons defaults to frm==0b000 (rne) but doesn't print this 96# default rounding mode. 97# CHECK-INST: fcvt.d.w a0, a0{{$}} 98# CHECK-ALIAS: fcvt.d.w a0, a0{{$}} 99fcvt.d.w a0, a0 100# CHECK-INST: fcvt.d.w a0, a0{{$}} 101# CHECK-ALIAS: fcvt.d.w a0, a0{{$}} 102fcvt.d.w a0, a0, rne 103 104# For historical reasons defaults to frm==0b000 (rne) but doesn't print this 105# default rounding mode. 106# CHECK-INST: fcvt.d.wu a0, a0{{$}} 107# CHECK-ALIAS: fcvt.d.wu a0, a0{{$}} 108fcvt.d.wu a0, a0 109# CHECK-INST: fcvt.d.wu a0, a0{{$}} 110# CHECK-ALIAS: fcvt.d.wu a0, a0{{$}} 111fcvt.d.wu a0, a0, rne 112 113# CHECK-INST: fcvt.l.d a0, a0, dyn{{$}} 114# CHECK-ALIAS: fcvt.l.d a0, a0{{$}} 115fcvt.l.d a0, a0 116 117# CHECK-INST: fcvt.lu.d a0, a0, dyn{{$}} 118# CHECK-ALIAS: fcvt.lu.d a0, a0{{$}} 119fcvt.lu.d a0, a0 120 121# CHECK-INST: fcvt.d.l a0, a0, dyn{{$}} 122# CHECK-ALIAS: fcvt.d.l a0, a0{{$}} 123fcvt.d.l a0, a0 124 125# CHECK-INST: fcvt.d.lu a0, a0, dyn{{$}} 126# CHECK-ALIAS: fcvt.d.lu a0, a0{{$}} 127fcvt.d.lu a0, a0 128 129# Zhinx instructions 130 131# CHECK-INST: fmadd.h a0, a1, a2, a3, dyn{{$}} 132# CHECK-ALIAS: fmadd.h a0, a1, a2, a3{{$}} 133fmadd.h a0, a1, a2, a3 134 135# CHECK-INST: fadd.h a0, a1, a2, dyn{{$}} 136# CHECK-ALIAS: fadd.h a0, a1, a2{{$}} 137fadd.h a0, a1, a2 138 139# For historical reasons defaults to frm==0b000 (rne) but doesn't print this 140# default rounding mode. 141# CHECK-INST: fcvt.s.h a0, a0{{$}} 142# CHECK-ALIAS: fcvt.s.h a0, a0{{$}} 143fcvt.s.h a0, a0 144# CHECK-INST: fcvt.s.h a0, a0{{$}} 145# CHECK-ALIAS: fcvt.s.h a0, a0{{$}} 146fcvt.s.h a0, a0, rne 147 148# CHECK-INST: fcvt.h.s a0, a0, dyn{{$}} 149# CHECK-ALIAS: fcvt.h.s a0, a0{{$}} 150fcvt.h.s a0, a0 151 152# For historical reasons defaults to frm==0b000 (rne) but doesn't print this 153# default rounding mode. 154# CHECK-INST: fcvt.d.h a0, a0{{$}} 155# CHECK-ALIAS: fcvt.d.h a0, a0{{$}} 156fcvt.d.h a0, a0 157# CHECK-INST: fcvt.d.h a0, a0{{$}} 158# CHECK-ALIAS: fcvt.d.h a0, a0{{$}} 159fcvt.d.h a0, a0, rne 160 161# CHECK-INST: fcvt.h.d a0, a0, dyn{{$}} 162# CHECK-ALIAS: fcvt.h.d a0, a0{{$}} 163fcvt.h.d a0, a0 164 165# CHECK-INST: fcvt.w.h a0, a0, dyn{{$}} 166# CHECK-ALIAS: fcvt.w.h a0, a0{{$}} 167fcvt.w.h a0, a0 168 169# CHECK-INST: fcvt.wu.h a0, a0, dyn{{$}} 170# CHECK-ALIAS: fcvt.wu.h a0, a0{{$}} 171fcvt.wu.h a0, a0 172 173# CHECK-INST: fcvt.h.w a0, a0, dyn{{$}} 174# CHECK-ALIAS: fcvt.h.w a0, a0{{$}} 175fcvt.h.w a0, a0 176 177# CHECK-INST: fcvt.h.wu a0, a0, dyn{{$}} 178# CHECK-ALIAS: fcvt.h.wu a0, a0{{$}} 179fcvt.h.wu a0, a0 180 181# CHECK-INST: fcvt.l.h a0, a0, dyn{{$}} 182# CHECK-ALIAS: fcvt.l.h a0, a0{{$}} 183fcvt.l.h a0, a0 184 185# CHECK-INST: fcvt.lu.h a0, a0, dyn{{$}} 186# CHECK-ALIAS: fcvt.lu.h a0, a0{{$}} 187fcvt.lu.h a0, a0 188 189# CHECK-INST: fcvt.h.l a0, a0, dyn{{$}} 190# CHECK-ALIAS: fcvt.h.l a0, a0{{$}} 191fcvt.h.l a0, a0 192 193# CHECK-INST: fcvt.h.lu a0, a0, dyn{{$}} 194# CHECK-ALIAS: fcvt.h.lu a0, a0{{$}} 195fcvt.h.lu a0, a0 196