1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s 4 5define i32 @lshl(i32 %x, i32 %y) nounwind { 6; CHECK-LABEL: lshl: 7; CHECK: ssl a3 8; CHECK-NEXT: sll a2, a2 9; CHECK-NEXT: ret 10 %c = shl i32 %x, %y 11 ret i32 %c 12} 13 14define i32 @lshl_imm_1(i32 %x) nounwind { 15; CHECK-LABEL: lshl_imm_1: 16; CHECK: slli a2, a2, 1 17; CHECK-NEXT: ret 18 %c = shl i32 %x, 1 19 ret i32 %c 20} 21 22define i32 @lshl_imm_10(i32 %x) nounwind { 23; CHECK-LABEL: lshl_imm_10: 24; CHECK: slli a2, a2, 10 25; CHECK-NEXT: ret 26 %c = shl i32 %x, 10 27 ret i32 %c 28} 29 30define i32 @lshl_imm_31(i32 %x) nounwind { 31; CHECK-LABEL: lshl_imm_31: 32; CHECK: slli a2, a2, 31 33; CHECK-NEXT: ret 34 %c = shl i32 %x, 31 35 ret i32 %c 36} 37 38define i32 @lshr(i32 %x, i32 %y) nounwind { 39; CHECK-LABEL: lshr: 40; CHECK: ssr a3 41; CHECK-NEXT: srl a2, a2 42; CHECK-NEXT: ret 43 %c = lshr i32 %x, %y 44 ret i32 %c 45} 46 47define i32 @lshr_imm_1(i32 %x) nounwind { 48; CHECK-LABEL: lshr_imm_1: 49; CHECK: srli a2, a2, 1 50; CHECK-NEXT: ret 51 %c = lshr i32 %x, 1 52 ret i32 %c 53} 54 55define i32 @lshr_imm_15(i32 %x) nounwind { 56; CHECK-LABEL: lshr_imm_15: 57; CHECK: srli a2, a2, 15 58; CHECK-NEXT: ret 59 %c = lshr i32 %x, 15 60 ret i32 %c 61} 62 63define i32 @lshr_imm_20(i32 %x) nounwind { 64; CHECK-LABEL: lshr_imm_20: 65; CHECK: extui a2, a2, 20, 12 66; CHECK-NEXT: ret 67 %c = lshr i32 %x, 20 68 ret i32 %c 69} 70 71define i32 @ashr(i32 %x, i32 %y) nounwind { 72; CHECK-LABEL: ashr: 73; CHECK: ssr a3 74; CHECK-NEXT: sra a2, a2 75; CHECK-NEXT: ret 76 %c = ashr i32 %x, %y 77 ret i32 %c 78} 79 80define i32 @ashr_imm_1(i32 %x) nounwind { 81; CHECK-LABEL: ashr_imm_1: 82; CHECK: srai a2, a2, 1 83; CHECK-NEXT: ret 84 %c = ashr i32 %x, 1 85 ret i32 %c 86} 87 88define i32 @ashr_imm_10(i32 %x) nounwind { 89; CHECK-LABEL: ashr_imm_10: 90; CHECK: srai a2, a2, 10 91; CHECK-NEXT: ret 92 %c = ashr i32 %x, 10 93 ret i32 %c 94} 95 96define i32 @ashr_imm_31(i32 %x) nounwind { 97; CHECK-LABEL: ashr_imm_31: 98; CHECK: srai a2, a2, 31 99; CHECK-NEXT: ret 100 %c = ashr i32 %x, 31 101 ret i32 %c 102} 103 104define i64 @lshl_64(i64 %x, i64 %y) nounwind { 105; CHECK-LABEL: lshl_64: 106; CHECK: ssl a4 107; CHECK-NEXT: src a3, a3, a2 108; CHECK-NEXT: addi a8, a4, -32 109; CHECK-NEXT: ssl a8 110; CHECK-NEXT: sll a10, a2 111; CHECK-NEXT: movi a9, 0 112; CHECK-NEXT: blt a8, a9, .LBB12_2 113; CHECK-NEXT: # %bb.1: 114; CHECK-NEXT: or a3, a10, a10 115; CHECK-NEXT: .LBB12_2: 116; CHECK-NEXT: ssl a4 117; CHECK-NEXT: sll a2, a2 118; CHECK-NEXT: blt a8, a9, .LBB12_4 119; CHECK-NEXT: # %bb.3: 120; CHECK-NEXT: or a2, a9, a9 121; CHECK-NEXT: .LBB12_4: 122; CHECK-NEXT: ret 123 %c = shl i64 %x, %y 124 ret i64 %c 125} 126 127define i64 @lshr_64(i64 %x, i64 %y) nounwind { 128; CHECK-LABEL: lshr_64: 129; CHECK: ssr a4 130; CHECK-NEXT: src a2, a3, a2 131; CHECK-NEXT: addi a8, a4, -32 132; CHECK-NEXT: ssr a8 133; CHECK-NEXT: srl a10, a3 134; CHECK-NEXT: movi a9, 0 135; CHECK-NEXT: blt a8, a9, .LBB13_2 136; CHECK-NEXT: # %bb.1: 137; CHECK-NEXT: or a2, a10, a10 138; CHECK-NEXT: .LBB13_2: 139; CHECK-NEXT: ssr a4 140; CHECK-NEXT: srl a3, a3 141; CHECK-NEXT: blt a8, a9, .LBB13_4 142; CHECK-NEXT: # %bb.3: 143; CHECK-NEXT: or a3, a9, a9 144; CHECK-NEXT: .LBB13_4: 145; CHECK-NEXT: ret 146 %c = lshr i64 %x, %y 147 ret i64 %c 148} 149 150define i64 @ashr_64(i64 %x, i64 %y) nounwind { 151; CHECK-LABEL: ashr_64: 152; CHECK: ssr a4 153; CHECK-NEXT: src a2, a3, a2 154; CHECK-NEXT: addi a9, a4, -32 155; CHECK-NEXT: ssr a9 156; CHECK-NEXT: sra a8, a3 157; CHECK-NEXT: movi a10, 0 158; CHECK-NEXT: blt a9, a10, .LBB14_2 159; CHECK-NEXT: # %bb.1: 160; CHECK-NEXT: or a2, a8, a8 161; CHECK-NEXT: .LBB14_2: 162; CHECK-NEXT: ssr a4 163; CHECK-NEXT: sra a8, a3 164; CHECK-NEXT: blt a9, a10, .LBB14_4 165; CHECK-NEXT: # %bb.3: 166; CHECK-NEXT: srai a8, a3, 31 167; CHECK-NEXT: .LBB14_4: 168; CHECK-NEXT: or a3, a8, a8 169; CHECK-NEXT: ret 170 %c = ashr i64 %x, %y 171 ret i64 %c 172} 173