xref: /llvm-project/llvm/test/CodeGen/Xtensa/select-cc.ll (revision 1e9a296557adbb5168346774c92814497e34524c) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=xtensa -disable-block-placement -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s
4
5define i32 @f_eq(i32 %a, ptr %b) nounwind {
6; CHECK-LABEL: f_eq:
7; CHECK:         l32i a8, a3, 0
8; CHECK-NEXT:    beq a2, a8, .LBB0_2
9; CHECK-NEXT:  # %bb.1:
10; CHECK-NEXT:    or a2, a8, a8
11; CHECK-NEXT:  .LBB0_2:
12; CHECK-NEXT:    ret
13  %val1 = load i32, ptr %b
14  %tst1 = icmp eq i32 %a, %val1
15  %val2 = select i1 %tst1, i32 %a, i32 %val1
16  ret i32 %val2
17}
18
19define i32 @f_ne(i32 %a, ptr %b) nounwind {
20; CHECK-LABEL: f_ne:
21; CHECK:         l32i a8, a3, 0
22; CHECK-NEXT:    bne a2, a8, .LBB1_2
23; CHECK-NEXT:  # %bb.1:
24; CHECK-NEXT:    or a2, a8, a8
25; CHECK-NEXT:  .LBB1_2:
26; CHECK-NEXT:    ret
27  %val1 = load i32, ptr %b
28  %tst1 = icmp ne i32 %a, %val1
29  %val2 = select i1 %tst1, i32 %a, i32 %val1
30  ret i32 %val2
31}
32
33define i32 @f_ugt(i32 %a, ptr %b) nounwind {
34; CHECK-LABEL: f_ugt:
35; CHECK:         or a8, a2, a2
36; CHECK-NEXT:    l32i a2, a3, 0
37; CHECK-NEXT:    bgeu a2, a8, .LBB2_2
38; CHECK-NEXT:  # %bb.1:
39; CHECK-NEXT:    or a2, a8, a8
40; CHECK-NEXT:  .LBB2_2:
41; CHECK-NEXT:    ret
42  %val1 = load i32, ptr %b
43  %tst1 = icmp ugt i32 %a, %val1
44  %val2 = select i1 %tst1, i32 %a, i32 %val1
45  ret i32 %val2
46}
47
48define i32 @f_uge(i32 %a, ptr %b) nounwind {
49; CHECK-LABEL: f_uge:
50; CHECK:         l32i a8, a3, 0
51; CHECK-NEXT:    bgeu a2, a8, .LBB3_2
52; CHECK-NEXT:  # %bb.1:
53; CHECK-NEXT:    or a2, a8, a8
54; CHECK-NEXT:  .LBB3_2:
55; CHECK-NEXT:    ret
56  %val1 = load i32, ptr %b
57  %tst1 = icmp uge i32 %a, %val1
58  %val2 = select i1 %tst1, i32 %a, i32 %val1
59  ret i32 %val2
60}
61
62define i32 @f_ult(i32 %a, ptr %b) nounwind {
63; CHECK-LABEL: f_ult:
64; CHECK:         l32i a8, a3, 0
65; CHECK-NEXT:    bltu a2, a8, .LBB4_2
66; CHECK-NEXT:  # %bb.1:
67; CHECK-NEXT:    or a2, a8, a8
68; CHECK-NEXT:  .LBB4_2:
69; CHECK-NEXT:    ret
70  %val1 = load i32, ptr %b
71  %tst1 = icmp ult i32 %a, %val1
72  %val2 = select i1 %tst1, i32 %a, i32 %val1
73  ret i32 %val2
74}
75
76define i32 @f_ule(i32 %a, ptr %b) nounwind {
77; CHECK-LABEL: f_ule:
78; CHECK:         or a8, a2, a2
79; CHECK-NEXT:    l32i a2, a3, 0
80; CHECK-NEXT:    bltu a2, a8, .LBB5_2
81; CHECK-NEXT:  # %bb.1:
82; CHECK-NEXT:    or a2, a8, a8
83; CHECK-NEXT:  .LBB5_2:
84; CHECK-NEXT:    ret
85  %val1 = load i32, ptr %b
86  %tst1 = icmp ule i32 %a, %val1
87  %val2 = select i1 %tst1, i32 %a, i32 %val1
88  ret i32 %val2
89}
90
91define i32 @f_sgt(i32 %a, ptr %b) nounwind {
92; CHECK-LABEL: f_sgt:
93; CHECK:         or a8, a2, a2
94; CHECK-NEXT:    l32i a2, a3, 0
95; CHECK-NEXT:    bge a2, a8, .LBB6_2
96; CHECK-NEXT:  # %bb.1:
97; CHECK-NEXT:    or a2, a8, a8
98; CHECK-NEXT:  .LBB6_2:
99; CHECK-NEXT:    ret
100  %val1 = load i32, ptr %b
101  %tst1 = icmp sgt i32 %a, %val1
102  %val2 = select i1 %tst1, i32 %a, i32 %val1
103  ret i32 %val2
104}
105
106define i32 @f_sge(i32 %a, ptr %b) nounwind {
107; CHECK-LABEL: f_sge:
108; CHECK:         l32i a8, a3, 0
109; CHECK-NEXT:    bge a2, a8, .LBB7_2
110; CHECK-NEXT:  # %bb.1:
111; CHECK-NEXT:    or a2, a8, a8
112; CHECK-NEXT:  .LBB7_2:
113; CHECK-NEXT:    ret
114  %val1 = load i32, ptr %b
115  %tst1 = icmp sge i32 %a, %val1
116  %val2 = select i1 %tst1, i32 %a, i32 %val1
117  ret i32 %val2
118}
119
120define i32 @f_slt(i32 %a, ptr %b) nounwind {
121; CHECK-LABEL: f_slt:
122; CHECK:         l32i a8, a3, 0
123; CHECK-NEXT:    blt a2, a8, .LBB8_2
124; CHECK-NEXT:  # %bb.1:
125; CHECK-NEXT:    or a2, a8, a8
126; CHECK-NEXT:  .LBB8_2:
127; CHECK-NEXT:    ret
128  %val1 = load i32, ptr %b
129  %tst1 = icmp slt i32 %a, %val1
130  %val2 = select i1 %tst1, i32 %a, i32 %val1
131  ret i32 %val2
132}
133
134define i32 @f_sle(i32 %a, ptr %b) nounwind {
135; CHECK-LABEL: f_sle:
136; CHECK:         or a8, a2, a2
137; CHECK-NEXT:    l32i a2, a3, 0
138; CHECK-NEXT:    blt a2, a8, .LBB9_2
139; CHECK-NEXT:  # %bb.1:
140; CHECK-NEXT:    or a2, a8, a8
141; CHECK-NEXT:  .LBB9_2:
142; CHECK-NEXT:    ret
143  %val1 = load i32, ptr %b
144  %tst1 = icmp sle i32 %a, %val1
145  %val2 = select i1 %tst1, i32 %a, i32 %val1
146  ret i32 %val2
147}
148
149define i32 @f_slt_imm(i32 %a, ptr %b) nounwind {
150; CHECK-LABEL: f_slt_imm:
151; CHECK:         movi a8, 1
152; CHECK-NEXT:    blt a2, a8, .LBB10_2
153; CHECK-NEXT:  # %bb.1:
154; CHECK-NEXT:    l32i a2, a3, 0
155; CHECK-NEXT:  .LBB10_2:
156; CHECK-NEXT:    ret
157  %val1 = load i32, ptr %b
158  %tst1 = icmp slt i32 %a, 1
159  %val2 = select i1 %tst1, i32 %a, i32 %val1
160  ret i32 %val2
161}
162
163define i32 @f_sgt_imm(i32 %a, ptr %b) nounwind {
164; CHECK-LABEL: f_sgt_imm:
165; CHECK:         movi a8, -1
166; CHECK-NEXT:    blt a8, a2, .LBB11_2
167; CHECK-NEXT:  # %bb.1:
168; CHECK-NEXT:    l32i a2, a3, 0
169; CHECK-NEXT:  .LBB11_2:
170; CHECK-NEXT:    ret
171  %val1 = load i32, ptr %b
172  %tst1 = icmp sgt i32 %a, -1
173  %val2 = select i1 %tst1, i32 %a, i32 %val1
174  ret i32 %val2
175}
176
177define i32 @f_ult_imm(i32 %a, ptr %b) nounwind {
178; CHECK-LABEL: f_ult_imm:
179; CHECK:         movi a8, 1024
180; CHECK-NEXT:    bltu a2, a8, .LBB12_2
181; CHECK-NEXT:  # %bb.1:
182; CHECK-NEXT:    l32i a2, a3, 0
183; CHECK-NEXT:  .LBB12_2:
184; CHECK-NEXT:    ret
185  %val1 = load i32, ptr %b
186  %tst1 = icmp ult i32 %a, 1024
187  %val2 = select i1 %tst1, i32 %a, i32 %val1
188  ret i32 %val2
189}
190
191; Tests for i64 operands
192
193define i64 @f_eq_i64(i64 %a, ptr %b) nounwind {
194; CHECK-LABEL: f_eq_i64:
195; CHECK:         l32i a8, a4, 4
196; CHECK-NEXT:    xor a9, a3, a8
197; CHECK-NEXT:    l32i a11, a4, 0
198; CHECK-NEXT:    xor a10, a2, a11
199; CHECK-NEXT:    or a9, a10, a9
200; CHECK-NEXT:    movi a10, 0
201; CHECK-NEXT:    beq a9, a10, .LBB13_2
202; CHECK-NEXT:  # %bb.1:
203; CHECK-NEXT:    or a2, a11, a11
204; CHECK-NEXT:  .LBB13_2:
205; CHECK-NEXT:    beq a9, a10, .LBB13_4
206; CHECK-NEXT:  # %bb.3:
207; CHECK-NEXT:    or a3, a8, a8
208; CHECK-NEXT:  .LBB13_4:
209; CHECK-NEXT:    ret
210  %val1 = load i64, ptr %b
211  %tst1 = icmp eq i64 %a, %val1
212  %val2 = select i1 %tst1, i64 %a, i64 %val1
213  ret i64 %val2
214}
215
216define i64 @f_ne_i64(i64 %a, ptr %b) nounwind {
217; CHECK-LABEL: f_ne_i64:
218; CHECK:         l32i a8, a4, 4
219; CHECK-NEXT:    xor a9, a3, a8
220; CHECK-NEXT:    l32i a11, a4, 0
221; CHECK-NEXT:    xor a10, a2, a11
222; CHECK-NEXT:    or a9, a10, a9
223; CHECK-NEXT:    movi a10, 0
224; CHECK-NEXT:    bne a9, a10, .LBB14_2
225; CHECK-NEXT:  # %bb.1:
226; CHECK-NEXT:    or a2, a11, a11
227; CHECK-NEXT:  .LBB14_2:
228; CHECK-NEXT:    bne a9, a10, .LBB14_4
229; CHECK-NEXT:  # %bb.3:
230; CHECK-NEXT:    or a3, a8, a8
231; CHECK-NEXT:  .LBB14_4:
232; CHECK-NEXT:    ret
233  %val1 = load i64, ptr %b
234  %tst1 = icmp ne i64 %a, %val1
235  %val2 = select i1 %tst1, i64 %a, i64 %val1
236  ret i64 %val2
237}
238
239define i64 @f_ugt_i64(i64 %a, ptr %b) nounwind {
240; CHECK-LABEL: f_ugt_i64:
241; CHECK:         l32i a8, a4, 4
242; CHECK-NEXT:    movi a9, 0
243; CHECK-NEXT:    movi a10, 1
244; CHECK-NEXT:    or a7, a10, a10
245; CHECK-NEXT:    bltu a8, a3, .LBB15_2
246; CHECK-NEXT:  # %bb.1:
247; CHECK-NEXT:    or a7, a9, a9
248; CHECK-NEXT:  .LBB15_2:
249; CHECK-NEXT:    l32i a11, a4, 0
250; CHECK-NEXT:    bltu a11, a2, .LBB15_4
251; CHECK-NEXT:  # %bb.3:
252; CHECK-NEXT:    or a10, a9, a9
253; CHECK-NEXT:  .LBB15_4:
254; CHECK-NEXT:    beq a3, a8, .LBB15_6
255; CHECK-NEXT:  # %bb.5:
256; CHECK-NEXT:    or a10, a7, a7
257; CHECK-NEXT:  .LBB15_6:
258; CHECK-NEXT:    bne a10, a9, .LBB15_8
259; CHECK-NEXT:  # %bb.7:
260; CHECK-NEXT:    or a2, a11, a11
261; CHECK-NEXT:  .LBB15_8:
262; CHECK-NEXT:    bne a10, a9, .LBB15_10
263; CHECK-NEXT:  # %bb.9:
264; CHECK-NEXT:    or a3, a8, a8
265; CHECK-NEXT:  .LBB15_10:
266; CHECK-NEXT:    ret
267  %val1 = load i64, ptr %b
268  %tst1 = icmp ugt i64 %a, %val1
269  %val2 = select i1 %tst1, i64 %a, i64 %val1
270  ret i64 %val2
271}
272
273define i64 @f_uge_i64(i64 %a, ptr %b) nounwind {
274; CHECK-LABEL: f_uge_i64:
275; CHECK:         l32i a8, a4, 4
276; CHECK-NEXT:    movi a9, 0
277; CHECK-NEXT:    movi a10, 1
278; CHECK-NEXT:    or a7, a10, a10
279; CHECK-NEXT:    bgeu a3, a8, .LBB16_2
280; CHECK-NEXT:  # %bb.1:
281; CHECK-NEXT:    or a7, a9, a9
282; CHECK-NEXT:  .LBB16_2:
283; CHECK-NEXT:    l32i a11, a4, 0
284; CHECK-NEXT:    bgeu a2, a11, .LBB16_4
285; CHECK-NEXT:  # %bb.3:
286; CHECK-NEXT:    or a10, a9, a9
287; CHECK-NEXT:  .LBB16_4:
288; CHECK-NEXT:    beq a3, a8, .LBB16_6
289; CHECK-NEXT:  # %bb.5:
290; CHECK-NEXT:    or a10, a7, a7
291; CHECK-NEXT:  .LBB16_6:
292; CHECK-NEXT:    bne a10, a9, .LBB16_8
293; CHECK-NEXT:  # %bb.7:
294; CHECK-NEXT:    or a2, a11, a11
295; CHECK-NEXT:  .LBB16_8:
296; CHECK-NEXT:    bne a10, a9, .LBB16_10
297; CHECK-NEXT:  # %bb.9:
298; CHECK-NEXT:    or a3, a8, a8
299; CHECK-NEXT:  .LBB16_10:
300; CHECK-NEXT:    ret
301  %val1 = load i64, ptr %b
302  %tst1 = icmp uge i64 %a, %val1
303  %val2 = select i1 %tst1, i64 %a, i64 %val1
304  ret i64 %val2
305}
306
307define i64 @f_ult_i64(i64 %a, ptr %b) nounwind {
308; CHECK-LABEL: f_ult_i64:
309; CHECK:         l32i a8, a4, 4
310; CHECK-NEXT:    movi a9, 0
311; CHECK-NEXT:    movi a10, 1
312; CHECK-NEXT:    or a7, a10, a10
313; CHECK-NEXT:    bltu a3, a8, .LBB17_2
314; CHECK-NEXT:  # %bb.1:
315; CHECK-NEXT:    or a7, a9, a9
316; CHECK-NEXT:  .LBB17_2:
317; CHECK-NEXT:    l32i a11, a4, 0
318; CHECK-NEXT:    bltu a2, a11, .LBB17_4
319; CHECK-NEXT:  # %bb.3:
320; CHECK-NEXT:    or a10, a9, a9
321; CHECK-NEXT:  .LBB17_4:
322; CHECK-NEXT:    beq a3, a8, .LBB17_6
323; CHECK-NEXT:  # %bb.5:
324; CHECK-NEXT:    or a10, a7, a7
325; CHECK-NEXT:  .LBB17_6:
326; CHECK-NEXT:    bne a10, a9, .LBB17_8
327; CHECK-NEXT:  # %bb.7:
328; CHECK-NEXT:    or a2, a11, a11
329; CHECK-NEXT:  .LBB17_8:
330; CHECK-NEXT:    bne a10, a9, .LBB17_10
331; CHECK-NEXT:  # %bb.9:
332; CHECK-NEXT:    or a3, a8, a8
333; CHECK-NEXT:  .LBB17_10:
334; CHECK-NEXT:    ret
335  %val1 = load i64, ptr %b
336  %tst1 = icmp ult i64 %a, %val1
337  %val2 = select i1 %tst1, i64 %a, i64 %val1
338  ret i64 %val2
339}
340
341define i64 @f_ule_i64(i64 %a, ptr %b) nounwind {
342; CHECK-LABEL: f_ule_i64:
343; CHECK:         l32i a8, a4, 4
344; CHECK-NEXT:    movi a9, 0
345; CHECK-NEXT:    movi a10, 1
346; CHECK-NEXT:    or a7, a10, a10
347; CHECK-NEXT:    bgeu a8, a3, .LBB18_2
348; CHECK-NEXT:  # %bb.1:
349; CHECK-NEXT:    or a7, a9, a9
350; CHECK-NEXT:  .LBB18_2:
351; CHECK-NEXT:    l32i a11, a4, 0
352; CHECK-NEXT:    bgeu a11, a2, .LBB18_4
353; CHECK-NEXT:  # %bb.3:
354; CHECK-NEXT:    or a10, a9, a9
355; CHECK-NEXT:  .LBB18_4:
356; CHECK-NEXT:    beq a3, a8, .LBB18_6
357; CHECK-NEXT:  # %bb.5:
358; CHECK-NEXT:    or a10, a7, a7
359; CHECK-NEXT:  .LBB18_6:
360; CHECK-NEXT:    bne a10, a9, .LBB18_8
361; CHECK-NEXT:  # %bb.7:
362; CHECK-NEXT:    or a2, a11, a11
363; CHECK-NEXT:  .LBB18_8:
364; CHECK-NEXT:    bne a10, a9, .LBB18_10
365; CHECK-NEXT:  # %bb.9:
366; CHECK-NEXT:    or a3, a8, a8
367; CHECK-NEXT:  .LBB18_10:
368; CHECK-NEXT:    ret
369  %val1 = load i64, ptr %b
370  %tst1 = icmp ule i64 %a, %val1
371  %val2 = select i1 %tst1, i64 %a, i64 %val1
372  ret i64 %val2
373}
374
375define i64 @f_sgt_i64(i64 %a, ptr %b) nounwind {
376; CHECK-LABEL: f_sgt_i64:
377; CHECK:         l32i a8, a4, 4
378; CHECK-NEXT:    movi a9, 0
379; CHECK-NEXT:    movi a10, 1
380; CHECK-NEXT:    or a7, a10, a10
381; CHECK-NEXT:    blt a8, a3, .LBB19_2
382; CHECK-NEXT:  # %bb.1:
383; CHECK-NEXT:    or a7, a9, a9
384; CHECK-NEXT:  .LBB19_2:
385; CHECK-NEXT:    l32i a11, a4, 0
386; CHECK-NEXT:    bltu a11, a2, .LBB19_4
387; CHECK-NEXT:  # %bb.3:
388; CHECK-NEXT:    or a10, a9, a9
389; CHECK-NEXT:  .LBB19_4:
390; CHECK-NEXT:    beq a3, a8, .LBB19_6
391; CHECK-NEXT:  # %bb.5:
392; CHECK-NEXT:    or a10, a7, a7
393; CHECK-NEXT:  .LBB19_6:
394; CHECK-NEXT:    bne a10, a9, .LBB19_8
395; CHECK-NEXT:  # %bb.7:
396; CHECK-NEXT:    or a2, a11, a11
397; CHECK-NEXT:  .LBB19_8:
398; CHECK-NEXT:    bne a10, a9, .LBB19_10
399; CHECK-NEXT:  # %bb.9:
400; CHECK-NEXT:    or a3, a8, a8
401; CHECK-NEXT:  .LBB19_10:
402; CHECK-NEXT:    ret
403  %val1 = load i64, ptr %b
404  %tst1 = icmp sgt i64 %a, %val1
405  %val2 = select i1 %tst1, i64 %a, i64 %val1
406  ret i64 %val2
407}
408
409define i64 @f_sge_i64(i64 %a, ptr %b) nounwind {
410; CHECK-LABEL: f_sge_i64:
411; CHECK:         l32i a8, a4, 4
412; CHECK-NEXT:    movi a9, 0
413; CHECK-NEXT:    movi a10, 1
414; CHECK-NEXT:    or a7, a10, a10
415; CHECK-NEXT:    bge a3, a8, .LBB20_2
416; CHECK-NEXT:  # %bb.1:
417; CHECK-NEXT:    or a7, a9, a9
418; CHECK-NEXT:  .LBB20_2:
419; CHECK-NEXT:    l32i a11, a4, 0
420; CHECK-NEXT:    bgeu a2, a11, .LBB20_4
421; CHECK-NEXT:  # %bb.3:
422; CHECK-NEXT:    or a10, a9, a9
423; CHECK-NEXT:  .LBB20_4:
424; CHECK-NEXT:    beq a3, a8, .LBB20_6
425; CHECK-NEXT:  # %bb.5:
426; CHECK-NEXT:    or a10, a7, a7
427; CHECK-NEXT:  .LBB20_6:
428; CHECK-NEXT:    bne a10, a9, .LBB20_8
429; CHECK-NEXT:  # %bb.7:
430; CHECK-NEXT:    or a2, a11, a11
431; CHECK-NEXT:  .LBB20_8:
432; CHECK-NEXT:    bne a10, a9, .LBB20_10
433; CHECK-NEXT:  # %bb.9:
434; CHECK-NEXT:    or a3, a8, a8
435; CHECK-NEXT:  .LBB20_10:
436; CHECK-NEXT:    ret
437  %val1 = load i64, ptr %b
438  %tst1 = icmp sge i64 %a, %val1
439  %val2 = select i1 %tst1, i64 %a, i64 %val1
440  ret i64 %val2
441}
442
443define i64 @f_slt_i64(i64 %a, ptr %b) nounwind {
444; CHECK-LABEL: f_slt_i64:
445; CHECK:         l32i a8, a4, 4
446; CHECK-NEXT:    movi a9, 0
447; CHECK-NEXT:    movi a10, 1
448; CHECK-NEXT:    or a7, a10, a10
449; CHECK-NEXT:    blt a3, a8, .LBB21_2
450; CHECK-NEXT:  # %bb.1:
451; CHECK-NEXT:    or a7, a9, a9
452; CHECK-NEXT:  .LBB21_2:
453; CHECK-NEXT:    l32i a11, a4, 0
454; CHECK-NEXT:    bltu a2, a11, .LBB21_4
455; CHECK-NEXT:  # %bb.3:
456; CHECK-NEXT:    or a10, a9, a9
457; CHECK-NEXT:  .LBB21_4:
458; CHECK-NEXT:    beq a3, a8, .LBB21_6
459; CHECK-NEXT:  # %bb.5:
460; CHECK-NEXT:    or a10, a7, a7
461; CHECK-NEXT:  .LBB21_6:
462; CHECK-NEXT:    bne a10, a9, .LBB21_8
463; CHECK-NEXT:  # %bb.7:
464; CHECK-NEXT:    or a2, a11, a11
465; CHECK-NEXT:  .LBB21_8:
466; CHECK-NEXT:    bne a10, a9, .LBB21_10
467; CHECK-NEXT:  # %bb.9:
468; CHECK-NEXT:    or a3, a8, a8
469; CHECK-NEXT:  .LBB21_10:
470; CHECK-NEXT:    ret
471  %val1 = load i64, ptr %b
472  %tst1 = icmp slt i64 %a, %val1
473  %val2 = select i1 %tst1, i64 %a, i64 %val1
474  ret i64 %val2
475}
476
477define i64 @f_sle_i64(i64 %a, ptr %b) nounwind {
478; CHECK-LABEL: f_sle_i64:
479; CHECK:         l32i a8, a4, 4
480; CHECK-NEXT:    movi a9, 0
481; CHECK-NEXT:    movi a10, 1
482; CHECK-NEXT:    or a7, a10, a10
483; CHECK-NEXT:    bge a8, a3, .LBB22_2
484; CHECK-NEXT:  # %bb.1:
485; CHECK-NEXT:    or a7, a9, a9
486; CHECK-NEXT:  .LBB22_2:
487; CHECK-NEXT:    l32i a11, a4, 0
488; CHECK-NEXT:    bgeu a11, a2, .LBB22_4
489; CHECK-NEXT:  # %bb.3:
490; CHECK-NEXT:    or a10, a9, a9
491; CHECK-NEXT:  .LBB22_4:
492; CHECK-NEXT:    beq a3, a8, .LBB22_6
493; CHECK-NEXT:  # %bb.5:
494; CHECK-NEXT:    or a10, a7, a7
495; CHECK-NEXT:  .LBB22_6:
496; CHECK-NEXT:    bne a10, a9, .LBB22_8
497; CHECK-NEXT:  # %bb.7:
498; CHECK-NEXT:    or a2, a11, a11
499; CHECK-NEXT:  .LBB22_8:
500; CHECK-NEXT:    bne a10, a9, .LBB22_10
501; CHECK-NEXT:  # %bb.9:
502; CHECK-NEXT:    or a3, a8, a8
503; CHECK-NEXT:  .LBB22_10:
504; CHECK-NEXT:    ret
505  %val1 = load i64, ptr %b
506  %tst1 = icmp sle i64 %a, %val1
507  %val2 = select i1 %tst1, i64 %a, i64 %val1
508  ret i64 %val2
509}
510