xref: /llvm-project/llvm/test/CodeGen/Xtensa/load.ll (revision ea625f48ab50b45da39e2a52b4287c908a1c3efc)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc --mtriple=xtensa < %s | FileCheck %s
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4define signext i8 @test_load_i8(ptr %p){
5; CHECK-LABEL: test_load_i8:
6; CHECK:         l8ui a8, a2, 0
7; CHECK-NEXT:    slli a8, a8, 24
8; CHECK-NEXT:    srai a2, a8, 24
9; CHECK-NEXT:    ret
10  %1 = load i8, ptr %p, align 1
11  ret i8 %1
12}
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