1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=xtensa < %s \ 3; RUN: | FileCheck -check-prefix=XTENSA %s 4 5@gi = external global i32 6 7define i32 @constraint_r(i32 %a) { 8; XTENSA-LABEL: constraint_r: 9; XTENSA: l32r a8, .LCPI0_0 10; XTENSA-NEXT: l32i a8, a8, 0 11; XTENSA-NEXT: #APP 12; XTENSA-NEXT: add a2, a2, a8 13; XTENSA-NEXT: #NO_APP 14; XTENSA-NEXT: ret 15 %1 = load i32, ptr @gi 16 %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) 17 ret i32 %2 18} 19 20define i32 @constraint_i(i32 %a) { 21; XTENSA-LABEL: constraint_i: 22; XTENSA: #APP 23; XTENSA-NEXT: addi a2, a2, 113 24; XTENSA-NEXT: #NO_APP 25; XTENSA-NEXT: ret 26 %1 = load i32, ptr @gi 27 %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113) 28 ret i32 %2 29} 30 31define i32 @explicit_register_a3(i32 %a) nounwind { 32; XTENSA-LABEL: explicit_register_a3: 33; XTENSA: or a3, a2, a2 34; XTENSA-NEXT: #APP 35; XTENSA-NEXT: addi a2, a3, 1 36; XTENSA-NEXT: #NO_APP 37; XTENSA-NEXT: ret 38 %1 = tail call i32 asm "addi $0, $1, 1", "=r,{a3}"(i32 %a) 39 ret i32 %1 40} 41