xref: /llvm-project/llvm/test/CodeGen/Xtensa/brcc.ll (revision 1e9a296557adbb5168346774c92814497e34524c) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=xtensa -disable-block-placement -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s
4
5define i32 @brcc_sgt(i32 %a, i32 %b) nounwind {
6; CHECK-LABEL: brcc_sgt:
7; CHECK:         bge a3, a2, .LBB0_2
8; CHECK-NEXT:  # %bb.1: # %t1
9; CHECK-NEXT:    addi a2, a2, 4
10; CHECK-NEXT:    ret
11; CHECK-NEXT:  .LBB0_2: # %t2
12; CHECK-NEXT:    addi a2, a3, 8
13; CHECK-NEXT:    ret
14  %wb = icmp sgt i32 %a, %b
15  br i1 %wb, label %t1, label %t2
16t1:
17  %t1v = add i32 %a, 4
18  br label %exit
19t2:
20  %t2v = add i32 %b, 8
21  br label %exit
22exit:
23  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
24  ret i32 %v
25}
26
27define i32 @brcc_ugt(i32 %a, i32 %b) nounwind {
28; CHECK-LABEL: brcc_ugt:
29; CHECK:         bgeu a3, a2, .LBB1_2
30; CHECK-NEXT:  # %bb.1: # %t1
31; CHECK-NEXT:    addi a2, a2, 4
32; CHECK-NEXT:    ret
33; CHECK-NEXT:  .LBB1_2: # %t2
34; CHECK-NEXT:    addi a2, a3, 8
35; CHECK-NEXT:    ret
36  %wb = icmp ugt i32 %a, %b
37  br i1 %wb, label %t1, label %t2
38t1:
39  %t1v = add i32 %a, 4
40  br label %exit
41t2:
42  %t2v = add i32 %b, 8
43  br label %exit
44exit:
45  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
46  ret i32 %v
47}
48
49define i32 @brcc_sle(i32 %a, i32 %b) nounwind {
50; CHECK-LABEL: brcc_sle:
51; CHECK:         blt a3, a2, .LBB2_2
52; CHECK-NEXT:  # %bb.1: # %t1
53; CHECK-NEXT:    addi a2, a2, 4
54; CHECK-NEXT:    ret
55; CHECK-NEXT:  .LBB2_2: # %t2
56; CHECK-NEXT:    addi a2, a3, 8
57; CHECK-NEXT:    ret
58  %wb = icmp sle i32 %a, %b
59  br i1 %wb, label %t1, label %t2
60t1:
61  %t1v = add i32 %a, 4
62  br label %exit
63t2:
64  %t2v = add i32 %b, 8
65  br label %exit
66exit:
67  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
68  ret i32 %v
69}
70
71define i32 @brcc_ule(i32 %a, i32 %b) nounwind {
72; CHECK-LABEL: brcc_ule:
73; CHECK:         bltu a3, a2, .LBB3_2
74; CHECK-NEXT:  # %bb.1: # %t1
75; CHECK-NEXT:    addi a2, a2, 4
76; CHECK-NEXT:    ret
77; CHECK-NEXT:  .LBB3_2: # %t2
78; CHECK-NEXT:    addi a2, a3, 8
79; CHECK-NEXT:    ret
80  %wb = icmp ule i32 %a, %b
81  br i1 %wb, label %t1, label %t2
82t1:
83  %t1v = add i32 %a, 4
84  br label %exit
85t2:
86  %t2v = add i32 %b, 8
87  br label %exit
88exit:
89  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
90  ret i32 %v
91}
92
93define i32 @brcc_eq(i32 %a, i32 %b) nounwind {
94; CHECK-LABEL: brcc_eq:
95; CHECK:         bne a2, a3, .LBB4_2
96; CHECK-NEXT:  # %bb.1: # %t1
97; CHECK-NEXT:    addi a2, a2, 4
98; CHECK-NEXT:    ret
99; CHECK-NEXT:  .LBB4_2: # %t2
100; CHECK-NEXT:    addi a2, a3, 8
101; CHECK-NEXT:    ret
102  %wb = icmp eq i32 %a, %b
103  br i1 %wb, label %t1, label %t2
104t1:
105  %t1v = add i32 %a, 4
106  br label %exit
107t2:
108  %t2v = add i32 %b, 8
109  br label %exit
110exit:
111  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
112  ret i32 %v
113}
114
115define i32 @brcc_ne(i32 %a, i32 %b) nounwind {
116; CHECK-LABEL: brcc_ne:
117; CHECK:         beq a2, a3, .LBB5_2
118; CHECK-NEXT:  # %bb.1: # %t1
119; CHECK-NEXT:    addi a2, a2, 4
120; CHECK-NEXT:    ret
121; CHECK-NEXT:  .LBB5_2: # %t2
122; CHECK-NEXT:    addi a2, a3, 8
123; CHECK-NEXT:    ret
124  %wb = icmp ne i32 %a, %b
125  br i1 %wb, label %t1, label %t2
126t1:
127  %t1v = add i32 %a, 4
128  br label %exit
129t2:
130  %t2v = add i32 %b, 8
131  br label %exit
132exit:
133  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
134  ret i32 %v
135}
136
137define i32 @brcc_ge(i32 %a, i32 %b) nounwind {
138; CHECK-LABEL: brcc_ge:
139; CHECK:         blt a2, a3, .LBB6_2
140; CHECK-NEXT:  # %bb.1: # %t1
141; CHECK-NEXT:    addi a2, a2, 4
142; CHECK-NEXT:    ret
143; CHECK-NEXT:  .LBB6_2: # %t2
144; CHECK-NEXT:    addi a2, a3, 8
145; CHECK-NEXT:    ret
146  %wb = icmp sge i32 %a, %b
147  br i1 %wb, label %t1, label %t2
148t1:
149  %t1v = add i32 %a, 4
150  br label %exit
151t2:
152  %t2v = add i32 %b, 8
153  br label %exit
154exit:
155  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
156  ret i32 %v
157}
158
159define i32 @brcc_lt(i32 %a, i32 %b) nounwind {
160; CHECK-LABEL: brcc_lt:
161; CHECK:         bge a2, a3, .LBB7_2
162; CHECK-NEXT:  # %bb.1: # %t1
163; CHECK-NEXT:    addi a2, a2, 4
164; CHECK-NEXT:    ret
165; CHECK-NEXT:  .LBB7_2: # %t2
166; CHECK-NEXT:    addi a2, a3, 8
167; CHECK-NEXT:    ret
168  %wb = icmp slt i32 %a, %b
169  br i1 %wb, label %t1, label %t2
170t1:
171  %t1v = add i32 %a, 4
172  br label %exit
173t2:
174  %t2v = add i32 %b, 8
175  br label %exit
176exit:
177  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
178  ret i32 %v
179}
180
181define i32 @brcc_uge(i32 %a, i32 %b) nounwind {
182; CHECK-LABEL: brcc_uge:
183; CHECK:         bltu a2, a3, .LBB8_2
184; CHECK-NEXT:  # %bb.1: # %t1
185; CHECK-NEXT:    addi a2, a2, 4
186; CHECK-NEXT:    ret
187; CHECK-NEXT:  .LBB8_2: # %t2
188; CHECK-NEXT:    addi a2, a3, 8
189; CHECK-NEXT:    ret
190  %wb = icmp uge i32 %a, %b
191  br i1 %wb, label %t1, label %t2
192t1:
193  %t1v = add i32 %a, 4
194  br label %exit
195t2:
196  %t2v = add i32 %b, 8
197  br label %exit
198exit:
199  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
200  ret i32 %v
201}
202
203define i32 @brcc_ult(i32 %a, i32 %b) nounwind {
204; CHECK-LABEL: brcc_ult:
205; CHECK:         bgeu a2, a3, .LBB9_2
206; CHECK-NEXT:  # %bb.1: # %t1
207; CHECK-NEXT:    addi a2, a2, 4
208; CHECK-NEXT:    ret
209; CHECK-NEXT:  .LBB9_2: # %t2
210; CHECK-NEXT:    addi a2, a3, 8
211; CHECK-NEXT:    ret
212  %wb = icmp ult i32 %a, %b
213  br i1 %wb, label %t1, label %t2
214t1:
215  %t1v = add i32 %a, 4
216  br label %exit
217t2:
218  %t2v = add i32 %b, 8
219  br label %exit
220exit:
221  %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
222  ret i32 %v
223}
224