1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s 3 4; Test simplifications of vector compares that should simplify to true, false or equality. 5 6define <4 x i32> @slt_min(<4 x i32> %x) { 7; CHECK-LABEL: slt_min: 8; CHECK: # %bb.0: 9; CHECK-NEXT: xorps %xmm0, %xmm0 10; CHECK-NEXT: retq 11 %cmp = icmp slt <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 12 %r = sext <4 x i1> %cmp to <4 x i32> 13 ret <4 x i32> %r 14} 15 16define <4 x i32> @sge_min(<4 x i32> %x) { 17; CHECK-LABEL: sge_min: 18; CHECK: # %bb.0: 19; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 20; CHECK-NEXT: retq 21 %cmp = icmp sge <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 22 %r = sext <4 x i1> %cmp to <4 x i32> 23 ret <4 x i32> %r 24} 25 26define <4 x i32> @sgt_min(<4 x i32> %x) { 27; CHECK-LABEL: sgt_min: 28; CHECK: # %bb.0: 29; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 30; CHECK-NEXT: retq 31 %cmp = icmp sgt <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 32 %r = sext <4 x i1> %cmp to <4 x i32> 33 ret <4 x i32> %r 34} 35 36define <4 x i32> @sle_min(<4 x i32> %x) { 37; CHECK-LABEL: sle_min: 38; CHECK: # %bb.0: 39; CHECK-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 40; CHECK-NEXT: retq 41 %cmp = icmp sle <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 42 %r = sext <4 x i1> %cmp to <4 x i32> 43 ret <4 x i32> %r 44} 45 46define <4 x i32> @sgt_max(<4 x i32> %x) { 47; CHECK-LABEL: sgt_max: 48; CHECK: # %bb.0: 49; CHECK-NEXT: xorps %xmm0, %xmm0 50; CHECK-NEXT: retq 51 %cmp = icmp sgt <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 52 %r = sext <4 x i1> %cmp to <4 x i32> 53 ret <4 x i32> %r 54} 55 56define <4 x i32> @sle_max(<4 x i32> %x) { 57; CHECK-LABEL: sle_max: 58; CHECK: # %bb.0: 59; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 60; CHECK-NEXT: retq 61 %cmp = icmp sle <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 62 %r = sext <4 x i1> %cmp to <4 x i32> 63 ret <4 x i32> %r 64} 65 66define <4 x i32> @slt_max(<4 x i32> %x) { 67; CHECK-LABEL: slt_max: 68; CHECK: # %bb.0: 69; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647] 70; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 71; CHECK-NEXT: movdqa %xmm1, %xmm0 72; CHECK-NEXT: retq 73 %cmp = icmp slt <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 74 %r = sext <4 x i1> %cmp to <4 x i32> 75 ret <4 x i32> %r 76} 77 78define <4 x i32> @sge_max(<4 x i32> %x) { 79; CHECK-LABEL: sge_max: 80; CHECK: # %bb.0: 81; CHECK-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 82; CHECK-NEXT: retq 83 %cmp = icmp sge <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 84 %r = sext <4 x i1> %cmp to <4 x i32> 85 ret <4 x i32> %r 86} 87 88define <4 x i32> @ult_min(<4 x i32> %x) { 89; CHECK-LABEL: ult_min: 90; CHECK: # %bb.0: 91; CHECK-NEXT: xorps %xmm0, %xmm0 92; CHECK-NEXT: retq 93 %cmp = icmp ult <4 x i32> %x, zeroinitializer 94 %r = sext <4 x i1> %cmp to <4 x i32> 95 ret <4 x i32> %r 96} 97 98define <4 x i32> @uge_min(<4 x i32> %x) { 99; CHECK-LABEL: uge_min: 100; CHECK: # %bb.0: 101; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 102; CHECK-NEXT: retq 103 %cmp = icmp uge <4 x i32> %x, zeroinitializer 104 %r = sext <4 x i1> %cmp to <4 x i32> 105 ret <4 x i32> %r 106} 107 108define <4 x i32> @ugt_min(<4 x i32> %x) { 109; CHECK-LABEL: ugt_min: 110; CHECK: # %bb.0: 111; CHECK-NEXT: pxor %xmm1, %xmm1 112; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 113; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 114; CHECK-NEXT: pxor %xmm1, %xmm0 115; CHECK-NEXT: retq 116 %cmp = icmp ugt <4 x i32> %x, zeroinitializer 117 %r = sext <4 x i1> %cmp to <4 x i32> 118 ret <4 x i32> %r 119} 120 121define <4 x i32> @ule_min(<4 x i32> %x) { 122; CHECK-LABEL: ule_min: 123; CHECK: # %bb.0: 124; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] 125; CHECK-NEXT: pxor %xmm1, %xmm0 126; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 127; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 128; CHECK-NEXT: pxor %xmm1, %xmm0 129; CHECK-NEXT: retq 130 %cmp = icmp ule <4 x i32> %x, zeroinitializer 131 %r = sext <4 x i1> %cmp to <4 x i32> 132 ret <4 x i32> %r 133} 134 135define <4 x i32> @ugt_max(<4 x i32> %x) { 136; CHECK-LABEL: ugt_max: 137; CHECK: # %bb.0: 138; CHECK-NEXT: xorps %xmm0, %xmm0 139; CHECK-NEXT: retq 140 %cmp = icmp ugt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 141 %r = sext <4 x i1> %cmp to <4 x i32> 142 ret <4 x i32> %r 143} 144 145define <4 x i32> @ule_max(<4 x i32> %x) { 146; CHECK-LABEL: ule_max: 147; CHECK: # %bb.0: 148; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 149; CHECK-NEXT: retq 150 %cmp = icmp ule <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 151 %r = sext <4 x i1> %cmp to <4 x i32> 152 ret <4 x i32> %r 153} 154 155define <4 x i32> @ult_max(<4 x i32> %x) { 156; CHECK-LABEL: ult_max: 157; CHECK: # %bb.0: 158; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 159; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 160; CHECK-NEXT: pxor %xmm1, %xmm0 161; CHECK-NEXT: retq 162 %cmp = icmp ult <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 163 %r = sext <4 x i1> %cmp to <4 x i32> 164 ret <4 x i32> %r 165} 166 167define <4 x i32> @uge_max(<4 x i32> %x) { 168; CHECK-LABEL: uge_max: 169; CHECK: # %bb.0: 170; CHECK-NEXT: pcmpeqd %xmm2, %xmm2 171; CHECK-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 172; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647] 173; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 174; CHECK-NEXT: pxor %xmm2, %xmm1 175; CHECK-NEXT: movdqa %xmm1, %xmm0 176; CHECK-NEXT: retq 177 %cmp = icmp uge <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 178 %r = sext <4 x i1> %cmp to <4 x i32> 179 ret <4 x i32> %r 180} 181 182define <4 x i32> @slt_min_plus1(<4 x i32> %x) { 183; CHECK-LABEL: slt_min_plus1: 184; CHECK: # %bb.0: 185; CHECK-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 186; CHECK-NEXT: retq 187 %cmp = icmp slt <4 x i32> %x, <i32 -2147483647, i32 -2147483647, i32 -2147483647, i32 -2147483647> 188 %r = sext <4 x i1> %cmp to <4 x i32> 189 ret <4 x i32> %r 190} 191 192define <4 x i32> @sge_min_plus1(<4 x i32> %x) { 193; CHECK-LABEL: sge_min_plus1: 194; CHECK: # %bb.0: 195; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 196; CHECK-NEXT: retq 197 %cmp = icmp sge <4 x i32> %x, <i32 -2147483647, i32 -2147483647, i32 -2147483647, i32 -2147483647> 198 %r = sext <4 x i1> %cmp to <4 x i32> 199 ret <4 x i32> %r 200} 201 202define <4 x i32> @sgt_max_minus1(<4 x i32> %x) { 203; CHECK-LABEL: sgt_max_minus1: 204; CHECK: # %bb.0: 205; CHECK-NEXT: pcmpeqd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 206; CHECK-NEXT: retq 207 %cmp = icmp sgt <4 x i32> %x, <i32 2147483646, i32 2147483646, i32 2147483646, i32 2147483646> 208 %r = sext <4 x i1> %cmp to <4 x i32> 209 ret <4 x i32> %r 210} 211 212define <4 x i32> @sle_max_minus1(<4 x i32> %x) { 213; CHECK-LABEL: sle_max_minus1: 214; CHECK: # %bb.0: 215; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647] 216; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 217; CHECK-NEXT: movdqa %xmm1, %xmm0 218; CHECK-NEXT: retq 219 %cmp = icmp sle <4 x i32> %x, <i32 2147483646, i32 2147483646, i32 2147483646, i32 2147483646> 220 %r = sext <4 x i1> %cmp to <4 x i32> 221 ret <4 x i32> %r 222} 223 224define <4 x i32> @ult_one(<4 x i32> %x) { 225; CHECK-LABEL: ult_one: 226; CHECK: # %bb.0: 227; CHECK-NEXT: pxor %xmm1, %xmm1 228; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 229; CHECK-NEXT: retq 230 %cmp = icmp ult <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> 231 %r = sext <4 x i1> %cmp to <4 x i32> 232 ret <4 x i32> %r 233} 234 235define <4 x i32> @uge_one(<4 x i32> %x) { 236; CHECK-LABEL: uge_one: 237; CHECK: # %bb.0: 238; CHECK-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 239; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483649,2147483649,2147483649,2147483649] 240; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 241; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 242; CHECK-NEXT: pxor %xmm1, %xmm0 243; CHECK-NEXT: retq 244 %cmp = icmp uge <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1> 245 %r = sext <4 x i1> %cmp to <4 x i32> 246 ret <4 x i32> %r 247} 248 249define <4 x i32> @ugt_max_minus1(<4 x i32> %x) { 250; CHECK-LABEL: ugt_max_minus1: 251; CHECK: # %bb.0: 252; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 253; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 254; CHECK-NEXT: retq 255 %cmp = icmp ugt <4 x i32> %x, <i32 -2, i32 -2, i32 -2, i32 -2> 256 %r = sext <4 x i1> %cmp to <4 x i32> 257 ret <4 x i32> %r 258} 259 260define <4 x i32> @ule_max_minus1(<4 x i32> %x) { 261; CHECK-LABEL: ule_max_minus1: 262; CHECK: # %bb.0: 263; CHECK-NEXT: pxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 264; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 265; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 266; CHECK-NEXT: pxor %xmm1, %xmm0 267; CHECK-NEXT: retq 268 %cmp = icmp ule <4 x i32> %x, <i32 -2, i32 -2, i32 -2, i32 -2> 269 %r = sext <4 x i1> %cmp to <4 x i32> 270 ret <4 x i32> %r 271} 272 273define <4 x i32> @ugt_smax(<4 x i32> %x) { 274; CHECK-LABEL: ugt_smax: 275; CHECK: # %bb.0: 276; CHECK-NEXT: pxor %xmm1, %xmm1 277; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 278; CHECK-NEXT: movdqa %xmm1, %xmm0 279; CHECK-NEXT: retq 280 %cmp = icmp ugt <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 281 %r = sext <4 x i1> %cmp to <4 x i32> 282 ret <4 x i32> %r 283} 284 285define <4 x i32> @ule_smax(<4 x i32> %x) { 286; CHECK-LABEL: ule_smax: 287; CHECK: # %bb.0: 288; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 289; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 290; CHECK-NEXT: retq 291 %cmp = icmp ule <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 292 %r = sext <4 x i1> %cmp to <4 x i32> 293 ret <4 x i32> %r 294} 295 296define <4 x i32> @ult_smin(<4 x i32> %x) { 297; CHECK-LABEL: ult_smin: 298; CHECK: # %bb.0: 299; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 300; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 301; CHECK-NEXT: retq 302 %cmp = icmp ult <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 303 %r = sext <4 x i1> %cmp to <4 x i32> 304 ret <4 x i32> %r 305} 306 307define <4 x i32> @uge_smin(<4 x i32> %x) { 308; CHECK-LABEL: uge_smin: 309; CHECK: # %bb.0: 310; CHECK-NEXT: pxor %xmm1, %xmm1 311; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 312; CHECK-NEXT: movdqa %xmm1, %xmm0 313; CHECK-NEXT: retq 314 %cmp = icmp uge <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 315 %r = sext <4 x i1> %cmp to <4 x i32> 316 ret <4 x i32> %r 317} 318 319; Make sure we can efficiently handle ne smin by turning into sgt. 320define <4 x i32> @ne_smin(<4 x i32> %x) { 321; CHECK-LABEL: ne_smin: 322; CHECK: # %bb.0: 323; CHECK-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 324; CHECK-NEXT: retq 325 %cmp = icmp ne <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 326 %r = sext <4 x i1> %cmp to <4 x i32> 327 ret <4 x i32> %r 328} 329 330; Make sure we can efficiently handle ne smax by turning into sgt. We can't fold 331; the constant pool load, but the alternative is a cmpeq+invert which is 3 instructions. 332; The PCMPGT version is two instructions given sufficient register allocation freedom 333; to avoid the last mov to %xmm0 seen here. 334define <4 x i32> @ne_smax(<4 x i32> %x) { 335; CHECK-LABEL: ne_smax: 336; CHECK: # %bb.0: 337; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647] 338; CHECK-NEXT: pcmpgtd %xmm0, %xmm1 339; CHECK-NEXT: movdqa %xmm1, %xmm0 340; CHECK-NEXT: retq 341 %cmp = icmp ne <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 342 %r = sext <4 x i1> %cmp to <4 x i32> 343 ret <4 x i32> %r 344} 345