1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86 3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64 4 5define i32 @test0(ptr %v4) nounwind { 6; X86-LABEL: test0: 7; X86: # %bb.0: # %entry 8; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 9; X86-NEXT: pshufw $238, (%eax), %mm0 # mm0 = mem[2,3,2,3] 10; X86-NEXT: movd %mm0, %eax 11; X86-NEXT: addl $32, %eax 12; X86-NEXT: retl 13; 14; X64-LABEL: test0: 15; X64: # %bb.0: # %entry 16; X64-NEXT: pshufw $238, (%rdi), %mm0 # mm0 = mem[2,3,2,3] 17; X64-NEXT: movd %mm0, %eax 18; X64-NEXT: addl $32, %eax 19; X64-NEXT: retq 20entry: 21 %v5 = load <1 x i64>, ptr %v4, align 8 22 %v12 = bitcast <1 x i64> %v5 to <4 x i16> 23 %v13 = bitcast <4 x i16> %v12 to <1 x i64> 24 %v14 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %v13, i8 -18) 25 %v15 = bitcast <1 x i64> %v14 to <4 x i16> 26 %v16 = bitcast <4 x i16> %v15 to <1 x i64> 27 %v17 = extractelement <1 x i64> %v16, i32 0 28 %v18 = bitcast i64 %v17 to <2 x i32> 29 %v19 = extractelement <2 x i32> %v18, i32 0 30 %v20 = add i32 %v19, 32 31 ret i32 %v20 32} 33 34define i32 @test1(ptr nocapture readonly %ptr) nounwind { 35; X86-LABEL: test1: 36; X86: # %bb.0: # %entry 37; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 38; X86-NEXT: movd (%eax), %mm0 39; X86-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3] 40; X86-NEXT: movd %mm0, %eax 41; X86-NEXT: emms 42; X86-NEXT: retl 43; 44; X64-LABEL: test1: 45; X64: # %bb.0: # %entry 46; X64-NEXT: movd (%rdi), %mm0 47; X64-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3] 48; X64-NEXT: movd %mm0, %eax 49; X64-NEXT: emms 50; X64-NEXT: retq 51entry: 52 %0 = load i32, ptr %ptr, align 4 53 %1 = insertelement <2 x i32> undef, i32 %0, i32 0 54 %2 = insertelement <2 x i32> %1, i32 0, i32 1 55 %3 = bitcast <2 x i32> %2 to <1 x i64> 56 %4 = bitcast <1 x i64> %3 to i64 57 %5 = bitcast i64 %4 to <4 x i16> 58 %6 = bitcast <4 x i16> %5 to <1 x i64> 59 %7 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %6, i8 -24) 60 %8 = bitcast <1 x i64> %7 to <4 x i16> 61 %9 = bitcast <4 x i16> %8 to <1 x i64> 62 %10 = extractelement <1 x i64> %9, i32 0 63 %11 = bitcast i64 %10 to <2 x i32> 64 %12 = extractelement <2 x i32> %11, i32 0 65 tail call void @llvm.x86.mmx.emms() 66 ret i32 %12 67} 68 69define i32 @test2(ptr nocapture readonly %ptr) nounwind { 70; X86-LABEL: test2: 71; X86: # %bb.0: # %entry 72; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 73; X86-NEXT: pshufw $232, (%eax), %mm0 # mm0 = mem[0,2,2,3] 74; X86-NEXT: movd %mm0, %eax 75; X86-NEXT: emms 76; X86-NEXT: retl 77; 78; X64-LABEL: test2: 79; X64: # %bb.0: # %entry 80; X64-NEXT: pshufw $232, (%rdi), %mm0 # mm0 = mem[0,2,2,3] 81; X64-NEXT: movd %mm0, %eax 82; X64-NEXT: emms 83; X64-NEXT: retq 84entry: 85 %0 = load <1 x i64>, ptr %ptr, align 8 86 %1 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %0, i8 -24) 87 %2 = bitcast <1 x i64> %1 to <4 x i16> 88 %3 = bitcast <4 x i16> %2 to <1 x i64> 89 %4 = extractelement <1 x i64> %3, i32 0 90 %5 = bitcast i64 %4 to <2 x i32> 91 %6 = extractelement <2 x i32> %5, i32 0 92 tail call void @llvm.x86.mmx.emms() 93 ret i32 %6 94} 95 96define i32 @test3(<1 x i64> %a) nounwind { 97; X86-LABEL: test3: 98; X86: # %bb.0: 99; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 100; X86-NEXT: retl 101; 102; X64-LABEL: test3: 103; X64: # %bb.0: 104; X64-NEXT: movq %rdi, %rax 105; X64-NEXT: # kill: def $eax killed $eax killed $rax 106; X64-NEXT: retq 107 %tmp0 = bitcast <1 x i64> %a to <2 x i32> 108 %tmp1 = extractelement <2 x i32> %tmp0, i32 0 109 ret i32 %tmp1 110} 111 112; Verify we don't muck with extractelts from the upper lane. 113define i32 @test4(<1 x i64> %a) nounwind { 114; X86-LABEL: test4: 115; X86: # %bb.0: 116; X86-NEXT: movl {{[0-9]+}}(%esp), %eax 117; X86-NEXT: retl 118; 119; X64-LABEL: test4: 120; X64: # %bb.0: 121; X64-NEXT: movq %rdi, %xmm0 122; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] 123; X64-NEXT: movd %xmm0, %eax 124; X64-NEXT: retq 125 %tmp0 = bitcast <1 x i64> %a to <2 x i32> 126 %tmp1 = extractelement <2 x i32> %tmp0, i32 1 127 ret i32 %tmp1 128} 129 130declare <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64>, i8) 131declare void @llvm.x86.mmx.emms() 132