xref: /llvm-project/llvm/test/CodeGen/X86/tail-opts.ll (revision a4951eca40c070e020aa5d2689c08177fbeb780d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true -disable-cgp-delete-phis | FileCheck %s
3
4declare dso_local void @bar(i32)
5declare dso_local void @car(i32)
6declare dso_local void @dar(i32)
7declare dso_local void @ear(i32)
8declare dso_local void @far(i32)
9declare i1 @qux()
10
11@GHJK = dso_local global i32 0
12@HABC = dso_local global i32 0
13
14; BranchFolding should tail-merge the stores since they all precede
15; direct branches to the same place.
16
17define dso_local void @tail_merge_me() nounwind {
18; CHECK-LABEL: tail_merge_me:
19; CHECK:       # %bb.0: # %entry
20; CHECK-NEXT:    pushq %rax
21; CHECK-NEXT:    callq qux@PLT
22; CHECK-NEXT:    testb $1, %al
23; CHECK-NEXT:    je .LBB0_1
24; CHECK-NEXT:  # %bb.6: # %A
25; CHECK-NEXT:    xorl %edi, %edi
26; CHECK-NEXT:    callq bar
27; CHECK-NEXT:    jmp .LBB0_4
28; CHECK-NEXT:  .LBB0_1: # %next
29; CHECK-NEXT:    callq qux@PLT
30; CHECK-NEXT:    testb $1, %al
31; CHECK-NEXT:    je .LBB0_3
32; CHECK-NEXT:  # %bb.2: # %B
33; CHECK-NEXT:    movl $1, %edi
34; CHECK-NEXT:    callq car
35; CHECK-NEXT:    jmp .LBB0_4
36; CHECK-NEXT:  .LBB0_3: # %C
37; CHECK-NEXT:    movl $2, %edi
38; CHECK-NEXT:    callq dar
39; CHECK-NEXT:  .LBB0_4: # %M
40; CHECK-NEXT:    movl $0, GHJK(%rip)
41; CHECK-NEXT:    movl $1, HABC(%rip)
42; CHECK-NEXT:    callq qux@PLT
43; CHECK-NEXT:    testb $1, %al
44; CHECK-NEXT:    je .LBB0_5
45; CHECK-NEXT:  # %bb.7: # %return
46; CHECK-NEXT:    movl $1000, %edi # imm = 0x3E8
47; CHECK-NEXT:    callq ear
48; CHECK-NEXT:    popq %rax
49; CHECK-NEXT:    retq
50; CHECK-NEXT:  .LBB0_5: # %altret
51; CHECK-NEXT:    movl $1001, %edi # imm = 0x3E9
52; CHECK-NEXT:    callq far
53; CHECK-NEXT:    popq %rax
54; CHECK-NEXT:    retq
55entry:
56  %a = call i1 @qux()
57  br i1 %a, label %A, label %next
58next:
59  %b = call i1 @qux()
60  br i1 %b, label %B, label %C
61
62A:
63  call void @bar(i32 0)
64  store i32 0, ptr @GHJK
65  br label %M
66
67B:
68  call void @car(i32 1)
69  store i32 0, ptr @GHJK
70  br label %M
71
72C:
73  call void @dar(i32 2)
74  store i32 0, ptr @GHJK
75  br label %M
76
77M:
78  store i32 1, ptr @HABC
79  %c = call i1 @qux()
80  br i1 %c, label %return, label %altret
81
82return:
83  call void @ear(i32 1000)
84  ret void
85altret:
86  call void @far(i32 1001)
87  ret void
88}
89
90declare ptr @choose(ptr, ptr)
91
92; BranchFolding should tail-duplicate the indirect jump to avoid
93; redundant branching.
94
95define dso_local void @tail_duplicate_me() nounwind {
96; CHECK-LABEL: tail_duplicate_me:
97; CHECK:       # %bb.0: # %entry
98; CHECK-NEXT:    pushq %rbp
99; CHECK-NEXT:    pushq %rbx
100; CHECK-NEXT:    pushq %rax
101; CHECK-NEXT:    callq qux@PLT
102; CHECK-NEXT:    movl $.Ltmp0, %edi
103; CHECK-NEXT:    movl $.Ltmp1, %esi
104; CHECK-NEXT:    movl %eax, %ebp
105; CHECK-NEXT:    callq choose@PLT
106; CHECK-NEXT:    movq %rax, %rbx
107; CHECK-NEXT:    testb $1, %bpl
108; CHECK-NEXT:    je .LBB1_1
109; CHECK-NEXT:  # %bb.7: # %A
110; CHECK-NEXT:    xorl %edi, %edi
111; CHECK-NEXT:    callq bar
112; CHECK-NEXT:    movl $0, GHJK(%rip)
113; CHECK-NEXT:    jmpq *%rbx
114; CHECK-NEXT:  .Ltmp0: # Block address taken
115; CHECK-NEXT:  .LBB1_4: # %return
116; CHECK-NEXT:    movl $1000, %edi # imm = 0x3E8
117; CHECK-NEXT:    callq ear
118; CHECK-NEXT:    jmp .LBB1_5
119; CHECK-NEXT:  .LBB1_1: # %next
120; CHECK-NEXT:    callq qux@PLT
121; CHECK-NEXT:    testb $1, %al
122; CHECK-NEXT:    je .LBB1_3
123; CHECK-NEXT:  # %bb.2: # %B
124; CHECK-NEXT:    movl $1, %edi
125; CHECK-NEXT:    callq car
126; CHECK-NEXT:    movl $0, GHJK(%rip)
127; CHECK-NEXT:    jmpq *%rbx
128; CHECK-NEXT:  .Ltmp1: # Block address taken
129; CHECK-NEXT:  .LBB1_6: # %altret
130; CHECK-NEXT:    movl $1001, %edi # imm = 0x3E9
131; CHECK-NEXT:    callq far
132; CHECK-NEXT:  .LBB1_5: # %return
133; CHECK-NEXT:    addq $8, %rsp
134; CHECK-NEXT:    popq %rbx
135; CHECK-NEXT:    popq %rbp
136; CHECK-NEXT:    retq
137; CHECK-NEXT:  .LBB1_3: # %C
138; CHECK-NEXT:    movl $2, %edi
139; CHECK-NEXT:    callq dar
140; CHECK-NEXT:    movl $0, GHJK(%rip)
141; CHECK-NEXT:    jmpq *%rbx
142entry:
143  %a = call i1 @qux()
144  %c = call ptr @choose(ptr blockaddress(@tail_duplicate_me, %return),
145                        ptr blockaddress(@tail_duplicate_me, %altret))
146  br i1 %a, label %A, label %next
147next:
148  %b = call i1 @qux()
149  br i1 %b, label %B, label %C
150
151A:
152  call void @bar(i32 0)
153  store i32 0, ptr @GHJK
154  br label %M
155
156B:
157  call void @car(i32 1)
158  store i32 0, ptr @GHJK
159  br label %M
160
161C:
162  call void @dar(i32 2)
163  store i32 0, ptr @GHJK
164  br label %M
165
166M:
167  indirectbr ptr %c, [label %return, label %altret]
168
169return:
170  call void @ear(i32 1000)
171  ret void
172altret:
173  call void @far(i32 1001)
174  ret void
175}
176
177; BranchFolding shouldn't try to merge the tails of two blocks
178; with only a branch in common, regardless of the fallthrough situation.
179
180define i1 @dont_merge_oddly(ptr %result) nounwind {
181; CHECK-LABEL: dont_merge_oddly:
182; CHECK:       # %bb.0: # %entry
183; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
184; CHECK-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
185; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
186; CHECK-NEXT:    ucomiss %xmm1, %xmm2
187; CHECK-NEXT:    jbe .LBB2_3
188; CHECK-NEXT:  # %bb.1: # %bb
189; CHECK-NEXT:    ucomiss %xmm0, %xmm1
190; CHECK-NEXT:    ja .LBB2_4
191; CHECK-NEXT:  .LBB2_2: # %bb30
192; CHECK-NEXT:    movb $1, %al
193; CHECK-NEXT:    retq
194; CHECK-NEXT:  .LBB2_3: # %bb21
195; CHECK-NEXT:    ucomiss %xmm0, %xmm2
196; CHECK-NEXT:    jbe .LBB2_2
197; CHECK-NEXT:  .LBB2_4: # %bb26
198; CHECK-NEXT:    xorl %eax, %eax
199; CHECK-NEXT:    retq
200entry:
201  %tmp4 = getelementptr float, ptr %result, i32 2
202  %tmp5 = load float, ptr %tmp4, align 4
203  %tmp7 = getelementptr float, ptr %result, i32 4
204  %tmp8 = load float, ptr %tmp7, align 4
205  %tmp10 = getelementptr float, ptr %result, i32 6
206  %tmp11 = load float, ptr %tmp10, align 4
207  %tmp12 = fcmp olt float %tmp8, %tmp11
208  br i1 %tmp12, label %bb, label %bb21
209
210bb:
211  %tmp23469 = fcmp olt float %tmp5, %tmp8
212  br i1 %tmp23469, label %bb26, label %bb30
213
214bb21:
215  %tmp23 = fcmp olt float %tmp5, %tmp11
216  br i1 %tmp23, label %bb26, label %bb30
217
218bb26:
219  ret i1 0
220
221bb30:
222  ret i1 1
223}
224
225; Do any-size tail-merging when two candidate blocks will both require
226; an unconditional jump to complete a two-way conditional branch.
227;
228; This test only works when register allocation happens to use %rax for both
229; load addresses.
230
231%0 = type { ptr }
232%struct.lang_decl = type opaque
233%struct.rtx_def = type { i16, i8, i8, [1 x %union.rtunion] }
234%struct.tree_decl = type { [24 x i8], ptr, i32, ptr, i32, i8, i8, i8, i8, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, %union..2anon, %0, ptr, ptr }
235%union..2anon = type { i32 }
236%union.rtunion = type { ptr }
237%union.tree_node = type { %struct.tree_decl }
238
239define fastcc void @c_expand_expr_stmt(ptr %expr) nounwind {
240; CHECK-LABEL: c_expand_expr_stmt:
241; CHECK:       # %bb.0: # %entry
242; CHECK-NEXT:    pushq %rbx
243; CHECK-NEXT:    xorl %eax, %eax
244; CHECK-NEXT:    testb %al, %al
245; CHECK-NEXT:    jne .LBB3_9
246; CHECK-NEXT:  # %bb.1: # %entry
247; CHECK-NEXT:    movzbl 0, %ebx
248; CHECK-NEXT:    xorl %eax, %eax
249; CHECK-NEXT:    testb %al, %al
250; CHECK-NEXT:    jne .LBB3_8
251; CHECK-NEXT:  # %bb.2: # %bb.i
252; CHECK-NEXT:    xorl %eax, %eax
253; CHECK-NEXT:    testb %al, %al
254; CHECK-NEXT:    je .LBB3_8
255; CHECK-NEXT:  # %bb.3: # %lvalue_p.exit
256; CHECK-NEXT:    movq 0, %rax
257; CHECK-NEXT:    movzbl (%rax), %ecx
258; CHECK-NEXT:    testl %ecx, %ecx
259; CHECK-NEXT:    je .LBB3_10
260; CHECK-NEXT:  # %bb.4: # %lvalue_p.exit
261; CHECK-NEXT:    cmpl $2, %ecx
262; CHECK-NEXT:    jne .LBB3_15
263; CHECK-NEXT:  # %bb.5: # %bb.i1
264; CHECK-NEXT:    movq 32(%rax), %rax
265; CHECK-NEXT:    movzbl 16(%rax), %ecx
266; CHECK-NEXT:    testl %ecx, %ecx
267; CHECK-NEXT:    je .LBB3_13
268; CHECK-NEXT:  # %bb.6: # %bb.i1
269; CHECK-NEXT:    cmpl $2, %ecx
270; CHECK-NEXT:    jne .LBB3_15
271; CHECK-NEXT:  # %bb.7: # %bb.i.i
272; CHECK-NEXT:    xorl %edi, %edi
273; CHECK-NEXT:    callq lvalue_p@PLT
274; CHECK-NEXT:    testl %eax, %eax
275; CHECK-NEXT:    setne %al
276; CHECK-NEXT:    jmp .LBB3_16
277; CHECK-NEXT:  .LBB3_8: # %bb1
278; CHECK-NEXT:    cmpb $23, %bl
279; CHECK-NEXT:  .LBB3_9: # %bb3
280; CHECK-NEXT:  .LBB3_15:
281; CHECK-NEXT:    xorl %eax, %eax
282; CHECK-NEXT:    jmp .LBB3_16
283; CHECK-NEXT:  .LBB3_10: # %bb2.i3
284; CHECK-NEXT:    movq 8(%rax), %rax
285; CHECK-NEXT:    movzbl 16(%rax), %ecx
286; CHECK-NEXT:    xorl %eax, %eax
287; CHECK-NEXT:    cmpl $23, %ecx
288; CHECK-NEXT:    je .LBB3_16
289; CHECK-NEXT:  # %bb.11: # %bb2.i3
290; CHECK-NEXT:    cmpl $16, %ecx
291; CHECK-NEXT:    je .LBB3_16
292; CHECK-NEXT:    jmp .LBB3_9
293; CHECK-NEXT:  .LBB3_13: # %bb2.i.i2
294; CHECK-NEXT:    movq 8(%rax), %rax
295; CHECK-NEXT:    movzbl 16(%rax), %ecx
296; CHECK-NEXT:    xorl %eax, %eax
297; CHECK-NEXT:    cmpl $16, %ecx
298; CHECK-NEXT:    je .LBB3_16
299; CHECK-NEXT:  # %bb.14: # %bb2.i.i2
300; CHECK-NEXT:    cmpl $23, %ecx
301; CHECK-NEXT:    jne .LBB3_9
302; CHECK-NEXT:  .LBB3_16: # %lvalue_p.exit4
303; CHECK-NEXT:    testb %bl, %bl
304; CHECK-NEXT:    sete %cl
305; CHECK-NEXT:    orb %al, %cl
306entry:
307  %tmp4 = load i8, ptr null, align 8                  ; <i8> [#uses=3]
308  switch i8 %tmp4, label %bb3 [
309    i8 18, label %bb
310  ]
311
312bb:                                               ; preds = %entry
313  switch i32 undef, label %bb1 [
314    i32 0, label %bb2.i
315    i32 37, label %bb.i
316  ]
317
318bb.i:                                             ; preds = %bb
319  switch i32 undef, label %bb1 [
320    i32 0, label %lvalue_p.exit
321  ]
322
323bb2.i:                                            ; preds = %bb
324  br label %bb3
325
326lvalue_p.exit:                                    ; preds = %bb.i
327  %tmp21 = load ptr, ptr null, align 8  ; <ptr> [#uses=3]
328  %tmp22 = getelementptr inbounds %union.tree_node, ptr %tmp21, i64 0, i32 0, i32 0, i64 0 ; <ptr> [#uses=1]
329  %tmp23 = load i8, ptr %tmp22, align 8               ; <i8> [#uses=1]
330  %tmp24 = zext i8 %tmp23 to i32                  ; <i32> [#uses=1]
331  switch i32 %tmp24, label %lvalue_p.exit4 [
332    i32 0, label %bb2.i3
333    i32 2, label %bb.i1
334  ]
335
336bb.i1:                                            ; preds = %lvalue_p.exit
337  %tmp25 = getelementptr inbounds %union.tree_node, ptr %tmp21, i64 0, i32 0, i32 2 ; <ptr> [#uses=1]
338  %tmp27 = load ptr, ptr %tmp25, align 8 ; <ptr> [#uses=2]
339  %tmp28 = getelementptr inbounds %union.tree_node, ptr %tmp27, i64 0, i32 0, i32 0, i64 16 ; <ptr> [#uses=1]
340  %tmp29 = load i8, ptr %tmp28, align 8               ; <i8> [#uses=1]
341  %tmp30 = zext i8 %tmp29 to i32                  ; <i32> [#uses=1]
342  switch i32 %tmp30, label %lvalue_p.exit4 [
343    i32 0, label %bb2.i.i2
344    i32 2, label %bb.i.i
345  ]
346
347bb.i.i:                                           ; preds = %bb.i1
348  %tmp34 = tail call fastcc i32 @lvalue_p(ptr null) nounwind ; <i32> [#uses=1]
349  %phitmp = icmp ne i32 %tmp34, 0                 ; <i1> [#uses=1]
350  br label %lvalue_p.exit4
351
352bb2.i.i2:                                         ; preds = %bb.i1
353  %tmp35 = getelementptr inbounds %union.tree_node, ptr %tmp27, i64 0, i32 0, i32 0, i64 8 ; <ptr> [#uses=1]
354  %tmp37 = load ptr, ptr %tmp35, align 8 ; <ptr> [#uses=1]
355  %tmp38 = getelementptr inbounds %union.tree_node, ptr %tmp37, i64 0, i32 0, i32 0, i64 16 ; <ptr> [#uses=1]
356  %tmp39 = load i8, ptr %tmp38, align 8               ; <i8> [#uses=1]
357  switch i8 %tmp39, label %bb2 [
358    i8 16, label %lvalue_p.exit4
359    i8 23, label %lvalue_p.exit4
360  ]
361
362bb2.i3:                                           ; preds = %lvalue_p.exit
363  %tmp40 = getelementptr inbounds %union.tree_node, ptr %tmp21, i64 0, i32 0, i32 0, i64 8 ; <ptr> [#uses=1]
364  %tmp42 = load ptr, ptr %tmp40, align 8 ; <ptr> [#uses=1]
365  %tmp43 = getelementptr inbounds %union.tree_node, ptr %tmp42, i64 0, i32 0, i32 0, i64 16 ; <ptr> [#uses=1]
366  %tmp44 = load i8, ptr %tmp43, align 8               ; <i8> [#uses=1]
367  switch i8 %tmp44, label %bb2 [
368    i8 16, label %lvalue_p.exit4
369    i8 23, label %lvalue_p.exit4
370  ]
371
372lvalue_p.exit4:                                   ; preds = %bb2.i3, %bb2.i3, %bb2.i.i2, %bb2.i.i2, %bb.i.i, %bb.i1, %lvalue_p.exit
373  %tmp45 = phi i1 [ %phitmp, %bb.i.i ], [ false, %bb2.i.i2 ], [ false, %bb2.i.i2 ], [ false, %bb.i1 ], [ false, %bb2.i3 ], [ false, %bb2.i3 ], [ false, %lvalue_p.exit ] ; <i1> [#uses=1]
374  %tmp46 = icmp eq i8 %tmp4, 0                    ; <i1> [#uses=1]
375  %or.cond = or i1 %tmp45, %tmp46                 ; <i1> [#uses=1]
376  br i1 %or.cond, label %bb2, label %bb3
377
378bb1:                                              ; preds = %bb2.i.i, %bb.i, %bb
379  %.old = icmp eq i8 %tmp4, 23                    ; <i1> [#uses=1]
380  br i1 %.old, label %bb2, label %bb3
381
382bb2:                                              ; preds = %bb1, %lvalue_p.exit4, %bb2.i3, %bb2.i.i2
383  br label %bb3
384
385bb3:                                              ; preds = %bb2, %bb1, %lvalue_p.exit4, %bb2.i, %entry
386  %expr_addr.0 = phi ptr [ null, %bb2 ], [ %expr, %bb2.i ], [ %expr, %entry ], [ %expr, %bb1 ], [ %expr, %lvalue_p.exit4 ] ; <ptr> [#uses=0]
387  unreachable
388}
389
390declare fastcc i32 @lvalue_p(ptr nocapture) nounwind readonly
391
392declare fastcc ptr @default_conversion(ptr) nounwind
393
394
395; If one tail merging candidate falls through into the other,
396; tail merging is likely profitable regardless of how few
397; instructions are involved. This function should have only
398; one ret instruction.
399
400define dso_local void @foo(ptr %V) nounwind {
401; CHECK-LABEL: foo:
402; CHECK:       # %bb.0: # %entry
403; CHECK-NEXT:    testq %rdi, %rdi
404; CHECK-NEXT:    je .LBB4_2
405; CHECK-NEXT:  # %bb.1: # %bb
406; CHECK-NEXT:    pushq %rax
407; CHECK-NEXT:    callq func
408; CHECK-NEXT:    popq %rax
409; CHECK-NEXT:  .LBB4_2: # %return
410; CHECK-NEXT:    retq
411entry:
412  %t0 = icmp eq ptr %V, null
413  br i1 %t0, label %return, label %bb
414
415bb:
416  call void @func()
417  ret void
418
419return:
420  ret void
421}
422
423declare dso_local void @func()
424
425; one - One instruction may be tail-duplicated even with optsize.
426
427@XYZ = external dso_local global i32
428
429declare dso_local void @tail_call_me()
430
431define dso_local void @one(i32 %v) nounwind optsize {
432; CHECK-LABEL: one:
433; CHECK:       # %bb.0: # %entry
434; CHECK-NEXT:    testl %edi, %edi
435; CHECK-NEXT:    je .LBB5_3
436; CHECK-NEXT:  # %bb.1: # %bby
437; CHECK-NEXT:    cmpl $16, %edi
438; CHECK-NEXT:    je .LBB5_4
439; CHECK-NEXT:  # %bb.2: # %bb7
440; CHECK-NEXT:    jmp tail_call_me # TAILCALL
441; CHECK-NEXT:  .LBB5_3: # %bbx
442; CHECK-NEXT:    cmpl $128, %edi
443; CHECK-NEXT:    jne tail_call_me # TAILCALL
444; CHECK-NEXT:  .LBB5_4: # %return
445; CHECK-NEXT:    retq
446entry:
447  %0 = icmp eq i32 %v, 0
448  br i1 %0, label %bbx, label %bby
449
450bby:
451  switch i32 %v, label %bb7 [
452    i32 16, label %return
453  ]
454
455bb7:
456  tail call void @tail_call_me()
457  ret void
458
459bbx:
460  switch i32 %v, label %bb12 [
461    i32 128, label %return
462  ]
463
464bb12:
465  tail call void @tail_call_me()
466  ret void
467
468return:
469  ret void
470}
471
472define dso_local void @one_pgso(i32 %v) nounwind !prof !14 {
473; CHECK-LABEL: one_pgso:
474; CHECK:       # %bb.0: # %entry
475; CHECK-NEXT:    testl %edi, %edi
476; CHECK-NEXT:    je .LBB6_3
477; CHECK-NEXT:  # %bb.1: # %bby
478; CHECK-NEXT:    cmpl $16, %edi
479; CHECK-NEXT:    je .LBB6_4
480; CHECK-NEXT:  # %bb.2: # %bb7
481; CHECK-NEXT:    jmp tail_call_me # TAILCALL
482; CHECK-NEXT:  .LBB6_3: # %bbx
483; CHECK-NEXT:    cmpl $128, %edi
484; CHECK-NEXT:    jne tail_call_me # TAILCALL
485; CHECK-NEXT:  .LBB6_4: # %return
486; CHECK-NEXT:    retq
487entry:
488  %0 = icmp eq i32 %v, 0
489  br i1 %0, label %bbx, label %bby
490
491bby:
492  switch i32 %v, label %bb7 [
493    i32 16, label %return
494  ]
495
496bb7:
497  tail call void @tail_call_me()
498  ret void
499
500bbx:
501  switch i32 %v, label %bb12 [
502    i32 128, label %return
503  ]
504
505bb12:
506  tail call void @tail_call_me()
507  ret void
508
509return:
510  ret void
511}
512
513; two - Same as one, but with two instructions in the common
514; tail instead of one. This is too much to be merged, given
515; the optsize attribute.
516
517define dso_local void @two() nounwind optsize {
518; CHECK-LABEL: two:
519; CHECK:       # %bb.0: # %entry
520; CHECK-NEXT:    xorl %eax, %eax
521; CHECK-NEXT:    testb %al, %al
522; CHECK-NEXT:    xorl %eax, %eax
523; CHECK-NEXT:    testb %al, %al
524; CHECK-NEXT:    je .LBB7_1
525; CHECK-NEXT:  # %bb.2: # %return
526; CHECK-NEXT:    retq
527; CHECK-NEXT:  .LBB7_1: # %bb7
528; CHECK-NEXT:    movl $0, XYZ(%rip)
529; CHECK-NEXT:    movl $1, XYZ(%rip)
530entry:
531  %0 = icmp eq i32 undef, 0
532  br i1 %0, label %bbx, label %bby
533
534bby:
535  switch i32 undef, label %bb7 [
536    i32 16, label %return
537  ]
538
539bb7:
540  store volatile i32 0, ptr @XYZ
541  store volatile i32 1, ptr @XYZ
542  unreachable
543
544bbx:
545  switch i32 undef, label %bb12 [
546    i32 128, label %return
547  ]
548
549bb12:
550  store volatile i32 0, ptr @XYZ
551  store volatile i32 1, ptr @XYZ
552  unreachable
553
554return:
555  ret void
556}
557
558define dso_local void @two_pgso() nounwind !prof !14 {
559; CHECK-LABEL: two_pgso:
560; CHECK:       # %bb.0: # %entry
561; CHECK-NEXT:    xorl %eax, %eax
562; CHECK-NEXT:    testb %al, %al
563; CHECK-NEXT:    xorl %eax, %eax
564; CHECK-NEXT:    testb %al, %al
565; CHECK-NEXT:    je .LBB8_1
566; CHECK-NEXT:  # %bb.2: # %return
567; CHECK-NEXT:    retq
568; CHECK-NEXT:  .LBB8_1: # %bb7
569; CHECK-NEXT:    movl $0, XYZ(%rip)
570; CHECK-NEXT:    movl $1, XYZ(%rip)
571entry:
572  %0 = icmp eq i32 undef, 0
573  br i1 %0, label %bbx, label %bby
574
575bby:
576  switch i32 undef, label %bb7 [
577    i32 16, label %return
578  ]
579
580bb7:
581  store volatile i32 0, ptr @XYZ
582  store volatile i32 1, ptr @XYZ
583  unreachable
584
585bbx:
586  switch i32 undef, label %bb12 [
587    i32 128, label %return
588  ]
589
590bb12:
591  store volatile i32 0, ptr @XYZ
592  store volatile i32 1, ptr @XYZ
593  unreachable
594
595return:
596  ret void
597}
598
599; two_minsize - Same as two, but with minsize instead of optsize.
600
601define dso_local void @two_minsize() nounwind minsize {
602; CHECK-LABEL: two_minsize:
603; CHECK:       # %bb.0: # %entry
604; CHECK-NEXT:    xorl %eax, %eax
605; CHECK-NEXT:    testb %al, %al
606; CHECK-NEXT:    xorl %eax, %eax
607; CHECK-NEXT:    testb %al, %al
608; CHECK-NEXT:    je .LBB9_1
609; CHECK-NEXT:  # %bb.2: # %return
610; CHECK-NEXT:    retq
611; CHECK-NEXT:  .LBB9_1: # %bb7
612; CHECK-NEXT:    movl $0, XYZ(%rip)
613; CHECK-NEXT:    movl $1, XYZ(%rip)
614entry:
615  %0 = icmp eq i32 undef, 0
616  br i1 %0, label %bbx, label %bby
617
618bby:
619  switch i32 undef, label %bb7 [
620    i32 16, label %return
621  ]
622
623bb7:
624  store volatile i32 0, ptr @XYZ
625  store volatile i32 1, ptr @XYZ
626  unreachable
627
628bbx:
629  switch i32 undef, label %bb12 [
630    i32 128, label %return
631  ]
632
633bb12:
634  store volatile i32 0, ptr @XYZ
635  store volatile i32 1, ptr @XYZ
636  unreachable
637
638return:
639  ret void
640}
641
642; two_nosize - Same as two, but without the optsize attribute.
643; Now two instructions are enough to be tail-duplicated.
644
645define dso_local void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind {
646; CHECK-LABEL: two_nosize:
647; CHECK:       # %bb.0: # %entry
648; CHECK-NEXT:    testl %edi, %edi
649; CHECK-NEXT:    je .LBB10_3
650; CHECK-NEXT:  # %bb.1: # %bby
651; CHECK-NEXT:    testl %esi, %esi
652; CHECK-NEXT:    je .LBB10_4
653; CHECK-NEXT:  # %bb.2: # %bb7
654; CHECK-NEXT:    movl $0, XYZ(%rip)
655; CHECK-NEXT:    jmp tail_call_me # TAILCALL
656; CHECK-NEXT:  .LBB10_3: # %bbx
657; CHECK-NEXT:    cmpl $-1, %edx
658; CHECK-NEXT:    je .LBB10_4
659; CHECK-NEXT:  # %bb.5: # %bb12
660; CHECK-NEXT:    movl $0, XYZ(%rip)
661; CHECK-NEXT:    jmp tail_call_me # TAILCALL
662; CHECK-NEXT:  .LBB10_4: # %return
663; CHECK-NEXT:    retq
664entry:
665  %0 = icmp eq i32 %x, 0
666  br i1 %0, label %bbx, label %bby
667
668bby:
669  switch i32 %y, label %bb7 [
670    i32 0, label %return
671  ]
672
673bb7:
674  store volatile i32 0, ptr @XYZ
675  tail call void @tail_call_me()
676  ret void
677
678bbx:
679  switch i32 %z, label %bb12 [
680    i32 -1, label %return
681  ]
682
683bb12:
684  store volatile i32 0, ptr @XYZ
685  tail call void @tail_call_me()
686  ret void
687
688return:
689  ret void
690}
691
692; Tail-merging should merge the two ret instructions since one side
693; can fall-through into the ret and the other side has to branch anyway.
694
695define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone {
696; CHECK-LABEL: TESTE:
697; CHECK:       # %bb.0: # %entry
698; CHECK-NEXT:    testq %rdi, %rdi
699; CHECK-NEXT:    movl $1, %eax
700; CHECK-NEXT:    cmovgq %rdi, %rax
701; CHECK-NEXT:    testq %rsi, %rsi
702; CHECK-NEXT:    jle .LBB11_2
703; CHECK-NEXT:  # %bb.1: # %bb.nph
704; CHECK-NEXT:    imulq %rdi, %rsi
705; CHECK-NEXT:    movq %rsi, %rax
706; CHECK-NEXT:  .LBB11_2: # %for.end
707; CHECK-NEXT:    retq
708entry:
709  %cmp = icmp slt i64 %parami, 1                  ; <i1> [#uses=1]
710  %varx.0 = select i1 %cmp, i64 1, i64 %parami    ; <i64> [#uses=1]
711  %cmp410 = icmp slt i64 %paraml, 1               ; <i1> [#uses=1]
712  br i1 %cmp410, label %for.end, label %bb.nph
713
714bb.nph:                                           ; preds = %entry
715  %tmp15 = mul i64 %paraml, %parami                   ; <i64> [#uses=1]
716  ret i64 %tmp15
717
718for.end:                                          ; preds = %entry
719  ret i64 %varx.0
720}
721
722; We should tail merge small blocks that don't end in a tail call or return
723; instruction. Those blocks are typically unreachable and will be placed
724; out-of-line after the main return, so we should try to eliminate as many of
725; them as possible.
726
727declare dso_local void @abort()
728define dso_local void @merge_aborts() {
729; CHECK-LABEL: merge_aborts:
730; CHECK:       # %bb.0: # %entry
731; CHECK-NEXT:    pushq %rax
732; CHECK-NEXT:    .cfi_def_cfa_offset 16
733; CHECK-NEXT:    callq qux@PLT
734; CHECK-NEXT:    testb $1, %al
735; CHECK-NEXT:    je .LBB12_5
736; CHECK-NEXT:  # %bb.1: # %cont1
737; CHECK-NEXT:    callq qux@PLT
738; CHECK-NEXT:    testb $1, %al
739; CHECK-NEXT:    je .LBB12_5
740; CHECK-NEXT:  # %bb.2: # %cont2
741; CHECK-NEXT:    callq qux@PLT
742; CHECK-NEXT:    testb $1, %al
743; CHECK-NEXT:    je .LBB12_5
744; CHECK-NEXT:  # %bb.3: # %cont3
745; CHECK-NEXT:    callq qux@PLT
746; CHECK-NEXT:    testb $1, %al
747; CHECK-NEXT:    je .LBB12_5
748; CHECK-NEXT:  # %bb.4: # %cont4
749; CHECK-NEXT:    popq %rax
750; CHECK-NEXT:    .cfi_def_cfa_offset 8
751; CHECK-NEXT:    retq
752; CHECK-NEXT:  .LBB12_5: # %abort1
753; CHECK-NEXT:    .cfi_def_cfa_offset 16
754; CHECK-NEXT:    callq abort
755entry:
756  %c1 = call i1 @qux()
757  br i1 %c1, label %cont1, label %abort1
758abort1:
759  call void @abort()
760  unreachable
761cont1:
762  %c2 = call i1 @qux()
763  br i1 %c2, label %cont2, label %abort2
764abort2:
765  call void @abort()
766  unreachable
767cont2:
768  %c3 = call i1 @qux()
769  br i1 %c3, label %cont3, label %abort3
770abort3:
771  call void @abort()
772  unreachable
773cont3:
774  %c4 = call i1 @qux()
775  br i1 %c4, label %cont4, label %abort4
776abort4:
777  call void @abort()
778  unreachable
779cont4:
780  ret void
781}
782
783; Use alternating abort functions so that the blocks we wish to merge are not
784; layout successors during branch folding.
785
786declare dso_local void @alt_abort()
787
788define dso_local void @merge_alternating_aborts() {
789; CHECK-LABEL: merge_alternating_aborts:
790; CHECK:       # %bb.0: # %entry
791; CHECK-NEXT:    pushq %rax
792; CHECK-NEXT:    .cfi_def_cfa_offset 16
793; CHECK-NEXT:    callq qux@PLT
794; CHECK-NEXT:    testb $1, %al
795; CHECK-NEXT:    je .LBB13_5
796; CHECK-NEXT:  # %bb.1: # %cont1
797; CHECK-NEXT:    callq qux@PLT
798; CHECK-NEXT:    testb $1, %al
799; CHECK-NEXT:    je .LBB13_6
800; CHECK-NEXT:  # %bb.2: # %cont2
801; CHECK-NEXT:    callq qux@PLT
802; CHECK-NEXT:    testb $1, %al
803; CHECK-NEXT:    je .LBB13_5
804; CHECK-NEXT:  # %bb.3: # %cont3
805; CHECK-NEXT:    callq qux@PLT
806; CHECK-NEXT:    testb $1, %al
807; CHECK-NEXT:    je .LBB13_6
808; CHECK-NEXT:  # %bb.4: # %cont4
809; CHECK-NEXT:    popq %rax
810; CHECK-NEXT:    .cfi_def_cfa_offset 8
811; CHECK-NEXT:    retq
812; CHECK-NEXT:  .LBB13_5: # %abort1
813; CHECK-NEXT:    .cfi_def_cfa_offset 16
814; CHECK-NEXT:    callq abort
815; CHECK-NEXT:  .LBB13_6: # %abort2
816; CHECK-NEXT:    callq alt_abort
817entry:
818  %c1 = call i1 @qux()
819  br i1 %c1, label %cont1, label %abort1
820abort1:
821  call void @abort()
822  unreachable
823cont1:
824  %c2 = call i1 @qux()
825  br i1 %c2, label %cont2, label %abort2
826abort2:
827  call void @alt_abort()
828  unreachable
829cont2:
830  %c3 = call i1 @qux()
831  br i1 %c3, label %cont3, label %abort3
832abort3:
833  call void @abort()
834  unreachable
835cont3:
836  %c4 = call i1 @qux()
837  br i1 %c4, label %cont4, label %abort4
838abort4:
839  call void @alt_abort()
840  unreachable
841cont4:
842  ret void
843}
844
845; This triggers a situation where a new block (bb4 is split) is created and then
846; would be passed to the PGSO interface llvm::shouldOptimizeForSize().
847@GV = dso_local global i32 0
848define dso_local void @bfi_new_block_pgso(i32 %c) nounwind {
849; CHECK-LABEL: bfi_new_block_pgso:
850; CHECK:       # %bb.0: # %entry
851; CHECK-NEXT:    testl %edi, %edi
852; CHECK-NEXT:    je .LBB14_6
853; CHECK-NEXT:  # %bb.1: # %bb1
854; CHECK-NEXT:    pushq %rax
855; CHECK-NEXT:    cmpl $16, %edi
856; CHECK-NEXT:    je .LBB14_3
857; CHECK-NEXT:  # %bb.2: # %bb1
858; CHECK-NEXT:    cmpl $17, %edi
859; CHECK-NEXT:    je .LBB14_4
860; CHECK-NEXT:  # %bb.5: # %bb4
861; CHECK-NEXT:    popq %rax
862; CHECK-NEXT:    jmp tail_call_me # TAILCALL
863; CHECK-NEXT:  .LBB14_6: # %bb5
864; CHECK-NEXT:    cmpl $128, %edi
865; CHECK-NEXT:    jne tail_call_me # TAILCALL
866; CHECK-NEXT:  # %bb.7: # %return
867; CHECK-NEXT:    retq
868; CHECK-NEXT:  .LBB14_3: # %bb3
869; CHECK-NEXT:    movl $0, GV(%rip)
870; CHECK-NEXT:  .LBB14_4: # %bb4
871; CHECK-NEXT:    callq func
872; CHECK-NEXT:    popq %rax
873; CHECK-NEXT:    jmp tail_call_me # TAILCALL
874entry:
875  %0 = icmp eq i32 %c, 0
876  br i1 %0, label %bb5, label %bb1
877
878bb1:
879  switch i32 %c, label %bb4 [
880    i32 16, label %bb3
881    i32 17, label %bb2
882  ]
883
884bb2:
885  call void @func()
886  br label %bb4
887
888bb3:
889  store i32 0, ptr @GV
890  call void @func()
891  br label %bb4
892
893bb4:
894  tail call void @tail_call_me()
895  br label %return
896
897bb5:
898  switch i32 %c, label %bb6 [
899    i32 128, label %return
900  ]
901
902bb6:
903  tail call void @tail_call_me()
904  br label %return
905
906return:
907  ret void
908}
909
910!llvm.module.flags = !{!0}
911!0 = !{i32 1, !"ProfileSummary", !1}
912!1 = !{!2, !3, !4, !5, !6, !7, !8, !9}
913!2 = !{!"ProfileFormat", !"InstrProf"}
914!3 = !{!"TotalCount", i64 10000}
915!4 = !{!"MaxCount", i64 10}
916!5 = !{!"MaxInternalCount", i64 1}
917!6 = !{!"MaxFunctionCount", i64 1000}
918!7 = !{!"NumCounts", i64 3}
919!8 = !{!"NumFunctions", i64 3}
920!9 = !{!"DetailedSummary", !10}
921!10 = !{!11, !12, !13}
922!11 = !{i32 10000, i64 100, i32 1}
923!12 = !{i32 999000, i64 100, i32 1}
924!13 = !{i32 999999, i64 1, i32 2}
925!14 = !{!"function_entry_count", i64 0}
926