xref: /llvm-project/llvm/test/CodeGen/X86/sm3-intrinsics.ll (revision c6f66de21af060ead6e5402858351e9e869dc15f)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
3; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm3 | FileCheck %s
4
5define <4 x i32> @test_int_x86_vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
6; CHECK-LABEL: test_int_x86_vsm3msg1:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsm3msg1 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x70,0xda,0xc2]
9; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
10  %ret = call <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
11  ret <4 x i32> %ret
12}
13declare <4 x i32> @llvm.x86.vsm3msg1(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
14
15define <4 x i32> @test_int_x86_vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
16; CHECK-LABEL: test_int_x86_vsm3msg2:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsm3msg2 %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x71,0xda,0xc2]
19; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
20  %ret = call <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
21  ret <4 x i32> %ret
22}
23declare <4 x i32> @llvm.x86.vsm3msg2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C)
24
25define <4 x i32> @test_int_x86_vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
26; CHECK-LABEL: test_int_x86_vsm3rnds2:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsm3rnds2 $127, %xmm2, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0xde,0xc2,0x7f]
29; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
30  %ret = call <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 127)
31  ret <4 x i32> %ret
32}
33declare <4 x i32> @llvm.x86.vsm3rnds2(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32 %D)
34
35