xref: /llvm-project/llvm/test/CodeGen/X86/signbit-test.ll (revision adc7c589c3dd35af5991ee481fa4667094bca548) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
3
4define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {
5; CHECK-LABEL: test_clear_mask_i64_i32:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    movq %rdi, %rax
8; CHECK-NEXT:    testl %eax, %eax
9; CHECK-NEXT:    js .LBB0_2
10; CHECK-NEXT:  # %bb.1: # %t
11; CHECK-NEXT:    movl $42, %eax
12; CHECK-NEXT:  .LBB0_2: # %f
13; CHECK-NEXT:    retq
14entry:
15  %a = and i64 %x, 2147483648
16  %r = icmp eq i64 %a, 0
17  br i1 %r, label %t, label %f
18t:
19  br label %f
20f:
21  %ret = phi i64 [ %x, %entry], [ 42, %t]
22  ret i64 %ret
23}
24
25define i64 @test_set_mask_i64_i32(i64 %x) nounwind {
26; CHECK-LABEL: test_set_mask_i64_i32:
27; CHECK:       # %bb.0: # %entry
28; CHECK-NEXT:    movq %rdi, %rax
29; CHECK-NEXT:    testl %eax, %eax
30; CHECK-NEXT:    jns .LBB1_2
31; CHECK-NEXT:  # %bb.1: # %t
32; CHECK-NEXT:    movl $42, %eax
33; CHECK-NEXT:  .LBB1_2: # %f
34; CHECK-NEXT:    retq
35entry:
36  %a = and i64 %x, 2147483648
37  %r = icmp ne i64 %a, 0
38  br i1 %r, label %t, label %f
39t:
40  br label %f
41f:
42  %ret = phi i64 [ %x, %entry], [ 42, %t]
43  ret i64 %ret
44}
45
46define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {
47; CHECK-LABEL: test_clear_mask_i64_i16:
48; CHECK:       # %bb.0: # %entry
49; CHECK-NEXT:    movq %rdi, %rax
50; CHECK-NEXT:    testw %ax, %ax
51; CHECK-NEXT:    js .LBB2_2
52; CHECK-NEXT:  # %bb.1: # %t
53; CHECK-NEXT:    movl $42, %eax
54; CHECK-NEXT:  .LBB2_2: # %f
55; CHECK-NEXT:    retq
56entry:
57  %a = and i64 %x, 32768
58  %r = icmp eq i64 %a, 0
59  br i1 %r, label %t, label %f
60t:
61  br label %f
62f:
63  %ret = phi i64 [ %x, %entry], [ 42, %t]
64  ret i64 %ret
65}
66
67define i64 @test_set_mask_i64_i16(i64 %x) nounwind {
68; CHECK-LABEL: test_set_mask_i64_i16:
69; CHECK:       # %bb.0: # %entry
70; CHECK-NEXT:    movq %rdi, %rax
71; CHECK-NEXT:    testw %ax, %ax
72; CHECK-NEXT:    jns .LBB3_2
73; CHECK-NEXT:  # %bb.1: # %t
74; CHECK-NEXT:    movl $42, %eax
75; CHECK-NEXT:  .LBB3_2: # %f
76; CHECK-NEXT:    retq
77entry:
78  %a = and i64 %x, 32768
79  %r = icmp ne i64 %a, 0
80  br i1 %r, label %t, label %f
81t:
82  br label %f
83f:
84  %ret = phi i64 [ %x, %entry], [ 42, %t]
85  ret i64 %ret
86}
87
88define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {
89; CHECK-LABEL: test_clear_mask_i64_i8:
90; CHECK:       # %bb.0: # %entry
91; CHECK-NEXT:    movq %rdi, %rax
92; CHECK-NEXT:    testb %al, %al
93; CHECK-NEXT:    js .LBB4_2
94; CHECK-NEXT:  # %bb.1: # %t
95; CHECK-NEXT:    movl $42, %eax
96; CHECK-NEXT:  .LBB4_2: # %f
97; CHECK-NEXT:    retq
98entry:
99  %a = and i64 %x, 128
100  %r = icmp eq i64 %a, 0
101  br i1 %r, label %t, label %f
102t:
103  br label %f
104f:
105  %ret = phi i64 [ %x, %entry], [ 42, %t]
106  ret i64 %ret
107}
108
109define i64 @test_set_mask_i64_i8(i64 %x) nounwind {
110; CHECK-LABEL: test_set_mask_i64_i8:
111; CHECK:       # %bb.0: # %entry
112; CHECK-NEXT:    movq %rdi, %rax
113; CHECK-NEXT:    testb %al, %al
114; CHECK-NEXT:    jns .LBB5_2
115; CHECK-NEXT:  # %bb.1: # %t
116; CHECK-NEXT:    movl $42, %eax
117; CHECK-NEXT:  .LBB5_2: # %f
118; CHECK-NEXT:    retq
119entry:
120  %a = and i64 %x, 128
121  %r = icmp ne i64 %a, 0
122  br i1 %r, label %t, label %f
123t:
124  br label %f
125f:
126  %ret = phi i64 [ %x, %entry], [ 42, %t]
127  ret i64 %ret
128}
129
130define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {
131; CHECK-LABEL: test_clear_mask_i32_i16:
132; CHECK:       # %bb.0: # %entry
133; CHECK-NEXT:    movl %edi, %eax
134; CHECK-NEXT:    testw %ax, %ax
135; CHECK-NEXT:    js .LBB6_2
136; CHECK-NEXT:  # %bb.1: # %t
137; CHECK-NEXT:    movl $42, %eax
138; CHECK-NEXT:  .LBB6_2: # %f
139; CHECK-NEXT:    retq
140entry:
141  %a = and i32 %x, 32768
142  %r = icmp eq i32 %a, 0
143  br i1 %r, label %t, label %f
144t:
145  br label %f
146f:
147  %ret = phi i32 [ %x, %entry], [ 42, %t]
148  ret i32 %ret
149}
150
151define i32 @test_set_mask_i32_i16(i32 %x) nounwind {
152; CHECK-LABEL: test_set_mask_i32_i16:
153; CHECK:       # %bb.0: # %entry
154; CHECK-NEXT:    movl %edi, %eax
155; CHECK-NEXT:    testw %ax, %ax
156; CHECK-NEXT:    jns .LBB7_2
157; CHECK-NEXT:  # %bb.1: # %t
158; CHECK-NEXT:    movl $42, %eax
159; CHECK-NEXT:  .LBB7_2: # %f
160; CHECK-NEXT:    retq
161entry:
162  %a = and i32 %x, 32768
163  %r = icmp ne i32 %a, 0
164  br i1 %r, label %t, label %f
165t:
166  br label %f
167f:
168  %ret = phi i32 [ %x, %entry], [ 42, %t]
169  ret i32 %ret
170}
171
172define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {
173; CHECK-LABEL: test_clear_mask_i32_i8:
174; CHECK:       # %bb.0: # %entry
175; CHECK-NEXT:    movl %edi, %eax
176; CHECK-NEXT:    testb %al, %al
177; CHECK-NEXT:    js .LBB8_2
178; CHECK-NEXT:  # %bb.1: # %t
179; CHECK-NEXT:    movl $42, %eax
180; CHECK-NEXT:  .LBB8_2: # %f
181; CHECK-NEXT:    retq
182entry:
183  %a = and i32 %x, 128
184  %r = icmp eq i32 %a, 0
185  br i1 %r, label %t, label %f
186t:
187  br label %f
188f:
189  %ret = phi i32 [ %x, %entry], [ 42, %t]
190  ret i32 %ret
191}
192
193define i32 @test_set_mask_i32_i8(i32 %x) nounwind {
194; CHECK-LABEL: test_set_mask_i32_i8:
195; CHECK:       # %bb.0: # %entry
196; CHECK-NEXT:    movl %edi, %eax
197; CHECK-NEXT:    testb %al, %al
198; CHECK-NEXT:    jns .LBB9_2
199; CHECK-NEXT:  # %bb.1: # %t
200; CHECK-NEXT:    movl $42, %eax
201; CHECK-NEXT:  .LBB9_2: # %f
202; CHECK-NEXT:    retq
203entry:
204  %a = and i32 %x, 128
205  %r = icmp ne i32 %a, 0
206  br i1 %r, label %t, label %f
207t:
208  br label %f
209f:
210  %ret = phi i32 [ %x, %entry], [ 42, %t]
211  ret i32 %ret
212}
213
214define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
215; CHECK-LABEL: test_clear_mask_i16_i8:
216; CHECK:       # %bb.0: # %entry
217; CHECK-NEXT:    movl %edi, %eax
218; CHECK-NEXT:    testb %al, %al
219; CHECK-NEXT:    js .LBB10_2
220; CHECK-NEXT:  # %bb.1: # %t
221; CHECK-NEXT:    movw $42, %ax
222; CHECK-NEXT:  .LBB10_2: # %f
223; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
224; CHECK-NEXT:    retq
225entry:
226  %a = and i16 %x, 128
227  %r = icmp eq i16 %a, 0
228  br i1 %r, label %t, label %f
229t:
230  br label %f
231f:
232  %ret = phi i16 [ %x, %entry], [ 42, %t]
233  ret i16 %ret
234}
235
236define i16 @test_set_mask_i16_i8(i16 %x) nounwind {
237; CHECK-LABEL: test_set_mask_i16_i8:
238; CHECK:       # %bb.0: # %entry
239; CHECK-NEXT:    movl %edi, %eax
240; CHECK-NEXT:    testb %al, %al
241; CHECK-NEXT:    jns .LBB11_2
242; CHECK-NEXT:  # %bb.1: # %t
243; CHECK-NEXT:    movw $42, %ax
244; CHECK-NEXT:  .LBB11_2: # %f
245; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
246; CHECK-NEXT:    retq
247entry:
248  %a = and i16 %x, 128
249  %r = icmp ne i16 %a, 0
250  br i1 %r, label %t, label %f
251t:
252  br label %f
253f:
254  %ret = phi i16 [ %x, %entry], [ 42, %t]
255  ret i16 %ret
256}
257
258define i16 @test_set_mask_i16_i7(i16 %x) nounwind {
259; CHECK-LABEL: test_set_mask_i16_i7:
260; CHECK:       # %bb.0: # %entry
261; CHECK-NEXT:    movl %edi, %eax
262; CHECK-NEXT:    testb $64, %al
263; CHECK-NEXT:    je .LBB12_2
264; CHECK-NEXT:  # %bb.1: # %t
265; CHECK-NEXT:    movw $42, %ax
266; CHECK-NEXT:  .LBB12_2: # %f
267; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
268; CHECK-NEXT:    retq
269entry:
270  %a = and i16 %x, 64
271  %r = icmp ne i16 %a, 0
272  br i1 %r, label %t, label %f
273t:
274  br label %f
275f:
276  %ret = phi i16 [ %x, %entry], [ 42, %t]
277  ret i16 %ret
278}
279