xref: /llvm-project/llvm/test/CodeGen/X86/scalar-int-to-fp.ll (revision e9f9467da063875bd684e46660e2ff36ba4f55e2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown-unknown     -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK32,AVX512_32,AVX512DQVL_32
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown   -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK64,AVX512_64
4; RUN: llc < %s -mtriple=i386-unknown-unknown     -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=CHECK32,AVX512_32,AVX512DQ_32
5; RUN: llc < %s -mtriple=x86_64-unknown-unknown   -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=CHECK64,AVX512_64
6; RUN: llc < %s -mtriple=i386-unknown-unknown     -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK32,AVX512_32,AVX512F_32
7; RUN: llc < %s -mtriple=x86_64-unknown-unknown   -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK64,AVX512_64
8; RUN: llc < %s -mtriple=i386-unknown-unknown     -mattr=+sse2    | FileCheck %s --check-prefixes=CHECK32,SSE_32,SSE2_32
9; RUN: llc < %s -mtriple=x86_64-unknown-unknown   -mattr=+sse2    | FileCheck %s --check-prefixes=CHECK64,SSE2_64
10; RUN: llc < %s -mtriple=i386-unknown-unknown     -mattr=+sse     | FileCheck %s --check-prefixes=CHECK32,SSE_32,SSE1_32
11; RUN: llc < %s -mtriple=i386-unknown-unknown     -mattr=-sse     | FileCheck %s --check-prefixes=CHECK32,X87
12
13; Verify that scalar integer conversions to FP compile successfully
14; (at one time long double failed with avx512f), and that reasonable
15; instruction sequences are selected based on subtarget features.
16
17define float @u32_to_f(i32 %a) nounwind {
18; AVX512_32-LABEL: u32_to_f:
19; AVX512_32:       # %bb.0:
20; AVX512_32-NEXT:    pushl %eax
21; AVX512_32-NEXT:    vcvtusi2ssl {{[0-9]+}}(%esp), %xmm0, %xmm0
22; AVX512_32-NEXT:    vmovss %xmm0, (%esp)
23; AVX512_32-NEXT:    flds (%esp)
24; AVX512_32-NEXT:    popl %eax
25; AVX512_32-NEXT:    retl
26;
27; AVX512_64-LABEL: u32_to_f:
28; AVX512_64:       # %bb.0:
29; AVX512_64-NEXT:    vcvtusi2ss %edi, %xmm0, %xmm0
30; AVX512_64-NEXT:    retq
31;
32; SSE2_32-LABEL: u32_to_f:
33; SSE2_32:       # %bb.0:
34; SSE2_32-NEXT:    pushl %eax
35; SSE2_32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
36; SSE2_32-NEXT:    orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
37; SSE2_32-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
38; SSE2_32-NEXT:    cvtsd2ss %xmm0, %xmm0
39; SSE2_32-NEXT:    movss %xmm0, (%esp)
40; SSE2_32-NEXT:    flds (%esp)
41; SSE2_32-NEXT:    popl %eax
42; SSE2_32-NEXT:    retl
43;
44; SSE2_64-LABEL: u32_to_f:
45; SSE2_64:       # %bb.0:
46; SSE2_64-NEXT:    movl %edi, %eax
47; SSE2_64-NEXT:    cvtsi2ss %rax, %xmm0
48; SSE2_64-NEXT:    retq
49;
50; SSE1_32-LABEL: u32_to_f:
51; SSE1_32:       # %bb.0:
52; SSE1_32-NEXT:    pushl %ebp
53; SSE1_32-NEXT:    movl %esp, %ebp
54; SSE1_32-NEXT:    andl $-8, %esp
55; SSE1_32-NEXT:    subl $16, %esp
56; SSE1_32-NEXT:    movl 8(%ebp), %eax
57; SSE1_32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
58; SSE1_32-NEXT:    movl $0, {{[0-9]+}}(%esp)
59; SSE1_32-NEXT:    fildll {{[0-9]+}}(%esp)
60; SSE1_32-NEXT:    fstps {{[0-9]+}}(%esp)
61; SSE1_32-NEXT:    flds {{[0-9]+}}(%esp)
62; SSE1_32-NEXT:    movl %ebp, %esp
63; SSE1_32-NEXT:    popl %ebp
64; SSE1_32-NEXT:    retl
65;
66; X87-LABEL: u32_to_f:
67; X87:       # %bb.0:
68; X87-NEXT:    pushl %ebp
69; X87-NEXT:    movl %esp, %ebp
70; X87-NEXT:    andl $-8, %esp
71; X87-NEXT:    subl $8, %esp
72; X87-NEXT:    movl 8(%ebp), %eax
73; X87-NEXT:    movl %eax, (%esp)
74; X87-NEXT:    movl $0, {{[0-9]+}}(%esp)
75; X87-NEXT:    fildll (%esp)
76; X87-NEXT:    movl %ebp, %esp
77; X87-NEXT:    popl %ebp
78; X87-NEXT:    retl
79  %r = uitofp i32 %a to float
80  ret float %r
81}
82
83define float @s32_to_f(i32 %a) nounwind {
84; AVX512_32-LABEL: s32_to_f:
85; AVX512_32:       # %bb.0:
86; AVX512_32-NEXT:    pushl %eax
87; AVX512_32-NEXT:    vcvtsi2ssl {{[0-9]+}}(%esp), %xmm0, %xmm0
88; AVX512_32-NEXT:    vmovss %xmm0, (%esp)
89; AVX512_32-NEXT:    flds (%esp)
90; AVX512_32-NEXT:    popl %eax
91; AVX512_32-NEXT:    retl
92;
93; AVX512_64-LABEL: s32_to_f:
94; AVX512_64:       # %bb.0:
95; AVX512_64-NEXT:    vcvtsi2ss %edi, %xmm0, %xmm0
96; AVX512_64-NEXT:    retq
97;
98; SSE_32-LABEL: s32_to_f:
99; SSE_32:       # %bb.0:
100; SSE_32-NEXT:    pushl %eax
101; SSE_32-NEXT:    cvtsi2ssl {{[0-9]+}}(%esp), %xmm0
102; SSE_32-NEXT:    movss %xmm0, (%esp)
103; SSE_32-NEXT:    flds (%esp)
104; SSE_32-NEXT:    popl %eax
105; SSE_32-NEXT:    retl
106;
107; SSE2_64-LABEL: s32_to_f:
108; SSE2_64:       # %bb.0:
109; SSE2_64-NEXT:    cvtsi2ss %edi, %xmm0
110; SSE2_64-NEXT:    retq
111;
112; X87-LABEL: s32_to_f:
113; X87:       # %bb.0:
114; X87-NEXT:    pushl %eax
115; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
116; X87-NEXT:    movl %eax, (%esp)
117; X87-NEXT:    fildl (%esp)
118; X87-NEXT:    popl %eax
119; X87-NEXT:    retl
120  %r = sitofp i32 %a to float
121  ret float %r
122}
123
124define double @u32_to_d(i32 %a) nounwind {
125; AVX512_32-LABEL: u32_to_d:
126; AVX512_32:       # %bb.0:
127; AVX512_32-NEXT:    pushl %ebp
128; AVX512_32-NEXT:    movl %esp, %ebp
129; AVX512_32-NEXT:    andl $-8, %esp
130; AVX512_32-NEXT:    subl $8, %esp
131; AVX512_32-NEXT:    vcvtusi2sdl 8(%ebp), %xmm0, %xmm0
132; AVX512_32-NEXT:    vmovsd %xmm0, (%esp)
133; AVX512_32-NEXT:    fldl (%esp)
134; AVX512_32-NEXT:    movl %ebp, %esp
135; AVX512_32-NEXT:    popl %ebp
136; AVX512_32-NEXT:    retl
137;
138; AVX512_64-LABEL: u32_to_d:
139; AVX512_64:       # %bb.0:
140; AVX512_64-NEXT:    vcvtusi2sd %edi, %xmm0, %xmm0
141; AVX512_64-NEXT:    retq
142;
143; SSE2_32-LABEL: u32_to_d:
144; SSE2_32:       # %bb.0:
145; SSE2_32-NEXT:    pushl %ebp
146; SSE2_32-NEXT:    movl %esp, %ebp
147; SSE2_32-NEXT:    andl $-8, %esp
148; SSE2_32-NEXT:    subl $8, %esp
149; SSE2_32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
150; SSE2_32-NEXT:    orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
151; SSE2_32-NEXT:    subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
152; SSE2_32-NEXT:    movsd %xmm0, (%esp)
153; SSE2_32-NEXT:    fldl (%esp)
154; SSE2_32-NEXT:    movl %ebp, %esp
155; SSE2_32-NEXT:    popl %ebp
156; SSE2_32-NEXT:    retl
157;
158; SSE2_64-LABEL: u32_to_d:
159; SSE2_64:       # %bb.0:
160; SSE2_64-NEXT:    movl %edi, %eax
161; SSE2_64-NEXT:    cvtsi2sd %rax, %xmm0
162; SSE2_64-NEXT:    retq
163;
164; SSE1_32-LABEL: u32_to_d:
165; SSE1_32:       # %bb.0:
166; SSE1_32-NEXT:    pushl %ebp
167; SSE1_32-NEXT:    movl %esp, %ebp
168; SSE1_32-NEXT:    andl $-8, %esp
169; SSE1_32-NEXT:    subl $8, %esp
170; SSE1_32-NEXT:    movl 8(%ebp), %eax
171; SSE1_32-NEXT:    movl %eax, (%esp)
172; SSE1_32-NEXT:    movl $0, {{[0-9]+}}(%esp)
173; SSE1_32-NEXT:    fildll (%esp)
174; SSE1_32-NEXT:    movl %ebp, %esp
175; SSE1_32-NEXT:    popl %ebp
176; SSE1_32-NEXT:    retl
177;
178; X87-LABEL: u32_to_d:
179; X87:       # %bb.0:
180; X87-NEXT:    pushl %ebp
181; X87-NEXT:    movl %esp, %ebp
182; X87-NEXT:    andl $-8, %esp
183; X87-NEXT:    subl $8, %esp
184; X87-NEXT:    movl 8(%ebp), %eax
185; X87-NEXT:    movl %eax, (%esp)
186; X87-NEXT:    movl $0, {{[0-9]+}}(%esp)
187; X87-NEXT:    fildll (%esp)
188; X87-NEXT:    movl %ebp, %esp
189; X87-NEXT:    popl %ebp
190; X87-NEXT:    retl
191  %r = uitofp i32 %a to double
192  ret double %r
193}
194
195define double @s32_to_d(i32 %a) nounwind {
196; AVX512_32-LABEL: s32_to_d:
197; AVX512_32:       # %bb.0:
198; AVX512_32-NEXT:    pushl %ebp
199; AVX512_32-NEXT:    movl %esp, %ebp
200; AVX512_32-NEXT:    andl $-8, %esp
201; AVX512_32-NEXT:    subl $8, %esp
202; AVX512_32-NEXT:    vcvtsi2sdl 8(%ebp), %xmm0, %xmm0
203; AVX512_32-NEXT:    vmovsd %xmm0, (%esp)
204; AVX512_32-NEXT:    fldl (%esp)
205; AVX512_32-NEXT:    movl %ebp, %esp
206; AVX512_32-NEXT:    popl %ebp
207; AVX512_32-NEXT:    retl
208;
209; AVX512_64-LABEL: s32_to_d:
210; AVX512_64:       # %bb.0:
211; AVX512_64-NEXT:    vcvtsi2sd %edi, %xmm0, %xmm0
212; AVX512_64-NEXT:    retq
213;
214; SSE2_32-LABEL: s32_to_d:
215; SSE2_32:       # %bb.0:
216; SSE2_32-NEXT:    pushl %ebp
217; SSE2_32-NEXT:    movl %esp, %ebp
218; SSE2_32-NEXT:    andl $-8, %esp
219; SSE2_32-NEXT:    subl $8, %esp
220; SSE2_32-NEXT:    cvtsi2sdl 8(%ebp), %xmm0
221; SSE2_32-NEXT:    movsd %xmm0, (%esp)
222; SSE2_32-NEXT:    fldl (%esp)
223; SSE2_32-NEXT:    movl %ebp, %esp
224; SSE2_32-NEXT:    popl %ebp
225; SSE2_32-NEXT:    retl
226;
227; SSE2_64-LABEL: s32_to_d:
228; SSE2_64:       # %bb.0:
229; SSE2_64-NEXT:    cvtsi2sd %edi, %xmm0
230; SSE2_64-NEXT:    retq
231;
232; SSE1_32-LABEL: s32_to_d:
233; SSE1_32:       # %bb.0:
234; SSE1_32-NEXT:    pushl %eax
235; SSE1_32-NEXT:    movl {{[0-9]+}}(%esp), %eax
236; SSE1_32-NEXT:    movl %eax, (%esp)
237; SSE1_32-NEXT:    fildl (%esp)
238; SSE1_32-NEXT:    popl %eax
239; SSE1_32-NEXT:    retl
240;
241; X87-LABEL: s32_to_d:
242; X87:       # %bb.0:
243; X87-NEXT:    pushl %eax
244; X87-NEXT:    movl {{[0-9]+}}(%esp), %eax
245; X87-NEXT:    movl %eax, (%esp)
246; X87-NEXT:    fildl (%esp)
247; X87-NEXT:    popl %eax
248; X87-NEXT:    retl
249  %r = sitofp i32 %a to double
250  ret double %r
251}
252
253define x86_fp80 @u32_to_x(i32 %a) nounwind {
254; CHECK32-LABEL: u32_to_x:
255; CHECK32:       # %bb.0:
256; CHECK32-NEXT:    pushl %ebp
257; CHECK32-NEXT:    movl %esp, %ebp
258; CHECK32-NEXT:    andl $-8, %esp
259; CHECK32-NEXT:    subl $8, %esp
260; CHECK32-NEXT:    movl 8(%ebp), %eax
261; CHECK32-NEXT:    movl %eax, (%esp)
262; CHECK32-NEXT:    movl $0, {{[0-9]+}}(%esp)
263; CHECK32-NEXT:    fildll (%esp)
264; CHECK32-NEXT:    movl %ebp, %esp
265; CHECK32-NEXT:    popl %ebp
266; CHECK32-NEXT:    retl
267;
268; CHECK64-LABEL: u32_to_x:
269; CHECK64:       # %bb.0:
270; CHECK64-NEXT:    movl %edi, %eax
271; CHECK64-NEXT:    movq %rax, -{{[0-9]+}}(%rsp)
272; CHECK64-NEXT:    fildll -{{[0-9]+}}(%rsp)
273; CHECK64-NEXT:    retq
274  %r = uitofp i32 %a to x86_fp80
275  ret x86_fp80 %r
276}
277
278define x86_fp80 @s32_to_x(i32 %a) nounwind {
279; CHECK32-LABEL: s32_to_x:
280; CHECK32:       # %bb.0:
281; CHECK32-NEXT:    pushl %eax
282; CHECK32-NEXT:    movl {{[0-9]+}}(%esp), %eax
283; CHECK32-NEXT:    movl %eax, (%esp)
284; CHECK32-NEXT:    fildl (%esp)
285; CHECK32-NEXT:    popl %eax
286; CHECK32-NEXT:    retl
287;
288; CHECK64-LABEL: s32_to_x:
289; CHECK64:       # %bb.0:
290; CHECK64-NEXT:    movl %edi, -{{[0-9]+}}(%rsp)
291; CHECK64-NEXT:    fildl -{{[0-9]+}}(%rsp)
292; CHECK64-NEXT:    retq
293  %r = sitofp i32 %a to x86_fp80
294  ret x86_fp80 %r
295}
296
297define float @u64_to_f(i64 %a) nounwind {
298; AVX512DQVL_32-LABEL: u64_to_f:
299; AVX512DQVL_32:       # %bb.0:
300; AVX512DQVL_32-NEXT:    pushl %eax
301; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
302; AVX512DQVL_32-NEXT:    vcvtuqq2ps %ymm0, %xmm0
303; AVX512DQVL_32-NEXT:    vmovss %xmm0, (%esp)
304; AVX512DQVL_32-NEXT:    flds (%esp)
305; AVX512DQVL_32-NEXT:    popl %eax
306; AVX512DQVL_32-NEXT:    vzeroupper
307; AVX512DQVL_32-NEXT:    retl
308;
309; AVX512_64-LABEL: u64_to_f:
310; AVX512_64:       # %bb.0:
311; AVX512_64-NEXT:    vcvtusi2ss %rdi, %xmm0, %xmm0
312; AVX512_64-NEXT:    retq
313;
314; AVX512DQ_32-LABEL: u64_to_f:
315; AVX512DQ_32:       # %bb.0:
316; AVX512DQ_32-NEXT:    pushl %eax
317; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
318; AVX512DQ_32-NEXT:    vcvtuqq2ps %zmm0, %ymm0
319; AVX512DQ_32-NEXT:    vmovss %xmm0, (%esp)
320; AVX512DQ_32-NEXT:    flds (%esp)
321; AVX512DQ_32-NEXT:    popl %eax
322; AVX512DQ_32-NEXT:    vzeroupper
323; AVX512DQ_32-NEXT:    retl
324;
325; AVX512F_32-LABEL: u64_to_f:
326; AVX512F_32:       # %bb.0:
327; AVX512F_32-NEXT:    pushl %ebp
328; AVX512F_32-NEXT:    movl %esp, %ebp
329; AVX512F_32-NEXT:    andl $-8, %esp
330; AVX512F_32-NEXT:    subl $16, %esp
331; AVX512F_32-NEXT:    movl 12(%ebp), %eax
332; AVX512F_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
333; AVX512F_32-NEXT:    vmovlps %xmm0, {{[0-9]+}}(%esp)
334; AVX512F_32-NEXT:    shrl $31, %eax
335; AVX512F_32-NEXT:    fildll {{[0-9]+}}(%esp)
336; AVX512F_32-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
337; AVX512F_32-NEXT:    fstps {{[0-9]+}}(%esp)
338; AVX512F_32-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
339; AVX512F_32-NEXT:    vmovss %xmm0, (%esp)
340; AVX512F_32-NEXT:    flds (%esp)
341; AVX512F_32-NEXT:    movl %ebp, %esp
342; AVX512F_32-NEXT:    popl %ebp
343; AVX512F_32-NEXT:    retl
344;
345; SSE2_32-LABEL: u64_to_f:
346; SSE2_32:       # %bb.0:
347; SSE2_32-NEXT:    pushl %ebp
348; SSE2_32-NEXT:    movl %esp, %ebp
349; SSE2_32-NEXT:    andl $-8, %esp
350; SSE2_32-NEXT:    subl $16, %esp
351; SSE2_32-NEXT:    movl 12(%ebp), %eax
352; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
353; SSE2_32-NEXT:    movlps %xmm0, {{[0-9]+}}(%esp)
354; SSE2_32-NEXT:    shrl $31, %eax
355; SSE2_32-NEXT:    fildll {{[0-9]+}}(%esp)
356; SSE2_32-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%eax,4)
357; SSE2_32-NEXT:    fstps {{[0-9]+}}(%esp)
358; SSE2_32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
359; SSE2_32-NEXT:    movss %xmm0, (%esp)
360; SSE2_32-NEXT:    flds (%esp)
361; SSE2_32-NEXT:    movl %ebp, %esp
362; SSE2_32-NEXT:    popl %ebp
363; SSE2_32-NEXT:    retl
364;
365; SSE2_64-LABEL: u64_to_f:
366; SSE2_64:       # %bb.0:
367; SSE2_64-NEXT:    testq %rdi, %rdi
368; SSE2_64-NEXT:    js .LBB6_1
369; SSE2_64-NEXT:  # %bb.2:
370; SSE2_64-NEXT:    cvtsi2ss %rdi, %xmm0
371; SSE2_64-NEXT:    retq
372; SSE2_64-NEXT:  .LBB6_1:
373; SSE2_64-NEXT:    movq %rdi, %rax
374; SSE2_64-NEXT:    shrq %rax
375; SSE2_64-NEXT:    andl $1, %edi
376; SSE2_64-NEXT:    orq %rax, %rdi
377; SSE2_64-NEXT:    cvtsi2ss %rdi, %xmm0
378; SSE2_64-NEXT:    addss %xmm0, %xmm0
379; SSE2_64-NEXT:    retq
380;
381; SSE1_32-LABEL: u64_to_f:
382; SSE1_32:       # %bb.0:
383; SSE1_32-NEXT:    pushl %ebp
384; SSE1_32-NEXT:    movl %esp, %ebp
385; SSE1_32-NEXT:    andl $-8, %esp
386; SSE1_32-NEXT:    subl $24, %esp
387; SSE1_32-NEXT:    movl 8(%ebp), %eax
388; SSE1_32-NEXT:    movl 12(%ebp), %ecx
389; SSE1_32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
390; SSE1_32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
391; SSE1_32-NEXT:    fldl {{[0-9]+}}(%esp)
392; SSE1_32-NEXT:    fstpl {{[0-9]+}}(%esp)
393; SSE1_32-NEXT:    shrl $31, %ecx
394; SSE1_32-NEXT:    fildll {{[0-9]+}}(%esp)
395; SSE1_32-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
396; SSE1_32-NEXT:    fstps {{[0-9]+}}(%esp)
397; SSE1_32-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
398; SSE1_32-NEXT:    movss %xmm0, (%esp)
399; SSE1_32-NEXT:    flds (%esp)
400; SSE1_32-NEXT:    movl %ebp, %esp
401; SSE1_32-NEXT:    popl %ebp
402; SSE1_32-NEXT:    retl
403;
404; X87-LABEL: u64_to_f:
405; X87:       # %bb.0:
406; X87-NEXT:    pushl %ebp
407; X87-NEXT:    movl %esp, %ebp
408; X87-NEXT:    andl $-8, %esp
409; X87-NEXT:    subl $16, %esp
410; X87-NEXT:    movl 8(%ebp), %eax
411; X87-NEXT:    movl 12(%ebp), %ecx
412; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
413; X87-NEXT:    movl %eax, {{[0-9]+}}(%esp)
414; X87-NEXT:    shrl $31, %ecx
415; X87-NEXT:    fildll {{[0-9]+}}(%esp)
416; X87-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
417; X87-NEXT:    fstps {{[0-9]+}}(%esp)
418; X87-NEXT:    flds {{[0-9]+}}(%esp)
419; X87-NEXT:    movl %ebp, %esp
420; X87-NEXT:    popl %ebp
421; X87-NEXT:    retl
422  %r = uitofp i64 %a to float
423  ret float %r
424}
425
426define float @s64_to_f(i64 %a) nounwind {
427; AVX512DQVL_32-LABEL: s64_to_f:
428; AVX512DQVL_32:       # %bb.0:
429; AVX512DQVL_32-NEXT:    pushl %eax
430; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
431; AVX512DQVL_32-NEXT:    vcvtqq2ps %ymm0, %xmm0
432; AVX512DQVL_32-NEXT:    vmovss %xmm0, (%esp)
433; AVX512DQVL_32-NEXT:    flds (%esp)
434; AVX512DQVL_32-NEXT:    popl %eax
435; AVX512DQVL_32-NEXT:    vzeroupper
436; AVX512DQVL_32-NEXT:    retl
437;
438; AVX512_64-LABEL: s64_to_f:
439; AVX512_64:       # %bb.0:
440; AVX512_64-NEXT:    vcvtsi2ss %rdi, %xmm0, %xmm0
441; AVX512_64-NEXT:    retq
442;
443; AVX512DQ_32-LABEL: s64_to_f:
444; AVX512DQ_32:       # %bb.0:
445; AVX512DQ_32-NEXT:    pushl %eax
446; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
447; AVX512DQ_32-NEXT:    vcvtqq2ps %zmm0, %ymm0
448; AVX512DQ_32-NEXT:    vmovss %xmm0, (%esp)
449; AVX512DQ_32-NEXT:    flds (%esp)
450; AVX512DQ_32-NEXT:    popl %eax
451; AVX512DQ_32-NEXT:    vzeroupper
452; AVX512DQ_32-NEXT:    retl
453;
454; AVX512F_32-LABEL: s64_to_f:
455; AVX512F_32:       # %bb.0:
456; AVX512F_32-NEXT:    pushl %eax
457; AVX512F_32-NEXT:    fildll {{[0-9]+}}(%esp)
458; AVX512F_32-NEXT:    fstps (%esp)
459; AVX512F_32-NEXT:    flds (%esp)
460; AVX512F_32-NEXT:    popl %eax
461; AVX512F_32-NEXT:    retl
462;
463; SSE_32-LABEL: s64_to_f:
464; SSE_32:       # %bb.0:
465; SSE_32-NEXT:    pushl %eax
466; SSE_32-NEXT:    fildll {{[0-9]+}}(%esp)
467; SSE_32-NEXT:    fstps (%esp)
468; SSE_32-NEXT:    flds (%esp)
469; SSE_32-NEXT:    popl %eax
470; SSE_32-NEXT:    retl
471;
472; SSE2_64-LABEL: s64_to_f:
473; SSE2_64:       # %bb.0:
474; SSE2_64-NEXT:    cvtsi2ss %rdi, %xmm0
475; SSE2_64-NEXT:    retq
476;
477; X87-LABEL: s64_to_f:
478; X87:       # %bb.0:
479; X87-NEXT:    fildll {{[0-9]+}}(%esp)
480; X87-NEXT:    retl
481  %r = sitofp i64 %a to float
482  ret float %r
483}
484
485define float @s64_to_f_2(i64 %a) nounwind {
486; AVX512DQVL_32-LABEL: s64_to_f_2:
487; AVX512DQVL_32:       # %bb.0:
488; AVX512DQVL_32-NEXT:    pushl %eax
489; AVX512DQVL_32-NEXT:    movl {{[0-9]+}}(%esp), %eax
490; AVX512DQVL_32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
491; AVX512DQVL_32-NEXT:    addl $5, %eax
492; AVX512DQVL_32-NEXT:    adcl $0, %ecx
493; AVX512DQVL_32-NEXT:    vmovd %eax, %xmm0
494; AVX512DQVL_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
495; AVX512DQVL_32-NEXT:    vcvtqq2ps %ymm0, %xmm0
496; AVX512DQVL_32-NEXT:    vmovss %xmm0, (%esp)
497; AVX512DQVL_32-NEXT:    flds (%esp)
498; AVX512DQVL_32-NEXT:    popl %eax
499; AVX512DQVL_32-NEXT:    vzeroupper
500; AVX512DQVL_32-NEXT:    retl
501;
502; AVX512_64-LABEL: s64_to_f_2:
503; AVX512_64:       # %bb.0:
504; AVX512_64-NEXT:    addq $5, %rdi
505; AVX512_64-NEXT:    vcvtsi2ss %rdi, %xmm0, %xmm0
506; AVX512_64-NEXT:    retq
507;
508; AVX512DQ_32-LABEL: s64_to_f_2:
509; AVX512DQ_32:       # %bb.0:
510; AVX512DQ_32-NEXT:    pushl %eax
511; AVX512DQ_32-NEXT:    movl {{[0-9]+}}(%esp), %eax
512; AVX512DQ_32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
513; AVX512DQ_32-NEXT:    addl $5, %eax
514; AVX512DQ_32-NEXT:    adcl $0, %ecx
515; AVX512DQ_32-NEXT:    vmovd %eax, %xmm0
516; AVX512DQ_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
517; AVX512DQ_32-NEXT:    vcvtqq2ps %zmm0, %ymm0
518; AVX512DQ_32-NEXT:    vmovss %xmm0, (%esp)
519; AVX512DQ_32-NEXT:    flds (%esp)
520; AVX512DQ_32-NEXT:    popl %eax
521; AVX512DQ_32-NEXT:    vzeroupper
522; AVX512DQ_32-NEXT:    retl
523;
524; AVX512F_32-LABEL: s64_to_f_2:
525; AVX512F_32:       # %bb.0:
526; AVX512F_32-NEXT:    pushl %ebp
527; AVX512F_32-NEXT:    movl %esp, %ebp
528; AVX512F_32-NEXT:    andl $-8, %esp
529; AVX512F_32-NEXT:    subl $16, %esp
530; AVX512F_32-NEXT:    movl 8(%ebp), %eax
531; AVX512F_32-NEXT:    movl 12(%ebp), %ecx
532; AVX512F_32-NEXT:    addl $5, %eax
533; AVX512F_32-NEXT:    adcl $0, %ecx
534; AVX512F_32-NEXT:    vmovd %eax, %xmm0
535; AVX512F_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
536; AVX512F_32-NEXT:    vmovq %xmm0, {{[0-9]+}}(%esp)
537; AVX512F_32-NEXT:    fildll {{[0-9]+}}(%esp)
538; AVX512F_32-NEXT:    fstps {{[0-9]+}}(%esp)
539; AVX512F_32-NEXT:    flds {{[0-9]+}}(%esp)
540; AVX512F_32-NEXT:    movl %ebp, %esp
541; AVX512F_32-NEXT:    popl %ebp
542; AVX512F_32-NEXT:    retl
543;
544; SSE2_32-LABEL: s64_to_f_2:
545; SSE2_32:       # %bb.0:
546; SSE2_32-NEXT:    pushl %ebp
547; SSE2_32-NEXT:    movl %esp, %ebp
548; SSE2_32-NEXT:    andl $-8, %esp
549; SSE2_32-NEXT:    subl $16, %esp
550; SSE2_32-NEXT:    movl 8(%ebp), %eax
551; SSE2_32-NEXT:    movl 12(%ebp), %ecx
552; SSE2_32-NEXT:    addl $5, %eax
553; SSE2_32-NEXT:    adcl $0, %ecx
554; SSE2_32-NEXT:    movd %ecx, %xmm0
555; SSE2_32-NEXT:    movd %eax, %xmm1
556; SSE2_32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
557; SSE2_32-NEXT:    movq %xmm1, {{[0-9]+}}(%esp)
558; SSE2_32-NEXT:    fildll {{[0-9]+}}(%esp)
559; SSE2_32-NEXT:    fstps {{[0-9]+}}(%esp)
560; SSE2_32-NEXT:    flds {{[0-9]+}}(%esp)
561; SSE2_32-NEXT:    movl %ebp, %esp
562; SSE2_32-NEXT:    popl %ebp
563; SSE2_32-NEXT:    retl
564;
565; SSE2_64-LABEL: s64_to_f_2:
566; SSE2_64:       # %bb.0:
567; SSE2_64-NEXT:    addq $5, %rdi
568; SSE2_64-NEXT:    cvtsi2ss %rdi, %xmm0
569; SSE2_64-NEXT:    retq
570;
571; SSE1_32-LABEL: s64_to_f_2:
572; SSE1_32:       # %bb.0:
573; SSE1_32-NEXT:    pushl %ebp
574; SSE1_32-NEXT:    movl %esp, %ebp
575; SSE1_32-NEXT:    andl $-8, %esp
576; SSE1_32-NEXT:    subl $16, %esp
577; SSE1_32-NEXT:    movl 8(%ebp), %eax
578; SSE1_32-NEXT:    movl 12(%ebp), %ecx
579; SSE1_32-NEXT:    addl $5, %eax
580; SSE1_32-NEXT:    adcl $0, %ecx
581; SSE1_32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
582; SSE1_32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
583; SSE1_32-NEXT:    fildll {{[0-9]+}}(%esp)
584; SSE1_32-NEXT:    fstps {{[0-9]+}}(%esp)
585; SSE1_32-NEXT:    flds {{[0-9]+}}(%esp)
586; SSE1_32-NEXT:    movl %ebp, %esp
587; SSE1_32-NEXT:    popl %ebp
588; SSE1_32-NEXT:    retl
589;
590; X87-LABEL: s64_to_f_2:
591; X87:       # %bb.0:
592; X87-NEXT:    pushl %ebp
593; X87-NEXT:    movl %esp, %ebp
594; X87-NEXT:    andl $-8, %esp
595; X87-NEXT:    subl $8, %esp
596; X87-NEXT:    movl 8(%ebp), %eax
597; X87-NEXT:    movl 12(%ebp), %ecx
598; X87-NEXT:    addl $5, %eax
599; X87-NEXT:    adcl $0, %ecx
600; X87-NEXT:    movl %eax, (%esp)
601; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
602; X87-NEXT:    fildll (%esp)
603; X87-NEXT:    movl %ebp, %esp
604; X87-NEXT:    popl %ebp
605; X87-NEXT:    retl
606  %a1 = add i64 %a, 5
607  %r = sitofp i64 %a1 to float
608  ret float %r
609}
610
611define double @u64_to_d(i64 %a) nounwind {
612; AVX512DQVL_32-LABEL: u64_to_d:
613; AVX512DQVL_32:       # %bb.0:
614; AVX512DQVL_32-NEXT:    pushl %ebp
615; AVX512DQVL_32-NEXT:    movl %esp, %ebp
616; AVX512DQVL_32-NEXT:    andl $-8, %esp
617; AVX512DQVL_32-NEXT:    subl $8, %esp
618; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
619; AVX512DQVL_32-NEXT:    vcvtuqq2pd %ymm0, %ymm0
620; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
621; AVX512DQVL_32-NEXT:    fldl (%esp)
622; AVX512DQVL_32-NEXT:    movl %ebp, %esp
623; AVX512DQVL_32-NEXT:    popl %ebp
624; AVX512DQVL_32-NEXT:    vzeroupper
625; AVX512DQVL_32-NEXT:    retl
626;
627; AVX512_64-LABEL: u64_to_d:
628; AVX512_64:       # %bb.0:
629; AVX512_64-NEXT:    vcvtusi2sd %rdi, %xmm0, %xmm0
630; AVX512_64-NEXT:    retq
631;
632; AVX512DQ_32-LABEL: u64_to_d:
633; AVX512DQ_32:       # %bb.0:
634; AVX512DQ_32-NEXT:    pushl %ebp
635; AVX512DQ_32-NEXT:    movl %esp, %ebp
636; AVX512DQ_32-NEXT:    andl $-8, %esp
637; AVX512DQ_32-NEXT:    subl $8, %esp
638; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
639; AVX512DQ_32-NEXT:    vcvtuqq2pd %zmm0, %zmm0
640; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
641; AVX512DQ_32-NEXT:    fldl (%esp)
642; AVX512DQ_32-NEXT:    movl %ebp, %esp
643; AVX512DQ_32-NEXT:    popl %ebp
644; AVX512DQ_32-NEXT:    vzeroupper
645; AVX512DQ_32-NEXT:    retl
646;
647; AVX512F_32-LABEL: u64_to_d:
648; AVX512F_32:       # %bb.0:
649; AVX512F_32-NEXT:    pushl %ebp
650; AVX512F_32-NEXT:    movl %esp, %ebp
651; AVX512F_32-NEXT:    andl $-8, %esp
652; AVX512F_32-NEXT:    subl $8, %esp
653; AVX512F_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
654; AVX512F_32-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
655; AVX512F_32-NEXT:    vsubpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
656; AVX512F_32-NEXT:    vshufpd {{.*#+}} xmm1 = xmm0[1,0]
657; AVX512F_32-NEXT:    vaddsd %xmm0, %xmm1, %xmm0
658; AVX512F_32-NEXT:    vmovsd %xmm0, (%esp)
659; AVX512F_32-NEXT:    fldl (%esp)
660; AVX512F_32-NEXT:    movl %ebp, %esp
661; AVX512F_32-NEXT:    popl %ebp
662; AVX512F_32-NEXT:    retl
663;
664; SSE2_32-LABEL: u64_to_d:
665; SSE2_32:       # %bb.0:
666; SSE2_32-NEXT:    pushl %ebp
667; SSE2_32-NEXT:    movl %esp, %ebp
668; SSE2_32-NEXT:    andl $-8, %esp
669; SSE2_32-NEXT:    subl $8, %esp
670; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
671; SSE2_32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
672; SSE2_32-NEXT:    subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
673; SSE2_32-NEXT:    movapd %xmm0, %xmm1
674; SSE2_32-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
675; SSE2_32-NEXT:    addsd %xmm0, %xmm1
676; SSE2_32-NEXT:    movsd %xmm1, (%esp)
677; SSE2_32-NEXT:    fldl (%esp)
678; SSE2_32-NEXT:    movl %ebp, %esp
679; SSE2_32-NEXT:    popl %ebp
680; SSE2_32-NEXT:    retl
681;
682; SSE2_64-LABEL: u64_to_d:
683; SSE2_64:       # %bb.0:
684; SSE2_64-NEXT:    movq %rdi, %xmm1
685; SSE2_64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
686; SSE2_64-NEXT:    subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
687; SSE2_64-NEXT:    movapd %xmm1, %xmm0
688; SSE2_64-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
689; SSE2_64-NEXT:    addsd %xmm1, %xmm0
690; SSE2_64-NEXT:    retq
691;
692; SSE1_32-LABEL: u64_to_d:
693; SSE1_32:       # %bb.0:
694; SSE1_32-NEXT:    pushl %ebp
695; SSE1_32-NEXT:    movl %esp, %ebp
696; SSE1_32-NEXT:    andl $-8, %esp
697; SSE1_32-NEXT:    subl $16, %esp
698; SSE1_32-NEXT:    movl 8(%ebp), %eax
699; SSE1_32-NEXT:    movl 12(%ebp), %ecx
700; SSE1_32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
701; SSE1_32-NEXT:    movl %eax, (%esp)
702; SSE1_32-NEXT:    shrl $31, %ecx
703; SSE1_32-NEXT:    fildll (%esp)
704; SSE1_32-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
705; SSE1_32-NEXT:    fstpl {{[0-9]+}}(%esp)
706; SSE1_32-NEXT:    fldl {{[0-9]+}}(%esp)
707; SSE1_32-NEXT:    movl %ebp, %esp
708; SSE1_32-NEXT:    popl %ebp
709; SSE1_32-NEXT:    retl
710;
711; X87-LABEL: u64_to_d:
712; X87:       # %bb.0:
713; X87-NEXT:    pushl %ebp
714; X87-NEXT:    movl %esp, %ebp
715; X87-NEXT:    andl $-8, %esp
716; X87-NEXT:    subl $16, %esp
717; X87-NEXT:    movl 8(%ebp), %eax
718; X87-NEXT:    movl 12(%ebp), %ecx
719; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
720; X87-NEXT:    movl %eax, (%esp)
721; X87-NEXT:    shrl $31, %ecx
722; X87-NEXT:    fildll (%esp)
723; X87-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
724; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
725; X87-NEXT:    fldl {{[0-9]+}}(%esp)
726; X87-NEXT:    movl %ebp, %esp
727; X87-NEXT:    popl %ebp
728; X87-NEXT:    retl
729  %r = uitofp i64 %a to double
730  ret double %r
731}
732
733define double @u64_to_d_optsize(i64 %a) nounwind optsize {
734; AVX512DQVL_32-LABEL: u64_to_d_optsize:
735; AVX512DQVL_32:       # %bb.0:
736; AVX512DQVL_32-NEXT:    pushl %ebp
737; AVX512DQVL_32-NEXT:    movl %esp, %ebp
738; AVX512DQVL_32-NEXT:    andl $-8, %esp
739; AVX512DQVL_32-NEXT:    subl $8, %esp
740; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
741; AVX512DQVL_32-NEXT:    vcvtuqq2pd %ymm0, %ymm0
742; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
743; AVX512DQVL_32-NEXT:    fldl (%esp)
744; AVX512DQVL_32-NEXT:    movl %ebp, %esp
745; AVX512DQVL_32-NEXT:    popl %ebp
746; AVX512DQVL_32-NEXT:    vzeroupper
747; AVX512DQVL_32-NEXT:    retl
748;
749; AVX512_64-LABEL: u64_to_d_optsize:
750; AVX512_64:       # %bb.0:
751; AVX512_64-NEXT:    vcvtusi2sd %rdi, %xmm0, %xmm0
752; AVX512_64-NEXT:    retq
753;
754; AVX512DQ_32-LABEL: u64_to_d_optsize:
755; AVX512DQ_32:       # %bb.0:
756; AVX512DQ_32-NEXT:    pushl %ebp
757; AVX512DQ_32-NEXT:    movl %esp, %ebp
758; AVX512DQ_32-NEXT:    andl $-8, %esp
759; AVX512DQ_32-NEXT:    subl $8, %esp
760; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
761; AVX512DQ_32-NEXT:    vcvtuqq2pd %zmm0, %zmm0
762; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
763; AVX512DQ_32-NEXT:    fldl (%esp)
764; AVX512DQ_32-NEXT:    movl %ebp, %esp
765; AVX512DQ_32-NEXT:    popl %ebp
766; AVX512DQ_32-NEXT:    vzeroupper
767; AVX512DQ_32-NEXT:    retl
768;
769; AVX512F_32-LABEL: u64_to_d_optsize:
770; AVX512F_32:       # %bb.0:
771; AVX512F_32-NEXT:    pushl %ebp
772; AVX512F_32-NEXT:    movl %esp, %ebp
773; AVX512F_32-NEXT:    andl $-8, %esp
774; AVX512F_32-NEXT:    subl $8, %esp
775; AVX512F_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
776; AVX512F_32-NEXT:    vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
777; AVX512F_32-NEXT:    vsubpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
778; AVX512F_32-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
779; AVX512F_32-NEXT:    vmovlpd %xmm0, (%esp)
780; AVX512F_32-NEXT:    fldl (%esp)
781; AVX512F_32-NEXT:    movl %ebp, %esp
782; AVX512F_32-NEXT:    popl %ebp
783; AVX512F_32-NEXT:    retl
784;
785; SSE2_32-LABEL: u64_to_d_optsize:
786; SSE2_32:       # %bb.0:
787; SSE2_32-NEXT:    pushl %ebp
788; SSE2_32-NEXT:    movl %esp, %ebp
789; SSE2_32-NEXT:    andl $-8, %esp
790; SSE2_32-NEXT:    subl $8, %esp
791; SSE2_32-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
792; SSE2_32-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
793; SSE2_32-NEXT:    subpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
794; SSE2_32-NEXT:    movapd %xmm0, %xmm1
795; SSE2_32-NEXT:    unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
796; SSE2_32-NEXT:    addsd %xmm0, %xmm1
797; SSE2_32-NEXT:    movsd %xmm1, (%esp)
798; SSE2_32-NEXT:    fldl (%esp)
799; SSE2_32-NEXT:    movl %ebp, %esp
800; SSE2_32-NEXT:    popl %ebp
801; SSE2_32-NEXT:    retl
802;
803; SSE2_64-LABEL: u64_to_d_optsize:
804; SSE2_64:       # %bb.0:
805; SSE2_64-NEXT:    movq %rdi, %xmm1
806; SSE2_64-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
807; SSE2_64-NEXT:    subpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
808; SSE2_64-NEXT:    movapd %xmm1, %xmm0
809; SSE2_64-NEXT:    unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
810; SSE2_64-NEXT:    addsd %xmm1, %xmm0
811; SSE2_64-NEXT:    retq
812;
813; SSE1_32-LABEL: u64_to_d_optsize:
814; SSE1_32:       # %bb.0:
815; SSE1_32-NEXT:    pushl %ebp
816; SSE1_32-NEXT:    movl %esp, %ebp
817; SSE1_32-NEXT:    andl $-8, %esp
818; SSE1_32-NEXT:    subl $16, %esp
819; SSE1_32-NEXT:    movl 8(%ebp), %eax
820; SSE1_32-NEXT:    movl 12(%ebp), %ecx
821; SSE1_32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
822; SSE1_32-NEXT:    movl %eax, (%esp)
823; SSE1_32-NEXT:    shrl $31, %ecx
824; SSE1_32-NEXT:    fildll (%esp)
825; SSE1_32-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
826; SSE1_32-NEXT:    fstpl {{[0-9]+}}(%esp)
827; SSE1_32-NEXT:    fldl {{[0-9]+}}(%esp)
828; SSE1_32-NEXT:    movl %ebp, %esp
829; SSE1_32-NEXT:    popl %ebp
830; SSE1_32-NEXT:    retl
831;
832; X87-LABEL: u64_to_d_optsize:
833; X87:       # %bb.0:
834; X87-NEXT:    pushl %ebp
835; X87-NEXT:    movl %esp, %ebp
836; X87-NEXT:    andl $-8, %esp
837; X87-NEXT:    subl $16, %esp
838; X87-NEXT:    movl 8(%ebp), %eax
839; X87-NEXT:    movl 12(%ebp), %ecx
840; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
841; X87-NEXT:    movl %eax, (%esp)
842; X87-NEXT:    shrl $31, %ecx
843; X87-NEXT:    fildll (%esp)
844; X87-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
845; X87-NEXT:    fstpl {{[0-9]+}}(%esp)
846; X87-NEXT:    fldl {{[0-9]+}}(%esp)
847; X87-NEXT:    movl %ebp, %esp
848; X87-NEXT:    popl %ebp
849; X87-NEXT:    retl
850  %r = uitofp i64 %a to double
851  ret double %r
852}
853
854define double @s64_to_d(i64 %a) nounwind {
855; AVX512DQVL_32-LABEL: s64_to_d:
856; AVX512DQVL_32:       # %bb.0:
857; AVX512DQVL_32-NEXT:    pushl %ebp
858; AVX512DQVL_32-NEXT:    movl %esp, %ebp
859; AVX512DQVL_32-NEXT:    andl $-8, %esp
860; AVX512DQVL_32-NEXT:    subl $8, %esp
861; AVX512DQVL_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
862; AVX512DQVL_32-NEXT:    vcvtqq2pd %ymm0, %ymm0
863; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
864; AVX512DQVL_32-NEXT:    fldl (%esp)
865; AVX512DQVL_32-NEXT:    movl %ebp, %esp
866; AVX512DQVL_32-NEXT:    popl %ebp
867; AVX512DQVL_32-NEXT:    vzeroupper
868; AVX512DQVL_32-NEXT:    retl
869;
870; AVX512_64-LABEL: s64_to_d:
871; AVX512_64:       # %bb.0:
872; AVX512_64-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
873; AVX512_64-NEXT:    retq
874;
875; AVX512DQ_32-LABEL: s64_to_d:
876; AVX512DQ_32:       # %bb.0:
877; AVX512DQ_32-NEXT:    pushl %ebp
878; AVX512DQ_32-NEXT:    movl %esp, %ebp
879; AVX512DQ_32-NEXT:    andl $-8, %esp
880; AVX512DQ_32-NEXT:    subl $8, %esp
881; AVX512DQ_32-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
882; AVX512DQ_32-NEXT:    vcvtqq2pd %zmm0, %zmm0
883; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
884; AVX512DQ_32-NEXT:    fldl (%esp)
885; AVX512DQ_32-NEXT:    movl %ebp, %esp
886; AVX512DQ_32-NEXT:    popl %ebp
887; AVX512DQ_32-NEXT:    vzeroupper
888; AVX512DQ_32-NEXT:    retl
889;
890; AVX512F_32-LABEL: s64_to_d:
891; AVX512F_32:       # %bb.0:
892; AVX512F_32-NEXT:    pushl %ebp
893; AVX512F_32-NEXT:    movl %esp, %ebp
894; AVX512F_32-NEXT:    andl $-8, %esp
895; AVX512F_32-NEXT:    subl $8, %esp
896; AVX512F_32-NEXT:    fildll 8(%ebp)
897; AVX512F_32-NEXT:    fstpl (%esp)
898; AVX512F_32-NEXT:    fldl (%esp)
899; AVX512F_32-NEXT:    movl %ebp, %esp
900; AVX512F_32-NEXT:    popl %ebp
901; AVX512F_32-NEXT:    retl
902;
903; SSE2_32-LABEL: s64_to_d:
904; SSE2_32:       # %bb.0:
905; SSE2_32-NEXT:    pushl %ebp
906; SSE2_32-NEXT:    movl %esp, %ebp
907; SSE2_32-NEXT:    andl $-8, %esp
908; SSE2_32-NEXT:    subl $8, %esp
909; SSE2_32-NEXT:    fildll 8(%ebp)
910; SSE2_32-NEXT:    fstpl (%esp)
911; SSE2_32-NEXT:    fldl (%esp)
912; SSE2_32-NEXT:    movl %ebp, %esp
913; SSE2_32-NEXT:    popl %ebp
914; SSE2_32-NEXT:    retl
915;
916; SSE2_64-LABEL: s64_to_d:
917; SSE2_64:       # %bb.0:
918; SSE2_64-NEXT:    cvtsi2sd %rdi, %xmm0
919; SSE2_64-NEXT:    retq
920;
921; SSE1_32-LABEL: s64_to_d:
922; SSE1_32:       # %bb.0:
923; SSE1_32-NEXT:    fildll {{[0-9]+}}(%esp)
924; SSE1_32-NEXT:    retl
925;
926; X87-LABEL: s64_to_d:
927; X87:       # %bb.0:
928; X87-NEXT:    fildll {{[0-9]+}}(%esp)
929; X87-NEXT:    retl
930  %r = sitofp i64 %a to double
931  ret double %r
932}
933
934define double @s64_to_d_2(i64 %a) nounwind {
935; AVX512DQVL_32-LABEL: s64_to_d_2:
936; AVX512DQVL_32:       # %bb.0:
937; AVX512DQVL_32-NEXT:    pushl %ebp
938; AVX512DQVL_32-NEXT:    movl %esp, %ebp
939; AVX512DQVL_32-NEXT:    andl $-8, %esp
940; AVX512DQVL_32-NEXT:    subl $8, %esp
941; AVX512DQVL_32-NEXT:    movl 8(%ebp), %eax
942; AVX512DQVL_32-NEXT:    movl 12(%ebp), %ecx
943; AVX512DQVL_32-NEXT:    addl $5, %eax
944; AVX512DQVL_32-NEXT:    adcl $0, %ecx
945; AVX512DQVL_32-NEXT:    vmovd %eax, %xmm0
946; AVX512DQVL_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
947; AVX512DQVL_32-NEXT:    vcvtqq2pd %ymm0, %ymm0
948; AVX512DQVL_32-NEXT:    vmovlps %xmm0, (%esp)
949; AVX512DQVL_32-NEXT:    fldl (%esp)
950; AVX512DQVL_32-NEXT:    movl %ebp, %esp
951; AVX512DQVL_32-NEXT:    popl %ebp
952; AVX512DQVL_32-NEXT:    vzeroupper
953; AVX512DQVL_32-NEXT:    retl
954;
955; AVX512_64-LABEL: s64_to_d_2:
956; AVX512_64:       # %bb.0:
957; AVX512_64-NEXT:    addq $5, %rdi
958; AVX512_64-NEXT:    vcvtsi2sd %rdi, %xmm0, %xmm0
959; AVX512_64-NEXT:    retq
960;
961; AVX512DQ_32-LABEL: s64_to_d_2:
962; AVX512DQ_32:       # %bb.0:
963; AVX512DQ_32-NEXT:    pushl %ebp
964; AVX512DQ_32-NEXT:    movl %esp, %ebp
965; AVX512DQ_32-NEXT:    andl $-8, %esp
966; AVX512DQ_32-NEXT:    subl $8, %esp
967; AVX512DQ_32-NEXT:    movl 8(%ebp), %eax
968; AVX512DQ_32-NEXT:    movl 12(%ebp), %ecx
969; AVX512DQ_32-NEXT:    addl $5, %eax
970; AVX512DQ_32-NEXT:    adcl $0, %ecx
971; AVX512DQ_32-NEXT:    vmovd %eax, %xmm0
972; AVX512DQ_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
973; AVX512DQ_32-NEXT:    vcvtqq2pd %zmm0, %zmm0
974; AVX512DQ_32-NEXT:    vmovlps %xmm0, (%esp)
975; AVX512DQ_32-NEXT:    fldl (%esp)
976; AVX512DQ_32-NEXT:    movl %ebp, %esp
977; AVX512DQ_32-NEXT:    popl %ebp
978; AVX512DQ_32-NEXT:    vzeroupper
979; AVX512DQ_32-NEXT:    retl
980;
981; AVX512F_32-LABEL: s64_to_d_2:
982; AVX512F_32:       # %bb.0:
983; AVX512F_32-NEXT:    pushl %ebp
984; AVX512F_32-NEXT:    movl %esp, %ebp
985; AVX512F_32-NEXT:    andl $-8, %esp
986; AVX512F_32-NEXT:    subl $16, %esp
987; AVX512F_32-NEXT:    movl 8(%ebp), %eax
988; AVX512F_32-NEXT:    movl 12(%ebp), %ecx
989; AVX512F_32-NEXT:    addl $5, %eax
990; AVX512F_32-NEXT:    adcl $0, %ecx
991; AVX512F_32-NEXT:    vmovd %eax, %xmm0
992; AVX512F_32-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm0
993; AVX512F_32-NEXT:    vmovq %xmm0, {{[0-9]+}}(%esp)
994; AVX512F_32-NEXT:    fildll {{[0-9]+}}(%esp)
995; AVX512F_32-NEXT:    fstpl (%esp)
996; AVX512F_32-NEXT:    fldl (%esp)
997; AVX512F_32-NEXT:    movl %ebp, %esp
998; AVX512F_32-NEXT:    popl %ebp
999; AVX512F_32-NEXT:    retl
1000;
1001; SSE2_32-LABEL: s64_to_d_2:
1002; SSE2_32:       # %bb.0:
1003; SSE2_32-NEXT:    pushl %ebp
1004; SSE2_32-NEXT:    movl %esp, %ebp
1005; SSE2_32-NEXT:    andl $-8, %esp
1006; SSE2_32-NEXT:    subl $16, %esp
1007; SSE2_32-NEXT:    movl 8(%ebp), %eax
1008; SSE2_32-NEXT:    movl 12(%ebp), %ecx
1009; SSE2_32-NEXT:    addl $5, %eax
1010; SSE2_32-NEXT:    adcl $0, %ecx
1011; SSE2_32-NEXT:    movd %ecx, %xmm0
1012; SSE2_32-NEXT:    movd %eax, %xmm1
1013; SSE2_32-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
1014; SSE2_32-NEXT:    movq %xmm1, {{[0-9]+}}(%esp)
1015; SSE2_32-NEXT:    fildll {{[0-9]+}}(%esp)
1016; SSE2_32-NEXT:    fstpl (%esp)
1017; SSE2_32-NEXT:    fldl (%esp)
1018; SSE2_32-NEXT:    movl %ebp, %esp
1019; SSE2_32-NEXT:    popl %ebp
1020; SSE2_32-NEXT:    retl
1021;
1022; SSE2_64-LABEL: s64_to_d_2:
1023; SSE2_64:       # %bb.0:
1024; SSE2_64-NEXT:    addq $5, %rdi
1025; SSE2_64-NEXT:    cvtsi2sd %rdi, %xmm0
1026; SSE2_64-NEXT:    retq
1027;
1028; SSE1_32-LABEL: s64_to_d_2:
1029; SSE1_32:       # %bb.0:
1030; SSE1_32-NEXT:    pushl %ebp
1031; SSE1_32-NEXT:    movl %esp, %ebp
1032; SSE1_32-NEXT:    andl $-8, %esp
1033; SSE1_32-NEXT:    subl $8, %esp
1034; SSE1_32-NEXT:    movl 8(%ebp), %eax
1035; SSE1_32-NEXT:    movl 12(%ebp), %ecx
1036; SSE1_32-NEXT:    addl $5, %eax
1037; SSE1_32-NEXT:    adcl $0, %ecx
1038; SSE1_32-NEXT:    movl %eax, (%esp)
1039; SSE1_32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
1040; SSE1_32-NEXT:    fildll (%esp)
1041; SSE1_32-NEXT:    movl %ebp, %esp
1042; SSE1_32-NEXT:    popl %ebp
1043; SSE1_32-NEXT:    retl
1044;
1045; X87-LABEL: s64_to_d_2:
1046; X87:       # %bb.0:
1047; X87-NEXT:    pushl %ebp
1048; X87-NEXT:    movl %esp, %ebp
1049; X87-NEXT:    andl $-8, %esp
1050; X87-NEXT:    subl $8, %esp
1051; X87-NEXT:    movl 8(%ebp), %eax
1052; X87-NEXT:    movl 12(%ebp), %ecx
1053; X87-NEXT:    addl $5, %eax
1054; X87-NEXT:    adcl $0, %ecx
1055; X87-NEXT:    movl %eax, (%esp)
1056; X87-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
1057; X87-NEXT:    fildll (%esp)
1058; X87-NEXT:    movl %ebp, %esp
1059; X87-NEXT:    popl %ebp
1060; X87-NEXT:    retl
1061  %b = add i64 %a, 5
1062  %f = sitofp i64 %b to double
1063  ret double %f
1064}
1065
1066define x86_fp80 @u64_to_x(i64 %a) nounwind {
1067; CHECK32-LABEL: u64_to_x:
1068; CHECK32:       # %bb.0:
1069; CHECK32-NEXT:    pushl %ebp
1070; CHECK32-NEXT:    movl %esp, %ebp
1071; CHECK32-NEXT:    andl $-8, %esp
1072; CHECK32-NEXT:    subl $8, %esp
1073; CHECK32-NEXT:    movl 8(%ebp), %eax
1074; CHECK32-NEXT:    movl 12(%ebp), %ecx
1075; CHECK32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
1076; CHECK32-NEXT:    movl %eax, (%esp)
1077; CHECK32-NEXT:    shrl $31, %ecx
1078; CHECK32-NEXT:    fildll (%esp)
1079; CHECK32-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%ecx,4)
1080; CHECK32-NEXT:    movl %ebp, %esp
1081; CHECK32-NEXT:    popl %ebp
1082; CHECK32-NEXT:    retl
1083;
1084; CHECK64-LABEL: u64_to_x:
1085; CHECK64:       # %bb.0:
1086; CHECK64-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
1087; CHECK64-NEXT:    xorl %eax, %eax
1088; CHECK64-NEXT:    testq %rdi, %rdi
1089; CHECK64-NEXT:    sets %al
1090; CHECK64-NEXT:    fildll -{{[0-9]+}}(%rsp)
1091; CHECK64-NEXT:    fadds {{\.?LCPI[0-9]+_[0-9]+}}(,%rax,4)
1092; CHECK64-NEXT:    retq
1093  %r = uitofp i64 %a to x86_fp80
1094  ret x86_fp80 %r
1095}
1096
1097define x86_fp80 @s64_to_x(i64 %a) nounwind {
1098; CHECK32-LABEL: s64_to_x:
1099; CHECK32:       # %bb.0:
1100; CHECK32-NEXT:    fildll {{[0-9]+}}(%esp)
1101; CHECK32-NEXT:    retl
1102;
1103; CHECK64-LABEL: s64_to_x:
1104; CHECK64:       # %bb.0:
1105; CHECK64-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
1106; CHECK64-NEXT:    fildll -{{[0-9]+}}(%rsp)
1107; CHECK64-NEXT:    retq
1108  %r = sitofp i64 %a to x86_fp80
1109  ret x86_fp80 %r
1110}
1111