xref: /llvm-project/llvm/test/CodeGen/X86/scalar-extract.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-- -mattr=+mmx | FileCheck %s
3
4; Check that widening doesn't introduce a mmx register in this case when
5; a simple load/store would suffice.
6
7define void @foo(ptr %A, ptr %B) {
8; CHECK-LABEL: foo:
9; CHECK:       # %bb.0: # %entry
10; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
11; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
12; CHECK-NEXT:    movl (%ecx), %ecx
13; CHECK-NEXT:    movl %ecx, (%eax)
14; CHECK-NEXT:    retl
15entry:
16	%tmp1 = load <2 x i16>, ptr %A		; <<2 x i16>> [#uses=1]
17	store <2 x i16> %tmp1, ptr %B
18	ret void
19}
20
21