1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,SSE 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX1 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2 5 6define i32 @shl48sar47(i64 %a) #0 { 7; CHECK-LABEL: shl48sar47: 8; CHECK: # %bb.0: 9; CHECK-NEXT: movswl %di, %eax 10; CHECK-NEXT: addl %eax, %eax 11; CHECK-NEXT: retq 12 %1 = shl i64 %a, 48 13 %2 = ashr exact i64 %1, 47 14 %3 = trunc i64 %2 to i32 15 ret i32 %3 16} 17 18define i32 @shl48sar49(i64 %a) #0 { 19; CHECK-LABEL: shl48sar49: 20; CHECK: # %bb.0: 21; CHECK-NEXT: movswq %di, %rax 22; CHECK-NEXT: shrq %rax 23; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 24; CHECK-NEXT: retq 25 %1 = shl i64 %a, 48 26 %2 = ashr exact i64 %1, 49 27 %3 = trunc i64 %2 to i32 28 ret i32 %3 29} 30 31define i32 @shl56sar55(i64 %a) #0 { 32; CHECK-LABEL: shl56sar55: 33; CHECK: # %bb.0: 34; CHECK-NEXT: movsbl %dil, %eax 35; CHECK-NEXT: addl %eax, %eax 36; CHECK-NEXT: retq 37 %1 = shl i64 %a, 56 38 %2 = ashr exact i64 %1, 55 39 %3 = trunc i64 %2 to i32 40 ret i32 %3 41} 42 43define i32 @shl56sar57(i64 %a) #0 { 44; CHECK-LABEL: shl56sar57: 45; CHECK: # %bb.0: 46; CHECK-NEXT: movsbq %dil, %rax 47; CHECK-NEXT: shrq %rax 48; CHECK-NEXT: # kill: def $eax killed $eax killed $rax 49; CHECK-NEXT: retq 50 %1 = shl i64 %a, 56 51 %2 = ashr exact i64 %1, 57 52 %3 = trunc i64 %2 to i32 53 ret i32 %3 54} 55 56define i8 @all_sign_bit_ashr(i8 %x) { 57; CHECK-LABEL: all_sign_bit_ashr: 58; CHECK: # %bb.0: 59; CHECK-NEXT: movl %edi, %eax 60; CHECK-NEXT: andb $1, %al 61; CHECK-NEXT: negb %al 62; CHECK-NEXT: # kill: def $al killed $al killed $eax 63; CHECK-NEXT: retq 64 %and = and i8 %x, 1 65 %neg = sub i8 0, %and 66 %sar = ashr i8 %neg, 6 67 ret i8 %sar 68} 69 70define <4 x i32> @all_sign_bit_ashr_vec0(<4 x i32> %x) { 71; SSE-LABEL: all_sign_bit_ashr_vec0: 72; SSE: # %bb.0: 73; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 74; SSE-NEXT: pxor %xmm1, %xmm1 75; SSE-NEXT: psubd %xmm0, %xmm1 76; SSE-NEXT: movdqa %xmm1, %xmm0 77; SSE-NEXT: retq 78; 79; AVX1-LABEL: all_sign_bit_ashr_vec0: 80; AVX1: # %bb.0: 81; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 82; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 83; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0 84; AVX1-NEXT: retq 85; 86; AVX2-LABEL: all_sign_bit_ashr_vec0: 87; AVX2: # %bb.0: 88; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 89; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 90; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 91; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0 92; AVX2-NEXT: retq 93 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 94 %neg = sub <4 x i32> zeroinitializer, %and 95 %sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0> 96 ret <4 x i32> %sar 97} 98 99define <4 x i32> @all_sign_bit_ashr_vec1(<4 x i32> %x) { 100; SSE-LABEL: all_sign_bit_ashr_vec1: 101; SSE: # %bb.0: 102; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,0,0] 103; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 104; SSE-NEXT: pxor %xmm0, %xmm0 105; SSE-NEXT: psubd %xmm1, %xmm0 106; SSE-NEXT: retq 107; 108; AVX1-LABEL: all_sign_bit_ashr_vec1: 109; AVX1: # %bb.0: 110; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] 111; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 112; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 113; AVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0 114; AVX1-NEXT: retq 115; 116; AVX2-LABEL: all_sign_bit_ashr_vec1: 117; AVX2: # %bb.0: 118; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0 119; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 120; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 121; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 122; AVX2-NEXT: vpsubd %xmm0, %xmm1, %xmm0 123; AVX2-NEXT: retq 124 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 125 %sub = sub <4 x i32> <i32 0, i32 1, i32 2, i32 3>, %and 126 %shf = shufflevector <4 x i32> %sub, <4 x i32> undef, <4 x i32> zeroinitializer 127 %sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0> 128 ret <4 x i32> %sar 129} 130 131define <4 x i32> @all_sign_bit_ashr_vec2(<4 x i32> %x) { 132; SSE-LABEL: all_sign_bit_ashr_vec2: 133; SSE: # %bb.0: 134; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 135; SSE-NEXT: pcmpeqd %xmm1, %xmm1 136; SSE-NEXT: paddd %xmm1, %xmm0 137; SSE-NEXT: retq 138; 139; AVX1-LABEL: all_sign_bit_ashr_vec2: 140; AVX1: # %bb.0: 141; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 142; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 143; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 144; AVX1-NEXT: retq 145; 146; AVX2-LABEL: all_sign_bit_ashr_vec2: 147; AVX2: # %bb.0: 148; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 149; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 150; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 151; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 152; AVX2-NEXT: retq 153 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 154 %add = add <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1> 155 %sar = ashr <4 x i32> %add, <i32 1, i32 31, i32 5, i32 0> 156 ret <4 x i32> %sar 157} 158 159define <4 x i32> @all_sign_bit_ashr_vec3(<4 x i32> %x) { 160; SSE-LABEL: all_sign_bit_ashr_vec3: 161; SSE: # %bb.0: 162; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,0,0] 163; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 164; SSE-NEXT: pcmpeqd %xmm0, %xmm0 165; SSE-NEXT: paddd %xmm1, %xmm0 166; SSE-NEXT: retq 167; 168; AVX1-LABEL: all_sign_bit_ashr_vec3: 169; AVX1: # %bb.0: 170; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] 171; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 172; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 173; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 174; AVX1-NEXT: retq 175; 176; AVX2-LABEL: all_sign_bit_ashr_vec3: 177; AVX2: # %bb.0: 178; AVX2-NEXT: vpbroadcastd %xmm0, %xmm0 179; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [1,1,1,1] 180; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 181; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 182; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 183; AVX2-NEXT: retq 184 %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> 185 %add = add <4 x i32> %and, <i32 -1, i32 1, i32 2, i32 3> 186 %shf = shufflevector <4 x i32> %add, <4 x i32> undef, <4 x i32> zeroinitializer 187 %sar = ashr <4 x i32> %shf, <i32 1, i32 31, i32 5, i32 0> 188 ret <4 x i32> %sar 189} 190 191attributes #0 = { nounwind } 192