xref: /llvm-project/llvm/test/CodeGen/X86/sar_fold.ll (revision 3e6e54eb795ce7a1ccd47df8c22fc08125a88886)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
3
4define i32 @shl16sar15(i32 %a) #0 {
5; CHECK-LABEL: shl16sar15:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    movswl {{[0-9]+}}(%esp), %eax
8; CHECK-NEXT:    addl %eax, %eax
9; CHECK-NEXT:    retl
10  %1 = shl i32 %a, 16
11  %2 = ashr exact i32 %1, 15
12  ret i32 %2
13}
14
15define i32 @shl16sar17(i32 %a) #0 {
16; CHECK-LABEL: shl16sar17:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    movswl {{[0-9]+}}(%esp), %eax
19; CHECK-NEXT:    sarl %eax
20; CHECK-NEXT:    retl
21  %1 = shl i32 %a, 16
22  %2 = ashr exact i32 %1, 17
23  ret i32 %2
24}
25
26define i32 @shl24sar23(i32 %a) #0 {
27; CHECK-LABEL: shl24sar23:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
30; CHECK-NEXT:    addl %eax, %eax
31; CHECK-NEXT:    retl
32  %1 = shl i32 %a, 24
33  %2 = ashr exact i32 %1, 23
34  ret i32 %2
35}
36
37define i32 @shl24sar25(i32 %a) #0 {
38; CHECK-LABEL: shl24sar25:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
41; CHECK-NEXT:    sarl %eax
42; CHECK-NEXT:    retl
43  %1 = shl i32 %a, 24
44  %2 = ashr exact i32 %1, 25
45  ret i32 %2
46}
47
48define void @shl144sar48(ptr %p) #0 {
49; CHECK-LABEL: shl144sar48:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
52; CHECK-NEXT:    movswl (%eax), %ecx
53; CHECK-NEXT:    movl %ecx, %edx
54; CHECK-NEXT:    sarl $31, %edx
55; CHECK-NEXT:    shldl $2, %ecx, %edx
56; CHECK-NEXT:    shll $2, %ecx
57; CHECK-NEXT:    movl %ecx, 12(%eax)
58; CHECK-NEXT:    movl %edx, 16(%eax)
59; CHECK-NEXT:    movl $0, 8(%eax)
60; CHECK-NEXT:    movl $0, 4(%eax)
61; CHECK-NEXT:    movl $0, (%eax)
62; CHECK-NEXT:    retl
63  %a = load i160, ptr %p
64  %1 = shl i160 %a, 144
65  %2 = ashr exact i160 %1, 46
66  store i160 %2, ptr %p
67  ret void
68}
69
70define void @shl144sar2(ptr %p) #0 {
71; CHECK-LABEL: shl144sar2:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
74; CHECK-NEXT:    movswl (%eax), %ecx
75; CHECK-NEXT:    shll $14, %ecx
76; CHECK-NEXT:    movl %ecx, 16(%eax)
77; CHECK-NEXT:    movl $0, 8(%eax)
78; CHECK-NEXT:    movl $0, 12(%eax)
79; CHECK-NEXT:    movl $0, 4(%eax)
80; CHECK-NEXT:    movl $0, (%eax)
81; CHECK-NEXT:    retl
82  %a = load i160, ptr %p
83  %1 = shl i160 %a, 144
84  %2 = ashr exact i160 %1, 2
85  store i160 %2, ptr %p
86  ret void
87}
88