xref: /llvm-project/llvm/test/CodeGen/X86/rotate5.ll (revision b651fdff79027064071db7c1d0250553e3e6a232)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
4
5; Ensure that the (pre-extended) shift amount type is wide enough to take any mask.
6define void @PR56859() {
7; X86-LABEL: PR56859:
8; X86:       # %bb.0: # %entry
9; X86-NEXT:    movl (%eax), %ecx
10; X86-NEXT:    testl %ecx, %ecx
11; X86-NEXT:    setne %al
12; X86-NEXT:    movl $1, %edx
13; X86-NEXT:    # kill: def $cl killed $cl killed $ecx
14; X86-NEXT:    shrl %cl, %edx
15; X86-NEXT:    btsl %eax, %edx
16; X86-NEXT:    movl %edx, (%eax)
17; X86-NEXT:    retl
18;
19; X64-LABEL: PR56859:
20; X64:       # %bb.0: # %entry
21; X64-NEXT:    movl (%rax), %ecx
22; X64-NEXT:    testl %ecx, %ecx
23; X64-NEXT:    setne %al
24; X64-NEXT:    movl $1, %edx
25; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
26; X64-NEXT:    shrl %cl, %edx
27; X64-NEXT:    btsl %eax, %edx
28; X64-NEXT:    movl %edx, (%rax)
29; X64-NEXT:    retq
30entry:
31  %0 = load i32, ptr undef, align 4
32  %tobool = icmp ne i32 %0, 0
33  %lor.ext = zext i1 %tobool to i32
34  %shr = lshr i32 1, %0
35  %shl = shl i32 1, %lor.ext
36  %or = or i32 %shl, %shr
37  store i32 %or, ptr undef, align 4
38  ret void
39}
40