xref: /llvm-project/llvm/test/CodeGen/X86/rotate-multi.ll (revision 86eff6be686a1e41e13c08ebfc2db4dd4d58e7c6) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
3
4; OR of two rotates of %a0(edi).
5define i32 @f0(i32 %a0) #0 {
6; CHECK-LABEL: f0:
7; CHECK:       # %bb.0: # %b0
8; CHECK-NEXT:    movl %edi, %eax
9; CHECK-NEXT:    roll $7, %eax
10; CHECK-NEXT:    roll $9, %edi
11; CHECK-NEXT:    orl %edi, %eax
12; CHECK-NEXT:    retq
13b0:
14  %v0 = shl i32 %a0, 7
15  %v1 = lshr i32 %a0, 25
16  %v2 = or i32 %v0, %v1
17  %v3 = shl i32 %a0, 9
18  %v4 = lshr i32 %a0, 23
19  %v5 = or i32 %v3, %v4
20  %v6 = or i32 %v2, %v5
21  ret i32 %v6
22}
23
24; OR of two rotates of %a0(edi) with an extra input %a1(esi).
25define i32 @f1(i32 %a0, i32 %a1) #0 {
26; CHECK-LABEL: f1:
27; CHECK:       # %bb.0: # %b0
28; CHECK-NEXT:    movl %edi, %eax
29; CHECK-NEXT:    shll $7, %eax
30; CHECK-NEXT:    orl %esi, %eax
31; CHECK-NEXT:    roll $9, %edi
32; CHECK-NEXT:    orl %edi, %eax
33; CHECK-NEXT:    retq
34b0:
35  %v0 = shl i32 %a0, 7
36  %v1 = lshr i32 %a0, 25
37  %v2 = or i32 %v0, %a1
38  %v3 = shl i32 %a0, 9
39  %v4 = lshr i32 %a0, 23
40  %v5 = or i32 %v3, %v4
41  %v6 = or i32 %v2, %v5
42  %v7 = or i32 %v6, %v1
43  ret i32 %v6
44}
45
46; OR of two rotates of two different inputs: %a0(edi) and %a1(esi).
47define i32 @f2(i32 %a0, i32 %a1) #0 {
48; CHECK-LABEL: f2:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    movl %edi, %ecx
51; CHECK-NEXT:    shll $11, %ecx
52; CHECK-NEXT:    shrl $21, %edi
53; CHECK-NEXT:    movl %esi, %eax
54; CHECK-NEXT:    shll $19, %eax
55; CHECK-NEXT:    orl %ecx, %eax
56; CHECK-NEXT:    shrl $13, %esi
57; CHECK-NEXT:    orl %edi, %esi
58; CHECK-NEXT:    orl %esi, %eax
59; CHECK-NEXT:    retq
60  %v0 = shl i32 %a0, 11
61  %v1 = lshr i32 %a0, 21
62  %v2 = shl i32 %a1, 19
63  %v3 = lshr i32 %a1, 13
64  %v4 = or i32 %v0, %v2
65  %v5 = or i32 %v1, %v3
66  %v6 = or i32 %v4, %v5
67  ret i32 %v6
68}
69
70; ORs of multiple shifts of the same value with only one pair actually
71; matching a rotate.
72define i32 @f3(i32 %a0) #0 {
73; CHECK-LABEL: f3:
74; CHECK:       # %bb.0: # %b0
75; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
76; CHECK-NEXT:    leal (,%rdi,8), %eax
77; CHECK-NEXT:    movl %edi, %ecx
78; CHECK-NEXT:    shll $5, %ecx
79; CHECK-NEXT:    orl %eax, %ecx
80; CHECK-NEXT:    movl %edi, %eax
81; CHECK-NEXT:    shll $7, %eax
82; CHECK-NEXT:    movl %edi, %edx
83; CHECK-NEXT:    shll $13, %edx
84; CHECK-NEXT:    orl %eax, %edx
85; CHECK-NEXT:    orl %ecx, %edx
86; CHECK-NEXT:    movl %edi, %eax
87; CHECK-NEXT:    shll $19, %eax
88; CHECK-NEXT:    movl %edi, %ecx
89; CHECK-NEXT:    shrl $2, %ecx
90; CHECK-NEXT:    orl %eax, %ecx
91; CHECK-NEXT:    movl %edi, %esi
92; CHECK-NEXT:    shrl $15, %esi
93; CHECK-NEXT:    orl %ecx, %esi
94; CHECK-NEXT:    orl %edx, %esi
95; CHECK-NEXT:    movl %edi, %ecx
96; CHECK-NEXT:    shrl $23, %ecx
97; CHECK-NEXT:    movl %edi, %eax
98; CHECK-NEXT:    shrl $25, %eax
99; CHECK-NEXT:    orl %ecx, %eax
100; CHECK-NEXT:    shrl $30, %edi
101; CHECK-NEXT:    orl %edi, %eax
102; CHECK-NEXT:    orl %esi, %eax
103; CHECK-NEXT:    retq
104b0:
105  %v0 = shl i32 %a0, 3
106  %v1 = shl i32 %a0, 5
107  %v2 = shl i32 %a0, 7      ; rotate
108  %v3 = shl i32 %a0, 13
109  %v4 = shl i32 %a0, 19
110  %v5 = lshr i32 %a0, 2
111  %v6 = lshr i32 %a0, 15
112  %v7 = lshr i32 %a0, 23
113  %v8 = lshr i32 %a0, 25    ; rotate
114  %v9 = lshr i32 %a0, 30
115  %v10 = or i32  %v0, %v1
116  %v11 = or i32 %v10, %v2
117  %v12 = or i32 %v11, %v3
118  %v13 = or i32 %v12, %v4
119  %v14 = or i32 %v13, %v5
120  %v15 = or i32 %v14, %v6
121  %v16 = or i32 %v15, %v7
122  %v17 = or i32 %v16, %v8
123  %v18 = or i32 %v17, %v9
124  ret i32 %v18
125}
126
127attributes #0 = { readnone nounwind }
128