1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+cmov | FileCheck %s 3 4define i32 @test1(i32 %X) { 5; CHECK-LABEL: test1: 6; CHECK: # %bb.0: 7; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 8; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081 9; CHECK-NEXT: movl %ecx, %eax 10; CHECK-NEXT: imull %edx 11; CHECK-NEXT: leal (%edx,%ecx), %eax 12; CHECK-NEXT: movl %eax, %edx 13; CHECK-NEXT: shrl $31, %edx 14; CHECK-NEXT: sarl $7, %eax 15; CHECK-NEXT: addl %edx, %eax 16; CHECK-NEXT: movl %eax, %edx 17; CHECK-NEXT: shll $8, %edx 18; CHECK-NEXT: subl %edx, %eax 19; CHECK-NEXT: addl %ecx, %eax 20; CHECK-NEXT: retl 21 %tmp1 = srem i32 %X, 255 22 ret i32 %tmp1 23} 24 25define i32 @test2(i32 %X) { 26; CHECK-LABEL: test2: 27; CHECK: # %bb.0: 28; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 29; CHECK-NEXT: leal 255(%eax), %ecx 30; CHECK-NEXT: testl %eax, %eax 31; CHECK-NEXT: cmovnsl %eax, %ecx 32; CHECK-NEXT: andl $-256, %ecx 33; CHECK-NEXT: subl %ecx, %eax 34; CHECK-NEXT: retl 35 %tmp1 = srem i32 %X, 256 36 ret i32 %tmp1 37} 38 39define i32 @test3(i32 %X) { 40; CHECK-LABEL: test3: 41; CHECK: # %bb.0: 42; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx 43; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081 44; CHECK-NEXT: movl %ecx, %eax 45; CHECK-NEXT: mull %edx 46; CHECK-NEXT: shrl $7, %edx 47; CHECK-NEXT: movl %edx, %eax 48; CHECK-NEXT: shll $8, %eax 49; CHECK-NEXT: subl %eax, %edx 50; CHECK-NEXT: addl %edx, %ecx 51; CHECK-NEXT: movl %ecx, %eax 52; CHECK-NEXT: retl 53 %tmp1 = urem i32 %X, 255 54 ret i32 %tmp1 55} 56 57define i32 @test4(i32 %X) { 58; CHECK-LABEL: test4: 59; CHECK: # %bb.0: 60; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax 61; CHECK-NEXT: retl 62 %tmp1 = urem i32 %X, 256 63 ret i32 %tmp1 64} 65 66define i32 @test5(i32 %X) nounwind readnone { 67; CHECK-LABEL: test5: 68; CHECK: # %bb.0: # %entry 69; CHECK-NEXT: movl $41, %eax 70; CHECK-NEXT: xorl %edx, %edx 71; CHECK-NEXT: idivl {{[0-9]+}}(%esp) 72; CHECK-NEXT: movl %edx, %eax 73; CHECK-NEXT: retl 74entry: 75 %0 = srem i32 41, %X 76 ret i32 %0 77} 78 79