1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s 3 4define void @PR57402() { 5; CHECK-LABEL: PR57402: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: notl %eax 8; CHECK-NEXT: andl $-2, %eax 9; CHECK-NEXT: leal 1(%rax,%rax,2), %ecx 10; CHECK-NEXT: movswq %cx, %rsi 11; CHECK-NEXT: xorl %edi, %edi 12; CHECK-NEXT: movq $-1, %rax 13; CHECK-NEXT: xorl %edx, %edx 14; CHECK-NEXT: divq %rsi 15; CHECK-NEXT: testb %dil, %dil 16; CHECK-NEXT: jne .LBB0_4 17; CHECK-NEXT: # %bb.1: # %entry 18; CHECK-NEXT: xorl %eax, %eax 19; CHECK-NEXT: testb %al, %al 20; CHECK-NEXT: jne .LBB0_4 21; CHECK-NEXT: # %bb.2: # %entry 22; CHECK-NEXT: andl %ecx, %edx 23; CHECK-NEXT: movswl %dx, %eax 24; CHECK-NEXT: imull %eax, %eax 25; CHECK-NEXT: testq %rax, %rax 26; CHECK-NEXT: jne .LBB0_3 27; CHECK-NEXT: .LBB0_4: # %if.end 28; CHECK-NEXT: retq 29; CHECK-NEXT: .LBB0_3: # %if.then 30entry: 31 %.fr = freeze i64 undef 32 %0 = trunc i64 %.fr to i16 33 %1 = and i16 %0, -2 34 %2 = xor i16 %1, -2 35 %3 = mul i16 %2, 3 36 %conv = or i16 %3, 1 37 %conv2 = sext i16 %conv to i64 38 %rem = urem i64 -1, %conv2 39 %conv3 = trunc i64 %rem to i32 40 %sext = shl i32 %conv3, 16 41 %conv4 = ashr exact i32 %sext, 16 42 %conv5 = sext i16 %conv to i32 43 %and = and i32 %conv4, %conv5 44 %and.fr = freeze i32 %and 45 %conv6 = sext i32 %and.fr to i64 46 %mul7 = mul i64 %.fr, %conv6 47 %4 = and i64 %mul7, 4294967295 48 %tobool1216 = icmp ne i64 %4, 0 49 %tobool12 = and i1 undef, %tobool1216 50 %or.cond = and i1 undef, %tobool12 51 br i1 %or.cond, label %if.then, label %if.end 52 53if.then: ; preds = %entry 54 unreachable 55 56if.end: ; preds = %entry 57 ret void 58} 59