1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s 3 4define <4 x i3> @test1(ptr %in) nounwind { 5; CHECK-LABEL: test1: 6; CHECK: # %bb.0: 7; CHECK-NEXT: movzwl (%rdi), %eax 8; CHECK-NEXT: movl %eax, %ecx 9; CHECK-NEXT: shrl $3, %ecx 10; CHECK-NEXT: andl $7, %ecx 11; CHECK-NEXT: movl %eax, %edx 12; CHECK-NEXT: andl $7, %edx 13; CHECK-NEXT: vmovd %edx, %xmm0 14; CHECK-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0 15; CHECK-NEXT: movl %eax, %ecx 16; CHECK-NEXT: shrl $6, %ecx 17; CHECK-NEXT: andl $7, %ecx 18; CHECK-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0 19; CHECK-NEXT: shrl $9, %eax 20; CHECK-NEXT: andl $7, %eax 21; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0 22; CHECK-NEXT: retq 23 %ret = load <4 x i3>, ptr %in, align 1 24 ret <4 x i3> %ret 25} 26 27define <4 x i1> @test2(ptr %in) nounwind { 28; CHECK-LABEL: test2: 29; CHECK: # %bb.0: 30; CHECK-NEXT: movzbl (%rdi), %eax 31; CHECK-NEXT: movl %eax, %ecx 32; CHECK-NEXT: shrb %cl 33; CHECK-NEXT: andb $1, %cl 34; CHECK-NEXT: movl %eax, %edx 35; CHECK-NEXT: andb $1, %dl 36; CHECK-NEXT: vmovd %edx, %xmm0 37; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0 38; CHECK-NEXT: movl %eax, %ecx 39; CHECK-NEXT: shrb $2, %cl 40; CHECK-NEXT: andb $1, %cl 41; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0 42; CHECK-NEXT: shrb $3, %al 43; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0 44; CHECK-NEXT: retq 45 %ret = load <4 x i1>, ptr %in, align 1 46 ret <4 x i1> %ret 47} 48 49define <4 x i64> @test3(ptr %in) nounwind { 50; CHECK-LABEL: test3: 51; CHECK: # %bb.0: 52; CHECK-NEXT: movzbl (%rdi), %eax 53; CHECK-NEXT: movzbl %al, %ecx 54; CHECK-NEXT: shrb %al 55; CHECK-NEXT: movzbl %al, %eax 56; CHECK-NEXT: andl $1, %eax 57; CHECK-NEXT: negl %eax 58; CHECK-NEXT: movl %ecx, %edx 59; CHECK-NEXT: andl $1, %edx 60; CHECK-NEXT: negl %edx 61; CHECK-NEXT: vmovd %edx, %xmm0 62; CHECK-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0 63; CHECK-NEXT: movl %ecx, %eax 64; CHECK-NEXT: shrb $2, %al 65; CHECK-NEXT: movzbl %al, %eax 66; CHECK-NEXT: andl $1, %eax 67; CHECK-NEXT: negl %eax 68; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0 69; CHECK-NEXT: shrb $3, %cl 70; CHECK-NEXT: movzbl %cl, %eax 71; CHECK-NEXT: negl %eax 72; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0 73; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1 74; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] 75; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 76; CHECK-NEXT: retq 77 %wide.load35 = load <4 x i1>, ptr %in, align 1 78 %sext = sext <4 x i1> %wide.load35 to <4 x i64> 79 ret <4 x i64> %sext 80} 81 82define <16 x i4> @test4(ptr %in) nounwind { 83; CHECK-LABEL: test4: 84; CHECK: # %bb.0: 85; CHECK-NEXT: movq (%rdi), %rax 86; CHECK-NEXT: movl %eax, %ecx 87; CHECK-NEXT: shrl $4, %ecx 88; CHECK-NEXT: andl $15, %ecx 89; CHECK-NEXT: movl %eax, %edx 90; CHECK-NEXT: andl $15, %edx 91; CHECK-NEXT: vmovd %edx, %xmm0 92; CHECK-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0 93; CHECK-NEXT: movl %eax, %ecx 94; CHECK-NEXT: shrl $8, %ecx 95; CHECK-NEXT: andl $15, %ecx 96; CHECK-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm0 97; CHECK-NEXT: movl %eax, %ecx 98; CHECK-NEXT: shrl $12, %ecx 99; CHECK-NEXT: andl $15, %ecx 100; CHECK-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0 101; CHECK-NEXT: movl %eax, %ecx 102; CHECK-NEXT: shrl $16, %ecx 103; CHECK-NEXT: andl $15, %ecx 104; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0 105; CHECK-NEXT: movl %eax, %ecx 106; CHECK-NEXT: shrl $20, %ecx 107; CHECK-NEXT: andl $15, %ecx 108; CHECK-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0 109; CHECK-NEXT: movl %eax, %ecx 110; CHECK-NEXT: shrl $24, %ecx 111; CHECK-NEXT: andl $15, %ecx 112; CHECK-NEXT: vpinsrb $6, %ecx, %xmm0, %xmm0 113; CHECK-NEXT: movl %eax, %ecx 114; CHECK-NEXT: shrl $28, %ecx 115; CHECK-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0 116; CHECK-NEXT: movq %rax, %rcx 117; CHECK-NEXT: shrq $32, %rcx 118; CHECK-NEXT: andl $15, %ecx 119; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0 120; CHECK-NEXT: movq %rax, %rcx 121; CHECK-NEXT: shrq $36, %rcx 122; CHECK-NEXT: andl $15, %ecx 123; CHECK-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0 124; CHECK-NEXT: movq %rax, %rcx 125; CHECK-NEXT: shrq $40, %rcx 126; CHECK-NEXT: andl $15, %ecx 127; CHECK-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0 128; CHECK-NEXT: movq %rax, %rcx 129; CHECK-NEXT: shrq $44, %rcx 130; CHECK-NEXT: andl $15, %ecx 131; CHECK-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0 132; CHECK-NEXT: movq %rax, %rcx 133; CHECK-NEXT: shrq $48, %rcx 134; CHECK-NEXT: andl $15, %ecx 135; CHECK-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0 136; CHECK-NEXT: movq %rax, %rcx 137; CHECK-NEXT: shrq $52, %rcx 138; CHECK-NEXT: andl $15, %ecx 139; CHECK-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0 140; CHECK-NEXT: movq %rax, %rcx 141; CHECK-NEXT: shrq $56, %rcx 142; CHECK-NEXT: andl $15, %ecx 143; CHECK-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 144; CHECK-NEXT: shrq $60, %rax 145; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 146; CHECK-NEXT: retq 147 %ret = load <16 x i4>, ptr %in, align 1 148 ret <16 x i4> %ret 149} 150