1; When EXPENSIVE_CHECKS are enabled, the machine verifier appears between each 2; pass. Ignore it with 'grep -v'. 3; RUN: llc -mtriple=x86_64-- -O1 -debug-pass=Structure < %s -o /dev/null 2>&1 \ 4; RUN: | grep -v 'Verify generated machine code' | FileCheck %s 5; RUN: llc -mtriple=x86_64-- -O2 -debug-pass=Structure < %s -o /dev/null 2>&1 \ 6; RUN: | grep -v 'Verify generated machine code' | FileCheck %s 7; RUN: llc -mtriple=x86_64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 \ 8; RUN: | grep -v 'Verify generated machine code' | FileCheck %s 9; RUN: llc -mtriple=x86_64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 \ 10; RUN: | FileCheck %s --check-prefix=FPM 11 12; REQUIRES: asserts 13 14; CHECK-LABEL: Pass Arguments: 15; CHECK-NEXT: Target Library Information 16; CHECK-NEXT: Target Pass Configuration 17; CHECK-NEXT: Machine Module Information 18; CHECK-NEXT: Target Transform Information 19; CHECK-NEXT: Type-Based Alias Analysis 20; CHECK-NEXT: Scoped NoAlias Alias Analysis 21; CHECK-NEXT: Assumption Cache Tracker 22; CHECK-NEXT: Profile summary info 23; CHECK-NEXT: Create Garbage Collector Module Metadata 24; CHECK-NEXT: Machine Branch Probability Analysis 25; CHECK-NEXT: Default Regalloc Eviction Advisor 26; CHECK-NEXT: Default Regalloc Priority Advisor 27; CHECK-NEXT: ModulePass Manager 28; CHECK-NEXT: Pre-ISel Intrinsic Lowering 29; CHECK-NEXT: FunctionPass Manager 30; CHECK-NEXT: Expand large div/rem 31; CHECK-NEXT: Expand large fp convert 32; CHECK-NEXT: Expand Atomic instructions 33; CHECK-NEXT: Lower AMX intrinsics 34; CHECK-NEXT: Lower AMX type for load/store 35; CHECK-NEXT: Module Verifier 36; CHECK-NEXT: Dominator Tree Construction 37; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 38; CHECK-NEXT: Natural Loop Information 39; CHECK-NEXT: Canonicalize natural loops 40; CHECK-NEXT: Scalar Evolution Analysis 41; CHECK-NEXT: Loop Pass Manager 42; CHECK-NEXT: Canonicalize Freeze Instructions in Loops 43; CHECK-NEXT: Induction Variable Users 44; CHECK-NEXT: Loop Strength Reduction 45; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 46; CHECK-NEXT: Function Alias Analysis Results 47; CHECK-NEXT: Merge contiguous icmps into a memcmp 48; CHECK-NEXT: Natural Loop Information 49; CHECK-NEXT: Lazy Branch Probability Analysis 50; CHECK-NEXT: Lazy Block Frequency Analysis 51; CHECK-NEXT: Expand memcmp() to load/stores 52; CHECK-NEXT: Lower Garbage Collection Instructions 53; CHECK-NEXT: Shadow Stack GC Lowering 54; CHECK-NEXT: Remove unreachable blocks from the CFG 55; CHECK-NEXT: Natural Loop Information 56; CHECK-NEXT: Post-Dominator Tree Construction 57; CHECK-NEXT: Branch Probability Analysis 58; CHECK-NEXT: Block Frequency Analysis 59; CHECK-NEXT: Constant Hoisting 60; CHECK-NEXT: Replace intrinsics with calls to vector library 61; CHECK-NEXT: Lazy Branch Probability Analysis 62; CHECK-NEXT: Lazy Block Frequency Analysis 63; CHECK-NEXT: Optimization Remark Emitter 64; CHECK-NEXT: Partially inline calls to library functions 65; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining) 66; CHECK-NEXT: Scalarize Masked Memory Intrinsics 67; CHECK-NEXT: Expand reduction intrinsics 68; CHECK-NEXT: Interleaved Access Pass 69; CHECK-NEXT: X86 Partial Reduction 70; CHECK-NEXT: Expand indirectbr instructions 71; CHECK-NEXT: Natural Loop Information 72; CHECK-NEXT: CodeGen Prepare 73; CHECK-NEXT: Dominator Tree Construction 74; CHECK-NEXT: Exception handling preparation 75; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 76; CHECK-NEXT: Function Alias Analysis Results 77; CHECK-NEXT: ObjC ARC contraction 78; CHECK-NEXT: Prepare callbr 79; CHECK-NEXT: Safe Stack instrumentation pass 80; CHECK-NEXT: Insert stack protectors 81; CHECK-NEXT: Module Verifier 82; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) 83; CHECK-NEXT: Function Alias Analysis Results 84; CHECK-NEXT: Natural Loop Information 85; CHECK-NEXT: Post-Dominator Tree Construction 86; CHECK-NEXT: Branch Probability Analysis 87; CHECK-NEXT: Assignment Tracking Analysis 88; CHECK-NEXT: Lazy Branch Probability Analysis 89; CHECK-NEXT: Lazy Block Frequency Analysis 90; CHECK-NEXT: X86 DAG->DAG Instruction Selection 91; CHECK-NEXT: MachineDominator Tree Construction 92; CHECK-NEXT: Local Dynamic TLS Access Clean-up 93; CHECK-NEXT: X86 PIC Global Base Reg Initialization 94; CHECK-NEXT: Argument Stack Rebase 95; CHECK-NEXT: Finalize ISel and expand pseudo-instructions 96; CHECK-NEXT: X86 Domain Reassignment Pass 97; CHECK-NEXT: Lazy Machine Block Frequency Analysis 98; CHECK-NEXT: Early Tail Duplication 99; CHECK-NEXT: Optimize machine instruction PHIs 100; CHECK-NEXT: Slot index numbering 101; CHECK-NEXT: Merge disjoint stack slots 102; CHECK-NEXT: Local Stack Slot Allocation 103; CHECK-NEXT: Remove dead machine instructions 104; CHECK-NEXT: MachineDominator Tree Construction 105; CHECK-NEXT: Machine Natural Loop Construction 106; CHECK-NEXT: Machine Trace Metrics 107; CHECK-NEXT: Early If-Conversion 108; CHECK-NEXT: Lazy Machine Block Frequency Analysis 109; CHECK-NEXT: Machine InstCombiner 110; CHECK-NEXT: X86 cmov Conversion 111; CHECK-NEXT: MachineDominator Tree Construction 112; CHECK-NEXT: Machine Natural Loop Construction 113; CHECK-NEXT: Machine Block Frequency Analysis 114; CHECK-NEXT: Early Machine Loop Invariant Code Motion 115; CHECK-NEXT: MachineDominator Tree Construction 116; CHECK-NEXT: Machine Block Frequency Analysis 117; CHECK-NEXT: Machine Common Subexpression Elimination 118; CHECK-NEXT: MachinePostDominator Tree Construction 119; CHECK-NEXT: Machine Cycle Info Analysis 120; CHECK-NEXT: Machine code sinking 121; CHECK-NEXT: Peephole Optimizations 122; CHECK-NEXT: Remove dead machine instructions 123; CHECK-NEXT: Live Range Shrink 124; CHECK-NEXT: X86 Windows Fixup Buffer Security Check 125; CHECK-NEXT: X86 Fixup SetCC 126; CHECK-NEXT: Lazy Machine Block Frequency Analysis 127; CHECK-NEXT: X86 LEA Optimize 128; CHECK-NEXT: X86 Optimize Call Frame 129; CHECK-NEXT: X86 Avoid Store Forwarding Block 130; CHECK-NEXT: X86 speculative load hardening 131; CHECK-NEXT: X86 EFLAGS copy lowering 132; CHECK-NEXT: X86 DynAlloca Expander 133; CHECK-NEXT: MachineDominator Tree Construction 134; CHECK-NEXT: Machine Natural Loop Construction 135; CHECK-NEXT: Tile Register Pre-configure 136; CHECK-NEXT: Detect Dead Lanes 137; CHECK-NEXT: Init Undef Pass 138; CHECK-NEXT: Process Implicit Definitions 139; CHECK-NEXT: Remove unreachable machine basic blocks 140; CHECK-NEXT: Live Variable Analysis 141; CHECK-NEXT: Eliminate PHI nodes for register allocation 142; CHECK-NEXT: Two-Address instruction pass 143; CHECK-NEXT: Slot index numbering 144; CHECK-NEXT: Live Interval Analysis 145; CHECK-NEXT: Register Coalescer 146; CHECK-NEXT: Rename Disconnected Subregister Components 147; CHECK-NEXT: Machine Instruction Scheduler 148; CHECK-NEXT: Machine Block Frequency Analysis 149; CHECK-NEXT: Debug Variable Analysis 150; CHECK-NEXT: Live Stack Slot Analysis 151; CHECK-NEXT: Virtual Register Map 152; CHECK-NEXT: Live Register Matrix 153; CHECK-NEXT: Bundle Machine CFG Edges 154; CHECK-NEXT: Spill Code Placement Analysis 155; CHECK-NEXT: Lazy Machine Block Frequency Analysis 156; CHECK-NEXT: Machine Optimization Remark Emitter 157; CHECK-NEXT: Greedy Register Allocator 158; CHECK-NEXT: Tile Register Configure 159; CHECK-NEXT: Greedy Register Allocator 160; CHECK-NEXT: Virtual Register Rewriter 161; CHECK-NEXT: Register Allocation Pass Scoring 162; CHECK-NEXT: Stack Slot Coloring 163; CHECK-NEXT: Machine Copy Propagation Pass 164; CHECK-NEXT: Machine Loop Invariant Code Motion 165; CHECK-NEXT: X86 Lower Tile Copy 166; CHECK-NEXT: Bundle Machine CFG Edges 167; CHECK-NEXT: X86 FP Stackifier 168; CHECK-NEXT: MachineDominator Tree Construction 169; CHECK-NEXT: Machine Dominance Frontier Construction 170; CHECK-NEXT: X86 Load Value Injection (LVI) Load Hardening 171; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis 172; CHECK-NEXT: Fixup Statepoint Caller Saved 173; CHECK-NEXT: PostRA Machine Sink 174; CHECK-NEXT: Machine Block Frequency Analysis 175; CHECK-NEXT: MachinePostDominator Tree Construction 176; CHECK-NEXT: Lazy Machine Block Frequency Analysis 177; CHECK-NEXT: Machine Optimization Remark Emitter 178; CHECK-NEXT: Shrink Wrapping analysis 179; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization 180; CHECK-NEXT: Machine Late Instructions Cleanup Pass 181; CHECK-NEXT: Control Flow Optimizer 182; CHECK-NEXT: Lazy Machine Block Frequency Analysis 183; CHECK-NEXT: Tail Duplication 184; CHECK-NEXT: Machine Copy Propagation Pass 185; CHECK-NEXT: Post-RA pseudo instruction expansion pass 186; CHECK-NEXT: X86 pseudo instruction expansion pass 187; CHECK-NEXT: Insert KCFI indirect call checks 188; CHECK-NEXT: MachineDominator Tree Construction 189; CHECK-NEXT: Machine Natural Loop Construction 190; CHECK-NEXT: Post RA top-down list latency scheduler 191; CHECK-NEXT: Analyze Machine Code For Garbage Collection 192; CHECK-NEXT: Machine Block Frequency Analysis 193; CHECK-NEXT: MachinePostDominator Tree Construction 194; CHECK-NEXT: Branch Probability Basic Block Placement 195; CHECK-NEXT: Insert fentry calls 196; CHECK-NEXT: Insert XRay ops 197; CHECK-NEXT: Implement the 'patchable-function' attribute 198; CHECK-NEXT: ReachingDefAnalysis 199; CHECK-NEXT: X86 Execution Dependency Fix 200; CHECK-NEXT: BreakFalseDeps 201; CHECK-NEXT: X86 Indirect Branch Tracking 202; CHECK-NEXT: X86 vzeroupper inserter 203; CHECK-NEXT: Lazy Machine Block Frequency Analysis 204; CHECK-NEXT: X86 Byte/Word Instruction Fixup 205; CHECK-NEXT: Lazy Machine Block Frequency Analysis 206; CHECK-NEXT: X86 Atom pad short functions 207; CHECK-NEXT: X86 LEA Fixup 208; CHECK-NEXT: X86 Fixup Inst Tuning 209; CHECK-NEXT: X86 Fixup Vector Constants 210; CHECK-NEXT: Compressing EVEX instrs when possible 211; CHECK-NEXT: X86 Discriminate Memory Operands 212; CHECK-NEXT: X86 Insert Cache Prefetches 213; CHECK-NEXT: X86 insert wait instruction 214; CHECK-NEXT: Contiguously Lay Out Funclets 215; CHECK-NEXT: Remove Loads Into Fake Uses 216; CHECK-NEXT: StackMap Liveness Analysis 217; CHECK-NEXT: Live DEBUG_VALUE analysis 218; CHECK-NEXT: Machine Sanitizer Binary Metadata 219; CHECK-NEXT: Lazy Machine Block Frequency Analysis 220; CHECK-NEXT: Machine Optimization Remark Emitter 221; CHECK-NEXT: Stack Frame Layout Analysis 222; CHECK-NEXT: X86 Speculative Execution Side Effect Suppression 223; CHECK-NEXT: X86 Indirect Thunks 224; CHECK-NEXT: X86 Return Thunks 225; CHECK-NEXT: Check CFA info and insert CFI instructions if needed 226; CHECK-NEXT: X86 Load Value Injection (LVI) Ret-Hardening 227; CHECK-NEXT: Pseudo Probe Inserter 228; CHECK-NEXT: Unpack machine instruction bundles 229; CHECK-NEXT: Lazy Machine Block Frequency Analysis 230; CHECK-NEXT: Machine Optimization Remark Emitter 231; CHECK-NEXT: X86 Assembly Printer 232; CHECK-NEXT: Free MachineFunction 233 234; We should only have one function pass manager. 235; In the past, module passes have accidentally been added into the middle of 236; the codegen pipeline, implicitly creating new function pass managers. 237; FPM: FunctionPass Manager 238; FPM-NOT: FunctionPass Manager 239 240define void @f() { 241 ret void 242} 243