xref: /llvm-project/llvm/test/CodeGen/X86/mulfix_combine.ll (revision 5e331e4ce85ad37dca45739846c2a801f06ab573) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-linux -o - | FileCheck %s
3
4declare i32 @llvm.smul.fix.i32(i32, i32, i32 immarg)
5declare i32 @llvm.umul.fix.i32(i32, i32, i32 immarg)
6declare i32 @llvm.smul.fix.sat.i32(i32, i32, i32 immarg)
7declare i32 @llvm.umul.fix.sat.i32(i32, i32, i32 immarg)
8
9declare <4 x i32> @llvm.smul.fix.v4i32(<4 x i32>, <4 x i32>, i32 immarg)
10declare <4 x i32> @llvm.umul.fix.v4i32(<4 x i32>, <4 x i32>, i32 immarg)
11declare <4 x i32> @llvm.smul.fix.sat.v4i32(<4 x i32>, <4 x i32>, i32 immarg)
12declare <4 x i32> @llvm.umul.fix.sat.v4i32(<4 x i32>, <4 x i32>, i32 immarg)
13
14define i32 @smulfix_undef(i32 %y) nounwind {
15; CHECK-LABEL: smulfix_undef:
16; CHECK:       # %bb.0:
17; CHECK-NEXT:    xorl %eax, %eax
18; CHECK-NEXT:    retq
19  %tmp = call i32 @llvm.smul.fix.i32(i32 undef, i32 %y, i32 2)
20  ret i32 %tmp
21}
22
23define i32 @smulfix_zero(i32 %y) nounwind {
24; CHECK-LABEL: smulfix_zero:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    xorl %eax, %eax
27; CHECK-NEXT:    retq
28  %tmp = call i32 @llvm.smul.fix.i32(i32 0, i32 %y, i32 2)
29  ret i32 %tmp
30}
31
32define i32 @umulfix_undef(i32 %y) nounwind {
33; CHECK-LABEL: umulfix_undef:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    xorl %eax, %eax
36; CHECK-NEXT:    retq
37  %tmp = call i32 @llvm.umul.fix.i32(i32 undef, i32 %y, i32 2)
38  ret i32 %tmp
39}
40
41define i32 @umulfix_zero(i32 %y) nounwind {
42; CHECK-LABEL: umulfix_zero:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    xorl %eax, %eax
45; CHECK-NEXT:    retq
46  %tmp = call i32 @llvm.umul.fix.i32(i32 0, i32 %y, i32 2)
47  ret i32 %tmp
48}
49
50define i32 @smulfixsat_undef(i32 %y) nounwind {
51; CHECK-LABEL: smulfixsat_undef:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    xorl %eax, %eax
54; CHECK-NEXT:    retq
55  %tmp = call i32 @llvm.smul.fix.sat.i32(i32 undef, i32 %y, i32 2)
56  ret i32 %tmp
57}
58
59define i32 @smulfixsat_zero(i32 %y) nounwind {
60; CHECK-LABEL: smulfixsat_zero:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    xorl %eax, %eax
63; CHECK-NEXT:    retq
64  %tmp = call i32 @llvm.smul.fix.sat.i32(i32 0, i32 %y, i32 2)
65  ret i32 %tmp
66}
67
68define i32 @umulfixsat_undef(i32 %y) nounwind {
69; CHECK-LABEL: umulfixsat_undef:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    xorl %eax, %eax
72; CHECK-NEXT:    retq
73  %tmp = call i32 @llvm.umul.fix.sat.i32(i32 undef, i32 %y, i32 2)
74  ret i32 %tmp
75}
76
77define i32 @umulfixsat_zero(i32 %y) nounwind {
78; CHECK-LABEL: umulfixsat_zero:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    xorl %eax, %eax
81; CHECK-NEXT:    retq
82  %tmp = call i32 @llvm.umul.fix.sat.i32(i32 0, i32 %y, i32 2)
83  ret i32 %tmp
84}
85
86define <4 x i32> @vec_smulfix_undef(<4 x i32> %y) nounwind {
87; CHECK-LABEL: vec_smulfix_undef:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    xorps %xmm0, %xmm0
90; CHECK-NEXT:    retq
91  %tmp = call <4 x i32> @llvm.smul.fix.v4i32(<4 x i32> undef, <4 x i32> %y, i32 2)
92  ret <4 x i32> %tmp
93}
94
95define <4 x i32> @vec_smulfix_zero(<4 x i32> %y) nounwind {
96; CHECK-LABEL: vec_smulfix_zero:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    xorps %xmm0, %xmm0
99; CHECK-NEXT:    retq
100  %tmp = call <4 x i32> @llvm.smul.fix.v4i32(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> %y, i32 2)
101  ret <4 x i32> %tmp
102}
103
104define <4 x i32> @vec_umulfix_undef(<4 x i32> %y) nounwind {
105; CHECK-LABEL: vec_umulfix_undef:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    xorps %xmm0, %xmm0
108; CHECK-NEXT:    retq
109  %tmp = call <4 x i32> @llvm.umul.fix.v4i32(<4 x i32> undef, <4 x i32> %y, i32 2)
110  ret <4 x i32> %tmp
111}
112
113define <4 x i32> @vec_umulfix_zero(<4 x i32> %y) nounwind {
114; CHECK-LABEL: vec_umulfix_zero:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    xorps %xmm0, %xmm0
117; CHECK-NEXT:    retq
118  %tmp = call <4 x i32> @llvm.umul.fix.v4i32(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> %y, i32 2)
119  ret <4 x i32> %tmp
120}
121
122define <4 x i32> @vec_smulfixsat_undef(<4 x i32> %y) nounwind {
123; CHECK-LABEL: vec_smulfixsat_undef:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    xorps %xmm0, %xmm0
126; CHECK-NEXT:    retq
127  %tmp = call <4 x i32> @llvm.smul.fix.sat.v4i32(<4 x i32> undef, <4 x i32> %y, i32 2)
128  ret <4 x i32> %tmp
129}
130
131define <4 x i32> @vec_smulfixsat_zero(<4 x i32> %y) nounwind {
132; CHECK-LABEL: vec_smulfixsat_zero:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    xorps %xmm0, %xmm0
135; CHECK-NEXT:    retq
136  %tmp = call <4 x i32> @llvm.smul.fix.sat.v4i32(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> %y, i32 2)
137  ret <4 x i32> %tmp
138}
139
140define <4 x i32> @vec_umulfixsat_undef(<4 x i32> %y) nounwind {
141; CHECK-LABEL: vec_umulfixsat_undef:
142; CHECK:       # %bb.0:
143; CHECK-NEXT:    xorps %xmm0, %xmm0
144; CHECK-NEXT:    retq
145  %tmp = call <4 x i32> @llvm.umul.fix.sat.v4i32(<4 x i32> undef, <4 x i32> %y, i32 2)
146  ret <4 x i32> %tmp
147}
148
149define <4 x i32> @vec_umulfixsat_zero(<4 x i32> %y) nounwind {
150; CHECK-LABEL: vec_umulfixsat_zero:
151; CHECK:       # %bb.0:
152; CHECK-NEXT:    xorps %xmm0, %xmm0
153; CHECK-NEXT:    retq
154  %tmp = call <4 x i32> @llvm.umul.fix.sat.v4i32(<4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> %y, i32 2)
155  ret <4 x i32> %tmp
156}
157