xref: /llvm-project/llvm/test/CodeGen/X86/mul-shift-reassoc.ll (revision 7863cc6c1c9e714de666f7df84fe9ef6ea7bb06c)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-- | FileCheck %s
3; RUN: llc < %s -mtriple=i686-- -early-live-intervals -verify-machineinstrs | FileCheck %s
4
5define i32 @test(i32 %X, i32 %Y) {
6	; Push the shl through the mul to allow an LEA to be formed, instead
7        ; of using a shift and add separately.
8; CHECK-LABEL: test:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
11; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
12; CHECK-NEXT:    imull %eax, %ecx
13; CHECK-NEXT:    leal (%eax,%ecx,2), %eax
14; CHECK-NEXT:    retl
15        %tmp.2 = shl i32 %X, 1          ; <i32> [#uses=1]
16        %tmp.3 = mul i32 %tmp.2, %Y             ; <i32> [#uses=1]
17        %tmp.5 = add i32 %tmp.3, %Y             ; <i32> [#uses=1]
18        ret i32 %tmp.5
19}
20
21