xref: /llvm-project/llvm/test/CodeGen/X86/mmx-bitcast.ll (revision b7e4fba6e5dcae5ff51f8eced21470a1b3ccd895) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s
3
4define i64 @t0(ptr %p) {
5; CHECK-LABEL: t0:
6; CHECK:       ## %bb.0:
7; CHECK-NEXT:    movq (%rdi), %mm0
8; CHECK-NEXT:    paddq %mm0, %mm0
9; CHECK-NEXT:    movq %mm0, %rax
10; CHECK-NEXT:    retq
11  %t = load <1 x i64>, ptr %p
12  %u = tail call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> %t, <1 x i64> %t)
13  %s = bitcast <1 x i64> %u to i64
14  ret i64 %s
15}
16
17define i64 @t1(ptr %p) {
18; CHECK-LABEL: t1:
19; CHECK:       ## %bb.0:
20; CHECK-NEXT:    movq (%rdi), %mm0
21; CHECK-NEXT:    paddd %mm0, %mm0
22; CHECK-NEXT:    movq %mm0, %rax
23; CHECK-NEXT:    retq
24  %t = load <1 x i64>, ptr %p
25  %u = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %t, <1 x i64> %t)
26  %s = bitcast <1 x i64> %u to i64
27  ret i64 %s
28}
29
30define i64 @t2(ptr %p) {
31; CHECK-LABEL: t2:
32; CHECK:       ## %bb.0:
33; CHECK-NEXT:    movq (%rdi), %mm0
34; CHECK-NEXT:    paddw %mm0, %mm0
35; CHECK-NEXT:    movq %mm0, %rax
36; CHECK-NEXT:    retq
37  %t = load <1 x i64>, ptr %p
38  %u = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> %t, <1 x i64> %t)
39  %s = bitcast <1 x i64> %u to i64
40  ret i64 %s
41}
42
43define i64 @t3(ptr %p) {
44; CHECK-LABEL: t3:
45; CHECK:       ## %bb.0:
46; CHECK-NEXT:    movq (%rdi), %mm0
47; CHECK-NEXT:    paddb %mm0, %mm0
48; CHECK-NEXT:    movq %mm0, %rax
49; CHECK-NEXT:    retq
50  %t = load <1 x i64>, ptr %p
51  %u = tail call <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64> %t, <1 x i64> %t)
52  %s = bitcast <1 x i64> %u to i64
53  ret i64 %s
54}
55
56@R = external global <1 x i64>
57
58define void @t4(<1 x i64> %A, <1 x i64> %B) {
59; CHECK-LABEL: t4:
60; CHECK:       ## %bb.0: ## %entry
61; CHECK-NEXT:    movq %rsi, %mm0
62; CHECK-NEXT:    movq %rdi, %mm1
63; CHECK-NEXT:    paddusw %mm0, %mm1
64; CHECK-NEXT:    movq _R@GOTPCREL(%rip), %rax
65; CHECK-NEXT:    movq %mm1, (%rax)
66; CHECK-NEXT:    emms
67; CHECK-NEXT:    retq
68entry:
69  %tmp7 = tail call <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64> %A, <1 x i64> %B)
70  store <1 x i64> %tmp7, ptr @R
71  tail call void @llvm.x86.mmx.emms()
72  ret void
73}
74
75define i64 @t5(i32 %a, i32 %b) nounwind readnone {
76; CHECK-LABEL: t5:
77; CHECK:       ## %bb.0:
78; CHECK-NEXT:    movd %esi, %xmm0
79; CHECK-NEXT:    movd %edi, %xmm1
80; CHECK-NEXT:    punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
81; CHECK-NEXT:    movq %xmm1, %rax
82; CHECK-NEXT:    retq
83  %v0 = insertelement <2 x i32> undef, i32 %a, i32 0
84  %v1 = insertelement <2 x i32> %v0, i32 %b, i32 1
85  %conv = bitcast <2 x i32> %v1 to i64
86  ret i64 %conv
87}
88
89declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)
90
91define <1 x i64> @t6(i64 %t) {
92; CHECK-LABEL: t6:
93; CHECK:       ## %bb.0:
94; CHECK-NEXT:    movq %rdi, %mm0
95; CHECK-NEXT:    psllq $48, %mm0
96; CHECK-NEXT:    movq %mm0, %rax
97; CHECK-NEXT:    retq
98  %t1 = insertelement <1 x i64> undef, i64 %t, i32 0
99  %t2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %t1, i32 48)
100  ret <1 x i64> %t2
101}
102
103declare <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64>, <1 x i64>)
104declare <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64>, <1 x i64>)
105declare <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64>, <1 x i64>)
106declare <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64>, <1 x i64>)
107declare <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64>, <1 x i64>)
108declare void @llvm.x86.mmx.emms()
109
110