1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 %s -o - | FileCheck %s --check-prefixes SSE2,SSE2-X64 3; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -fast-isel %s -o - | FileCheck %s --check-prefixes SSE2,SSE2-X64 4; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -global-isel-abort=1 %s -o - | FileCheck %s --check-prefixes SSE2,SSE2-GISEL 5 6; 7; 128 bit vectors 8; 9 10define <7 x i8> @test_vector_v7i8() { 11; SSE2-X64-LABEL: test_vector_v7i8: 12; SSE2-X64: # %bb.0: 13; SSE2-X64-NEXT: movq %rdi, %rax 14; SSE2-X64-NEXT: movl {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ecx 15; SSE2-X64-NEXT: movl %ecx, (%rdi) 16; SSE2-X64-NEXT: movb $63, 6(%rdi) 17; SSE2-X64-NEXT: movw $10775, 4(%rdi) # imm = 0x2A17 18; SSE2-X64-NEXT: retq 19; 20; SSE2-GISEL-LABEL: test_vector_v7i8: 21; SSE2-GISEL: # %bb.0: 22; SSE2-GISEL-NEXT: movq %rdi, %rax 23; SSE2-GISEL-NEXT: movb $4, %cl 24; SSE2-GISEL-NEXT: movb $8, %dl 25; SSE2-GISEL-NEXT: movb $15, %sil 26; SSE2-GISEL-NEXT: movb $16, %dil 27; SSE2-GISEL-NEXT: movb $23, %r8b 28; SSE2-GISEL-NEXT: movb $42, %r9b 29; SSE2-GISEL-NEXT: movb $63, %r10b 30; SSE2-GISEL-NEXT: movb %cl, (%rax) 31; SSE2-GISEL-NEXT: movb %dl, 1(%rax) 32; SSE2-GISEL-NEXT: movb %sil, 2(%rax) 33; SSE2-GISEL-NEXT: movb %dil, 3(%rax) 34; SSE2-GISEL-NEXT: movb %r8b, 4(%rax) 35; SSE2-GISEL-NEXT: movb %r9b, 5(%rax) 36; SSE2-GISEL-NEXT: movb %r10b, 6(%rax) 37; SSE2-GISEL-NEXT: retq 38 ret <7 x i8> <i8 4, i8 8, i8 15, i8 16, i8 23, i8 42, i8 63> 39} 40 41define <16 x i8> @test_vector_v16i8() { 42; SSE2-LABEL: test_vector_v16i8: 43; SSE2: # %bb.0: 44; SSE2-NEXT: movaps {{.*#+}} xmm0 = [4,8,15,16,23,42,63,70,92,105,123,133,157,160,174,180] 45; SSE2-NEXT: retq 46 ret <16 x i8> <i8 4, i8 8, i8 15, i8 16, i8 23, i8 42, i8 63, i8 70, i8 92, i8 105, i8 123, i8 133, i8 157, i8 160, i8 174, i8 180> 47} 48 49define <8 x i16> @test_vector_v8i16() { 50; SSE2-LABEL: test_vector_v8i16: 51; SSE2: # %bb.0: 52; SSE2-NEXT: movaps {{.*#+}} xmm0 = [4,15,23,63,92,123,157,174] 53; SSE2-NEXT: retq 54 ret <8 x i16> <i16 4, i16 15, i16 23, i16 63, i16 92, i16 123, i16 157, i16 174> 55} 56 57define <4 x float> @test_vector_v4f32() { 58; SSE2-LABEL: test_vector_v4f32: 59; SSE2: # %bb.0: 60; SSE2-NEXT: movaps {{.*#+}} xmm0 = [u,3.6627E+5,9.86864E+5,7.0851E+4] 61; SSE2-NEXT: retq 62 ret <4 x float> <float undef, float 366270.0, float 986864.0, float 70851.0> 63} 64 65define <2 x i64> @test_vector_v4i64() { 66; SSE2-LABEL: test_vector_v4i64: 67; SSE2: # %bb.0: 68; SSE2-NEXT: movaps {{.*#+}} xmm0 = [9406487659005566976,9903695591611287552] 69; SSE2-NEXT: retq 70 ret <2 x i64> <i64 9406487659005566976, i64 9903695591611287552> 71} 72 73