1; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X86 2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 5 6; PR16133 - we must treat XMM registers as v4f32 as SSE1 targets don't permit other vector types. 7 8define void @nop() nounwind { 9; X86-LABEL: nop: 10; X86: # %bb.0: 11; X86-NEXT: pushl %ebp 12; X86-NEXT: movl %esp, %ebp 13; X86-NEXT: andl $-16, %esp 14; X86-NEXT: subl $32, %esp 15; X86-NEXT: #APP 16; X86-NEXT: #NO_APP 17; X86-NEXT: movaps %xmm0, (%esp) 18; X86-NEXT: movl %ebp, %esp 19; X86-NEXT: popl %ebp 20; X86-NEXT: retl 21; 22; X64-LABEL: nop: 23; X64: # %bb.0: 24; X64-NEXT: #APP 25; X64-NEXT: #NO_APP 26; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) 27; X64-NEXT: retq 28 %1 = alloca <4 x float>, align 16 29 %2 = call <4 x float> asm "", "=x,~{dirflag},~{fpsr},~{flags}"() 30 store <4 x float> %2, ptr %1, align 16 31 ret void 32} 33