1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -verify-machineinstrs -no-integrated-as | FileCheck %s 3 4; There should be no stack manipulations between the inline asm and ret. 5define x86_fp80 @test1() nounwind { 6; CHECK-LABEL: test1: 7; CHECK: ## %bb.0: 8; CHECK-NEXT: ## InlineAsm Start 9; CHECK-NEXT: fld0 10; CHECK-NEXT: ## InlineAsm End 11; CHECK-NEXT: retl 12 %tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"() 13 ret x86_fp80 %tmp85 14} 15 16define double @test2() nounwind { 17; CHECK-LABEL: test2: 18; CHECK: ## %bb.0: 19; CHECK-NEXT: ## InlineAsm Start 20; CHECK-NEXT: fld0 21; CHECK-NEXT: ## InlineAsm End 22; CHECK-NEXT: retl 23 %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() 24 ret double %tmp85 25} 26 27; Setting up argument in st(0) should be a single fld. 28; Asm consumes stack, nothing should be popped. 29define void @test3(x86_fp80 %X) nounwind { 30; CHECK-LABEL: test3: 31; CHECK: ## %bb.0: 32; CHECK-NEXT: subl $12, %esp 33; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 34; CHECK-NEXT: ## InlineAsm Start 35; CHECK-NEXT: frob 36; CHECK-NEXT: ## InlineAsm End 37; CHECK-NEXT: addl $12, %esp 38; CHECK-NEXT: retl 39 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X) 40 ret void 41} 42 43define void @test4(double %X) nounwind { 44; CHECK-LABEL: test4: 45; CHECK: ## %bb.0: 46; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 47; CHECK-NEXT: ## InlineAsm Start 48; CHECK-NEXT: frob 49; CHECK-NEXT: ## InlineAsm End 50; CHECK-NEXT: retl 51 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %X) 52 ret void 53} 54 55; Same as test3/4, but using value from fadd. 56; The fadd can be done in xmm or x87 regs - we don't test that. 57define void @test5(double %X) nounwind { 58; CHECK-LABEL: test5: 59; CHECK: ## %bb.0: 60; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 61; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}} 62; CHECK-NEXT: ## InlineAsm Start 63; CHECK-NEXT: frob 64; CHECK-NEXT: ## InlineAsm End 65; CHECK-NEXT: retl 66 %Y = fadd double %X, 123.0 67 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %Y) 68 ret void 69} 70 71define void @test6(double %A, double %B, double %C, double %D, double %E) nounwind { 72; CHECK-LABEL: test6: 73; CHECK: ## %bb.0: ## %entry 74; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 75; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 76; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 77; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 78; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 79; CHECK-NEXT: ## InlineAsm Start 80; CHECK-NEXT: foo %st %st 81; CHECK-NEXT: ## InlineAsm End 82; CHECK-NEXT: fstp %st(0) 83; CHECK-NEXT: ## InlineAsm Start 84; CHECK-NEXT: bar %st(1) %st 85; CHECK-NEXT: ## InlineAsm End 86; CHECK-NEXT: fstp %st(1) 87; CHECK-NEXT: fstp %st(0) 88; CHECK-NEXT: ## InlineAsm Start 89; CHECK-NEXT: baz %st(1) %st 90; CHECK-NEXT: ## InlineAsm End 91; CHECK-NEXT: fstp %st(0) 92; CHECK-NEXT: ## InlineAsm Start 93; CHECK-NEXT: baz %st 94; CHECK-NEXT: ## InlineAsm End 95; CHECK-NEXT: fstp %st(0) 96; CHECK-NEXT: retl 97entry: 98; Uses the same value twice, should have one fstp after the asm. 99 tail call void asm sideeffect "foo $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %A, double %A ) nounwind 100; Uses two different values, should be in st(0)/st(1) and both be popped. 101 tail call void asm sideeffect "bar $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %B, double %C ) nounwind 102; Uses two different values, one of which isn't killed in this asm, it should not be popped after the asm. 103 tail call void asm sideeffect "baz $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %D, double %E ) nounwind 104; This is the last use of %D, so it should be popped after. 105 tail call void asm sideeffect "baz $0", "f,~{dirflag},~{fpsr},~{flags}"( double %D ) nounwind 106 ret void 107} 108 109; PR4185 110; Passing a non-killed value to asm in {st}. 111; Make sure it is duped before. 112; asm kills st(0), so we shouldn't pop anything 113; A valid alternative would be to remat the constant pool load before each 114; inline asm. 115define void @testPR4185() nounwind { 116; CHECK-LABEL: testPR4185: 117; CHECK: ## %bb.0: ## %return 118; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 119; CHECK-NEXT: fld %st(0) 120; CHECK-NEXT: ## InlineAsm Start 121; CHECK-NEXT: fistpl %st 122; CHECK-NEXT: ## InlineAsm End 123; CHECK-NEXT: ## InlineAsm Start 124; CHECK-NEXT: fistpl %st 125; CHECK-NEXT: ## InlineAsm End 126; CHECK-NEXT: retl 127return: 128 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) 129 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) 130 ret void 131} 132 133; Passing a non-killed value through asm in {st}. 134; Make sure it is not duped before. 135; Second asm kills st(0), so we shouldn't pop anything 136; A valid alternative would be to remat the constant pool load before each inline asm. 137define void @testPR4185b() nounwind { 138; CHECK-LABEL: testPR4185b: 139; CHECK: ## %bb.0: ## %return 140; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 141; CHECK-NEXT: ## InlineAsm Start 142; CHECK-NEXT: fistl %st 143; CHECK-NEXT: ## InlineAsm End 144; CHECK-NEXT: ## InlineAsm Start 145; CHECK-NEXT: fistpl %st 146; CHECK-NEXT: ## InlineAsm End 147; CHECK-NEXT: retl 148return: 149 call void asm sideeffect "fistl $0", "{st}"(double 1.000000e+06) 150 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) 151 ret void 152} 153 154; PR4459 155; The return value from ceil must be duped before being consumed by asm. 156define void @testPR4459(x86_fp80 %a) nounwind { 157; CHECK-LABEL: testPR4459: 158; CHECK: ## %bb.0: ## %entry 159; CHECK-NEXT: subl $28, %esp 160; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 161; CHECK-NEXT: fstpt (%esp) 162; CHECK-NEXT: calll _ceil 163; CHECK-NEXT: fld %st(0) 164; CHECK-NEXT: fxch %st(1) 165; CHECK-NEXT: ## InlineAsm Start 166; CHECK-NEXT: fistpl %st 167; CHECK-NEXT: ## InlineAsm End 168; CHECK-NEXT: fstpt (%esp) 169; CHECK-NEXT: calll _test3 170; CHECK-NEXT: addl $28, %esp 171; CHECK-NEXT: retl 172entry: 173 %0 = call x86_fp80 @ceil(x86_fp80 %a) 174 call void asm sideeffect "fistpl $0", "{st},~{st}"( x86_fp80 %0) 175 call void @test3(x86_fp80 %0 ) 176 ret void 177} 178declare x86_fp80 @ceil(x86_fp80) 179 180; PR4484 181; test1 leaves a value on the stack that is needed after the asm. 182; Load %a from stack after ceil 183; Set up call to test. 184define void @testPR4484(x86_fp80 %a) nounwind { 185; CHECK-LABEL: testPR4484: 186; CHECK: ## %bb.0: ## %entry 187; CHECK-NEXT: subl $28, %esp 188; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 189; CHECK-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill 190; CHECK-NEXT: calll _test1 191; CHECK-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload 192; CHECK-NEXT: ## InlineAsm Start 193; CHECK-NEXT: fistpl %st 194; CHECK-NEXT: ## InlineAsm End 195; CHECK-NEXT: fstpt (%esp) 196; CHECK-NEXT: calll _test3 197; CHECK-NEXT: addl $28, %esp 198; CHECK-NEXT: retl 199entry: 200 %0 = call x86_fp80 @test1() 201 call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a) 202 call void @test3(x86_fp80 %0) 203 ret void 204} 205 206; PR4485 207define void @testPR4485(ptr %a) nounwind { 208; CHECK-LABEL: testPR4485: 209; CHECK: ## %bb.0: ## %entry 210; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 211; CHECK-NEXT: fldt (%eax) 212; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 213; CHECK-NEXT: fmul %st, %st(1) 214; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 215; CHECK-NEXT: fmul %st, %st(2) 216; CHECK-NEXT: fxch %st(2) 217; CHECK-NEXT: ## InlineAsm Start 218; CHECK-NEXT: fistpl %st 219; CHECK-NEXT: ## InlineAsm End 220; CHECK-NEXT: fldt (%eax) 221; CHECK-NEXT: fmulp %st, %st(1) 222; CHECK-NEXT: fmulp %st, %st(1) 223; CHECK-NEXT: ## InlineAsm Start 224; CHECK-NEXT: fistpl %st 225; CHECK-NEXT: ## InlineAsm End 226; CHECK-NEXT: retl 227entry: 228 %0 = load x86_fp80, ptr %a, align 16 229 %1 = fmul x86_fp80 %0, 0xK4006B400000000000000 230 %2 = fmul x86_fp80 %1, 0xK4012F424000000000000 231 tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2) 232 %3 = load x86_fp80, ptr %a, align 16 233 %4 = fmul x86_fp80 %3, 0xK4006B400000000000000 234 %5 = fmul x86_fp80 %4, 0xK4012F424000000000000 235 tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5) 236 ret void 237} 238 239; An input argument in a fixed position is implicitly popped by the asm only if 240; the input argument is tied to an output register, or it is in the clobber list. 241; The clobber list case is tested above. 242; 243; This doesn't implicitly pop the stack: 244; 245; void fist1(long double x, int *p) { 246; asm volatile ("fistl %1" : : "t"(x), "m"(*p)); 247; } 248define void @fist1(x86_fp80 %x, ptr %p) nounwind ssp { 249; CHECK-LABEL: fist1: 250; CHECK: ## %bb.0: ## %entry 251; CHECK-NEXT: subl $12, %esp 252; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 253; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 254; CHECK-NEXT: ## InlineAsm Start 255; CHECK-NEXT: fistl (%eax) 256; CHECK-NEXT: ## InlineAsm End 257; CHECK-NEXT: fstp %st(0) 258; CHECK-NEXT: addl $12, %esp 259; CHECK-NEXT: retl 260entry: 261 tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, ptr elementtype(i32) %p) nounwind 262 ret void 263} 264 265; Here, the input operand is tied to an output which means that is is 266; implicitly popped (and then the output is implicitly pushed). 267; 268; long double fist2(long double x, int *p) { 269; long double y; 270; asm ("fistl %1" : "=&t"(y) : "0"(x), "m"(*p) : "memory"); 271; return y; 272; } 273define x86_fp80 @fist2(x86_fp80 %x, ptr %p) nounwind ssp { 274; CHECK-LABEL: fist2: 275; CHECK: ## %bb.0: ## %entry 276; CHECK-NEXT: subl $12, %esp 277; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 278; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 279; CHECK-NEXT: ## InlineAsm Start 280; CHECK-NEXT: fistl (%eax) 281; CHECK-NEXT: ## InlineAsm End 282; CHECK-NEXT: addl $12, %esp 283; CHECK-NEXT: retl 284entry: 285 %0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, ptr elementtype(i32) %p) nounwind 286 ret x86_fp80 %0 287} 288 289; An 'f' constraint is never implicitly popped: 290; 291; void fucomp1(long double x, long double y) { 292; asm volatile ("fucomp %1" : : "t"(x), "f"(y) : "st"); 293; } 294define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp { 295; CHECK-LABEL: fucomp1: 296; CHECK: ## %bb.0: ## %entry 297; CHECK-NEXT: subl $12, %esp 298; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 299; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 300; CHECK-NEXT: fxch %st(1) 301; CHECK-NEXT: ## InlineAsm Start 302; CHECK-NEXT: fucomp %st(1) 303; CHECK-NEXT: ## InlineAsm End 304; CHECK-NEXT: fstp %st(0) 305; CHECK-NEXT: addl $12, %esp 306; CHECK-NEXT: retl 307entry: 308 tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind 309 ret void 310} 311 312; The 'u' constraint is only popped implicitly when clobbered: 313; 314; void fucomp2(long double x, long double y) { 315; asm volatile ("fucomp %1" : : "t"(x), "u"(y) : "st"); 316; } 317; 318; void fucomp3(long double x, long double y) { 319; asm volatile ("fucompp %1" : : "t"(x), "u"(y) : "st", "st(1)"); 320; } 321; 322define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp { 323; CHECK-LABEL: fucomp2: 324; CHECK: ## %bb.0: ## %entry 325; CHECK-NEXT: subl $12, %esp 326; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 327; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 328; CHECK-NEXT: fxch %st(1) 329; CHECK-NEXT: ## InlineAsm Start 330; CHECK-NEXT: fucomp %st(1) 331; CHECK-NEXT: ## InlineAsm End 332; CHECK-NEXT: fstp %st(0) 333; CHECK-NEXT: addl $12, %esp 334; CHECK-NEXT: retl 335entry: 336 tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind 337 ret void 338} 339 340define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp { 341; CHECK-LABEL: fucomp3: 342; CHECK: ## %bb.0: ## %entry 343; CHECK-NEXT: subl $12, %esp 344; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 345; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 346; CHECK-NEXT: fxch %st(1) 347; CHECK-NEXT: ## InlineAsm Start 348; CHECK-NEXT: fucompp %st(1) 349; CHECK-NEXT: ## InlineAsm End 350; CHECK-NEXT: addl $12, %esp 351; CHECK-NEXT: retl 352entry: 353 tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind 354 ret void 355} 356 357; One input, two outputs, one dead output. 358%complex = type { float, float } 359define float @sincos1(float %x) nounwind ssp { 360; CHECK-LABEL: sincos1: 361; CHECK: ## %bb.0: ## %entry 362; CHECK-NEXT: flds {{[0-9]+}}(%esp) 363; CHECK-NEXT: ## InlineAsm Start 364; CHECK-NEXT: sincos 365; CHECK-NEXT: ## InlineAsm End 366; CHECK-NEXT: fstp %st(1) 367; CHECK-NEXT: retl 368entry: 369 %0 = tail call %complex asm "sincos", "={st},={st(1)},0,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 370 %asmresult = extractvalue %complex %0, 0 371 ret float %asmresult 372} 373 374; Same thing, swapped output operands. 375define float @sincos2(float %x) nounwind ssp { 376; CHECK-LABEL: sincos2: 377; CHECK: ## %bb.0: ## %entry 378; CHECK-NEXT: flds {{[0-9]+}}(%esp) 379; CHECK-NEXT: ## InlineAsm Start 380; CHECK-NEXT: sincos 381; CHECK-NEXT: ## InlineAsm End 382; CHECK-NEXT: fstp %st(1) 383; CHECK-NEXT: retl 384entry: 385 %0 = tail call %complex asm "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 386 %asmresult = extractvalue %complex %0, 1 387 ret float %asmresult 388} 389 390; Clobber st(0) after it was live-out/dead from the previous asm. 391; Load x, make a copy for the second asm. 392; Discard dead result in st(0), bring x to the top. 393; x is now in st(0) for the second asm 394; Discard both results. 395define float @sincos3(float %x) nounwind ssp { 396; CHECK-LABEL: sincos3: 397; CHECK: ## %bb.0: ## %entry 398; CHECK-NEXT: flds {{[0-9]+}}(%esp) 399; CHECK-NEXT: fld %st(0) 400; CHECK-NEXT: ## InlineAsm Start 401; CHECK-NEXT: sincos 402; CHECK-NEXT: ## InlineAsm End 403; CHECK-NEXT: fstp %st(0) 404; CHECK-NEXT: fxch %st(1) 405; CHECK-NEXT: ## InlineAsm Start 406; CHECK-NEXT: sincos 407; CHECK-NEXT: ## InlineAsm End 408; CHECK-NEXT: fstp %st(1) 409; CHECK-NEXT: fstp %st(0) 410; CHECK-NEXT: retl 411entry: 412 %0 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 413 %1 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 414 %asmresult = extractvalue %complex %0, 0 415 ret float %asmresult 416} 417 418; Pass the same value in two fixed stack slots. 419define i32 @PR10602() nounwind ssp { 420; CHECK-LABEL: PR10602: 421; CHECK: ## %bb.0: ## %entry 422; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 423; CHECK-NEXT: fld %st(0) 424; CHECK-NEXT: fxch %st(1) 425; CHECK-NEXT: ## InlineAsm Start 426; CHECK-NEXT: fcomi %st(1), %st; pushf; pop %eax 427; CHECK-NEXT: ## InlineAsm End 428; CHECK-NEXT: fstp %st(0) 429; CHECK-NEXT: fstp %st(0) 430; CHECK-NEXT: retl 431entry: 432 %0 = tail call i32 asm "fcomi $2, $1; pushf; pop $0", "=r,{st},{st(1)},~{dirflag},~{fpsr},~{flags}"(double 2.000000e+00, double 2.000000e+00) nounwind 433 ret i32 %0 434} 435 436; <rdar://problem/16952634> 437; X87 stackifier asserted when there was an ST register defined by an 438; inline-asm instruction and the ST register was live across another 439; inline-asm instruction. 440; 441; INLINEASM $frndint [sideeffect] [attdialect], $0:[regdef], %st0<imp-def,tied5>, $1:[reguse tiedto:$0], %st0<tied3>, $2:[clobber], early-clobber implicit dead %eflags 442; INLINEASM $fldcw $0 [sideeffect] [mayload] [attdialect], $0:[mem], undef %eax, 1, %noreg, 0, %noreg, $1:[clobber], early-clobber implicit dead %eflags 443; %fp0 = COPY %st0 444 445%struct.fpu_t = type { [8 x x86_fp80], x86_fp80, %struct.anon1, %struct.anon2, i32, i8, [15 x i8] } 446%struct.anon1 = type { i32, i32, i32 } 447%struct.anon2 = type { i32, i32, i32, i32 } 448 449@fpu = external global %struct.fpu_t, align 16 450 451; Function Attrs: ssp 452define void @test_live_st(i32 %a1) nounwind { 453; CHECK-LABEL: test_live_st: 454; CHECK: ## %bb.0: ## %entry 455; CHECK-NEXT: subl $12, %esp 456; CHECK-NEXT: fldt (%eax) 457; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp) 458; CHECK-NEXT: jne LBB20_2 459; CHECK-NEXT: ## %bb.1: ## %sw.bb4.i 460; CHECK-NEXT: ## InlineAsm Start 461; CHECK-NEXT: frndint 462; CHECK-NEXT: ## InlineAsm End 463; CHECK-NEXT: ## InlineAsm Start 464; CHECK-NEXT: fldcw (%eax) 465; CHECK-NEXT: ## InlineAsm End 466; CHECK-NEXT: LBB20_2: ## %_Z5tointRKe.exit 467; CHECK-NEXT: fnstcw (%esp) 468; CHECK-NEXT: movzwl (%esp), %eax 469; CHECK-NEXT: orl $3072, %eax ## imm = 0xC00 470; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp) 471; CHECK-NEXT: fldcw {{[0-9]+}}(%esp) 472; CHECK-NEXT: fistpl {{[0-9]+}}(%esp) 473; CHECK-NEXT: fldcw (%esp) 474; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 475; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) 476; CHECK-NEXT: fildl {{[0-9]+}}(%esp) 477; CHECK-NEXT: movl L_fpu$non_lazy_ptr, %eax 478; CHECK-NEXT: fstpt 128(%eax) 479; CHECK-NEXT: addl $12, %esp 480; CHECK-NEXT: retl 481entry: 482 %0 = load x86_fp80, ptr undef, align 16 483 %cond = icmp eq i32 %a1, 1 484 br i1 %cond, label %sw.bb4.i, label %_Z5tointRKe.exit 485 486sw.bb4.i: 487 %1 = call x86_fp80 asm sideeffect "frndint", "={st},0,~{dirflag},~{fpsr},~{flags}"(x86_fp80 %0) 488 call void asm sideeffect "fldcw $0", "*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) undef) 489 br label %_Z5tointRKe.exit 490 491_Z5tointRKe.exit: 492 %result.0.i = phi x86_fp80 [ %1, %sw.bb4.i ], [ %0, %entry ] 493 %conv.i1814 = fptosi x86_fp80 %result.0.i to i32 494 %conv626 = sitofp i32 %conv.i1814 to x86_fp80 495 store x86_fp80 %conv626, ptr getelementptr inbounds (%struct.fpu_t, ptr @fpu, i32 0, i32 1) 496 br label %return 497 498return: 499 ret void 500} 501 502; Check that x87 stackifier is correctly rewriting FP registers to ST registers. 503define double @test_operand_rewrite() nounwind { 504; CHECK-LABEL: test_operand_rewrite: 505; CHECK: ## %bb.0: ## %entry 506; CHECK-NEXT: ## InlineAsm Start 507; CHECK-NEXT: foo %st, %st(1) 508; CHECK-NEXT: ## InlineAsm End 509; CHECK-NEXT: fsubp %st, %st(1) 510; CHECK-NEXT: retl 511entry: 512 %0 = tail call { double, double } asm sideeffect "foo $0, $1", "={st},={st(1)},~{dirflag},~{fpsr},~{flags}"() 513 %asmresult = extractvalue { double, double } %0, 0 514 %asmresult1 = extractvalue { double, double } %0, 1 515 %sub = fsub double %asmresult, %asmresult1 516 ret double %sub 517} 518