1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=i386-pc-linux -stackrealign -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mtriple=i386-pc-none-elf -stackrealign -verify-machineinstrs < %s | FileCheck %s 4 5declare i32 @helper() nounwind 6define void @base() #0 { 7; CHECK-LABEL: base: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: pushl %ebp 10; CHECK-NEXT: .cfi_def_cfa_offset 8 11; CHECK-NEXT: .cfi_offset %ebp, -8 12; CHECK-NEXT: movl %esp, %ebp 13; CHECK-NEXT: .cfi_def_cfa_register %ebp 14; CHECK-NEXT: pushl %esi 15; CHECK-NEXT: andl $-32, %esp 16; CHECK-NEXT: subl $32, %esp 17; CHECK-NEXT: movl %esp, %esi 18; CHECK-NEXT: .cfi_offset %esi, -12 19; CHECK-NEXT: calll helper@PLT 20; CHECK-NEXT: movl %esp, %ecx 21; CHECK-NEXT: leal 31(,%eax,4), %eax 22; CHECK-NEXT: andl $-32, %eax 23; CHECK-NEXT: movl %ecx, %edx 24; CHECK-NEXT: subl %eax, %edx 25; CHECK-NEXT: movl %edx, %esp 26; CHECK-NEXT: negl %eax 27; CHECK-NEXT: movl $0, (%ecx,%eax) 28; CHECK-NEXT: leal -4(%ebp), %esp 29; CHECK-NEXT: popl %esi 30; CHECK-NEXT: popl %ebp 31; CHECK-NEXT: .cfi_def_cfa %esp, 4 32; CHECK-NEXT: retl 33entry: 34 %k = call i32 @helper() 35 %a = alloca i32, i32 %k, align 4 36 store i32 0, ptr %a, align 4 37 ret void 38} 39 40define void @clobber_base() #0 { 41; CHECK-LABEL: clobber_base: 42; CHECK: # %bb.0: # %entry 43; CHECK-NEXT: leal {{[0-9]+}}(%esp), %ecx 44; CHECK-NEXT: .cfi_def_cfa %ecx, 0 45; CHECK-NEXT: andl $-128, %esp 46; CHECK-NEXT: pushl -4(%ecx) 47; CHECK-NEXT: pushl %ebp 48; CHECK-NEXT: movl %esp, %ebp 49; CHECK-NEXT: .cfi_escape 0x10, 0x05, 0x02, 0x75, 0x00 # 50; CHECK-NEXT: pushl %esi 51; CHECK-NEXT: subl $244, %esp 52; CHECK-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill 53; CHECK-NEXT: .cfi_escape 0x10, 0x06, 0x02, 0x75, 0x7c # 54; CHECK-NEXT: .cfi_escape 0x0f, 0x04, 0x75, 0x84, 0x7f, 0x06 # 55; CHECK-NEXT: calll helper@PLT 56; CHECK-NEXT: movl %esp, %ecx 57; CHECK-NEXT: leal 31(,%eax,4), %eax 58; CHECK-NEXT: andl $-32, %eax 59; CHECK-NEXT: movl %ecx, %edx 60; CHECK-NEXT: subl %eax, %edx 61; CHECK-NEXT: movl %edx, %esp 62; CHECK-NEXT: negl %eax 63; CHECK-NEXT: movl $405, %esi # imm = 0x195 64; CHECK-NEXT: #APP 65; CHECK-NEXT: nop 66; CHECK-NEXT: #NO_APP 67; CHECK-NEXT: movl $8, %edx 68; CHECK-NEXT: #APP 69; CHECK-NEXT: movl %edx, -120(%ebp) 70; CHECK-NEXT: #NO_APP 71; CHECK-NEXT: movl $0, (%ecx,%eax) 72; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload 73; CHECK-NEXT: leal -4(%ebp), %esp 74; CHECK-NEXT: popl %esi 75; CHECK-NEXT: popl %ebp 76; CHECK-NEXT: leal -4(%ecx), %esp 77; CHECK-NEXT: .cfi_def_cfa %esp, 4 78; CHECK-NEXT: retl 79entry: 80 %k = call i32 @helper() 81 %a = alloca i32, align 128 82 %b = alloca i32, i32 %k, align 4 83 ; clobber base pointer register 84 tail call void asm sideeffect "nop", "{si}"(i32 405) 85 call void asm sideeffect "movl $0, $1", "r,*m"(i32 8, ptr elementtype(i32) %a) 86 store i32 0, ptr %b, align 4 87 ret void 88} 89 90define x86_regcallcc void @clobber_baseptr_argptr(i32 %param1, i32 %param2, i32 %param3, i32 %param4, i32 %param5, i32 %param6) #0 { 91; CHECK-LABEL: clobber_baseptr_argptr: 92; CHECK: # %bb.0: # %entry 93; CHECK-NEXT: pushl %ebp 94; CHECK-NEXT: .cfi_def_cfa_offset 8 95; CHECK-NEXT: .cfi_offset %ebp, -8 96; CHECK-NEXT: movl %esp, %ebp 97; CHECK-NEXT: .cfi_def_cfa_register %ebp 98; CHECK-NEXT: pushl %ebx 99; CHECK-NEXT: andl $-128, %esp 100; CHECK-NEXT: subl $128, %esp 101; CHECK-NEXT: movl %esp, %esi 102; CHECK-NEXT: .cfi_offset %ebx, -12 103; CHECK-NEXT: movl 8(%ebp), %edi 104; CHECK-NEXT: calll helper@PLT 105; CHECK-NEXT: movl %esp, %ecx 106; CHECK-NEXT: leal 31(,%eax,4), %eax 107; CHECK-NEXT: andl $-32, %eax 108; CHECK-NEXT: movl %ecx, %edx 109; CHECK-NEXT: subl %eax, %edx 110; CHECK-NEXT: movl %edx, %esp 111; CHECK-NEXT: negl %eax 112; CHECK-NEXT: pushl %esi 113; CHECK-NEXT: subl $28, %esp 114; CHECK-NEXT: movl $405, %esi # imm = 0x195 115; CHECK-NEXT: #APP 116; CHECK-NEXT: nop 117; CHECK-NEXT: #NO_APP 118; CHECK-NEXT: addl $28, %esp 119; CHECK-NEXT: popl %esi 120; CHECK-NEXT: movl $405, %ebx # imm = 0x195 121; CHECK-NEXT: #APP 122; CHECK-NEXT: nop 123; CHECK-NEXT: #NO_APP 124; CHECK-NEXT: movl $8, %edx 125; CHECK-NEXT: #APP 126; CHECK-NEXT: movl %edx, (%esi) 127; CHECK-NEXT: #NO_APP 128; CHECK-NEXT: movl %edi, (%ecx,%eax) 129; CHECK-NEXT: leal -4(%ebp), %esp 130; CHECK-NEXT: popl %ebx 131; CHECK-NEXT: popl %ebp 132; CHECK-NEXT: .cfi_def_cfa %esp, 4 133; CHECK-NEXT: retl 134entry: 135 %k = call i32 @helper() 136 %a = alloca i32, align 128 137 %b = alloca i32, i32 %k, align 4 138 ; clobber base pointer register 139 tail call void asm sideeffect "nop", "{si}"(i32 405) 140 ; clobber argument pointer register 141 tail call void asm sideeffect "nop", "{bx}"(i32 405) 142 call void asm sideeffect "movl $0, $1", "r,*m"(i32 8, ptr elementtype(i32) %a) 143 store i32 %param6, ptr %b, align 4 144 ret void 145} 146 147attributes #0 = {"frame-pointer"="all"} 148!llvm.module.flags = !{!0} 149!0 = !{i32 2, !"override-stack-alignment", i32 32} 150