xref: /llvm-project/llvm/test/CodeGen/X86/div-rem-simplify.ll (revision 25528d6de70e98683722e28655d8568d5f09b5c7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3
4; Div/rem by zero is undef.
5
6define i32 @srem0(i32 %x) {
7; CHECK-LABEL: srem0:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    retq
10  %rem = srem i32 %x, 0
11  ret i32 %rem
12}
13
14define i32 @urem0(i32 %x) {
15; CHECK-LABEL: urem0:
16; CHECK:       # %bb.0:
17; CHECK-NEXT:    retq
18  %rem = urem i32 %x, 0
19  ret i32 %rem
20}
21
22define i32 @sdiv0(i32 %x) {
23; CHECK-LABEL: sdiv0:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    retq
26  %div = sdiv i32 %x, 0
27  ret i32 %div
28}
29
30define i32 @udiv0(i32 %x) {
31; CHECK-LABEL: udiv0:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    retq
34  %div = udiv i32 %x, 0
35  ret i32 %div
36}
37
38; Div/rem by zero vectors is undef.
39
40define <4 x i32> @srem_vec0(<4 x i32> %x) {
41; CHECK-LABEL: srem_vec0:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    retq
44  %rem = srem <4 x i32> %x, zeroinitializer
45  ret <4 x i32> %rem
46}
47
48define <4 x i32> @urem_vec0(<4 x i32> %x) {
49; CHECK-LABEL: urem_vec0:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    retq
52  %rem = urem <4 x i32> %x, zeroinitializer
53  ret <4 x i32> %rem
54}
55
56define <4 x i32> @sdiv_vec0(<4 x i32> %x) {
57; CHECK-LABEL: sdiv_vec0:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    retq
60  %div = sdiv <4 x i32> %x, zeroinitializer
61  ret <4 x i32> %div
62}
63
64define <4 x i32> @udiv_vec0(<4 x i32> %x) {
65; CHECK-LABEL: udiv_vec0:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    retq
68  %div = udiv <4 x i32> %x, zeroinitializer
69  ret <4 x i32> %div
70}
71
72; Make sure we handle undef before we try to fold constants from the select with the 0.
73; These used to assert because we can't fold div/rem-by-0 into APInt.
74
75define i32 @sel_urem0(i1 %cond) {
76; CHECK-LABEL: sel_urem0:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    retq
79  %sel = select i1 %cond, i32 23, i32 234
80  %rem = urem i32 %sel, 0
81  ret i32 %rem
82}
83
84define i32 @sel_srem0(i1 %cond) {
85; CHECK-LABEL: sel_srem0:
86; CHECK:       # %bb.0:
87; CHECK-NEXT:    retq
88  %sel = select i1 %cond, i32 23, i32 234
89  %rem = srem i32 %sel, 0
90  ret i32 %rem
91}
92
93define i32 @sel_udiv0(i1 %cond) {
94; CHECK-LABEL: sel_udiv0:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    retq
97  %sel = select i1 %cond, i32 23, i32 234
98  %div = udiv i32 %sel, 0
99  ret i32 %div
100}
101
102define i32 @sel_sdiv0(i1 %cond) {
103; CHECK-LABEL: sel_sdiv0:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    retq
106  %sel = select i1 %cond, i32 23, i32 234
107  %div = sdiv i32 %sel, 0
108  ret i32 %div
109}
110
111; Make sure we handle undef before we try to fold constants from the select with the vector 0.
112; These used to assert because we can't fold div/rem-by-0 into APInt.
113
114define <4 x i32> @sel_urem0_vec(i1 %cond) {
115; CHECK-LABEL: sel_urem0_vec:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    retq
118  %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>
119  %rem = urem <4 x i32> %sel, zeroinitializer
120  ret <4 x i32> %rem
121}
122
123define <4 x i32> @sel_srem0_vec(i1 %cond) {
124; CHECK-LABEL: sel_srem0_vec:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    retq
127  %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>
128  %rem = srem <4 x i32> %sel, zeroinitializer
129  ret <4 x i32> %rem
130}
131
132define <4 x i32> @sel_udiv0_vec(i1 %cond) {
133; CHECK-LABEL: sel_udiv0_vec:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    retq
136  %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>
137  %div = udiv <4 x i32> %sel, zeroinitializer
138  ret <4 x i32> %div
139}
140
141define <4 x i32> @sel_sdiv0_vec(i1 %cond) {
142; CHECK-LABEL: sel_sdiv0_vec:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    retq
145  %sel = select i1 %cond, <4 x i32> <i32 -1, i32 0, i32 1, i32 2>, <4 x i32> <i32 11, i32 12, i32 13, i32 14>
146  %div = sdiv <4 x i32> %sel, zeroinitializer
147  ret <4 x i32> %div
148}
149
150; If any element of a constant divisor vector is zero, the whole op is undef.
151
152define <4 x i32> @sdiv0elt_vec(<4 x i32> %x) {
153; CHECK-LABEL: sdiv0elt_vec:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    retq
156  %zero = and <4 x i32> %x, <i32 0, i32 0, i32 0, i32 0>
157  %some_ones = or <4 x i32> %zero, <i32 0, i32 -1, i32 0, i32 3>
158  %div = sdiv <4 x i32> <i32 -11, i32 -12, i32 -13, i32 -14>, %some_ones
159  ret <4 x i32> %div
160}
161
162define <4 x i32> @udiv0elt_vec(<4 x i32> %x) {
163; CHECK-LABEL: udiv0elt_vec:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    retq
166  %div = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, <i32 0, i32 3, i32 4, i32 0>
167  ret <4 x i32> %div
168}
169
170define <4 x i32> @urem0elt_vec(<4 x i32> %x) {
171; CHECK-LABEL: urem0elt_vec:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    retq
174  %zero = and <4 x i32> %x, <i32 0, i32 0, i32 0, i32 0>
175  %some_ones = or <4 x i32> %zero, <i32 0, i32 0, i32 0, i32 3>
176  %rem = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %some_ones
177  ret <4 x i32> %rem
178}
179
180define <4 x i32> @srem0elt_vec(<4 x i32> %x) {
181; CHECK-LABEL: srem0elt_vec:
182; CHECK:       # %bb.0:
183; CHECK-NEXT:    retq
184  %rem = srem <4 x i32> <i32 -11, i32 -12, i32 -13, i32 -14>, <i32 -3, i32 -3, i32 0, i32 2>
185  ret <4 x i32> %rem
186}
187
188