1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE41 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1OR2 6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX1OR2 7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX,AVX512F 8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX,AVX512BW 9 10define i8 @test_demandedbits_umin_ult(i8 %a0, i8 %a1) { 11; CHECK-LABEL: test_demandedbits_umin_ult: 12; CHECK: # %bb.0: 13; CHECK-NEXT: movl %esi, %eax 14; CHECK-NEXT: orb $4, %al 15; CHECK-NEXT: andb $12, %al 16; CHECK-NEXT: # kill: def $al killed $al killed $eax 17; CHECK-NEXT: retq 18 %lhs0 = and i8 %a0, 13 ; b1101 19 %rhs0 = and i8 %a1, 12 ; b1100 20 %lhs1 = or i8 %lhs0, 12 ; b1100 21 %rhs1 = or i8 %rhs0, 4 ; b0100 22 %umin = tail call i8 @llvm.umin.i8(i8 %lhs1, i8 %rhs1) 23 ret i8 %umin 24} 25declare i8 @llvm.umin.i8(i8, i8) 26 27define <8 x i16> @test_v8i16_nosignbit(<8 x i16> %a, <8 x i16> %b) { 28; SSE2-LABEL: test_v8i16_nosignbit: 29; SSE2: # %bb.0: 30; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 31; SSE2-NEXT: psrlw $1, %xmm1 32; SSE2-NEXT: pmaxsw %xmm1, %xmm0 33; SSE2-NEXT: retq 34; 35; SSE41-LABEL: test_v8i16_nosignbit: 36; SSE41: # %bb.0: 37; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 38; SSE41-NEXT: psrlw $1, %xmm1 39; SSE41-NEXT: pmaxuw %xmm1, %xmm0 40; SSE41-NEXT: retq 41; 42; SSE42-LABEL: test_v8i16_nosignbit: 43; SSE42: # %bb.0: 44; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 45; SSE42-NEXT: psrlw $1, %xmm1 46; SSE42-NEXT: pmaxuw %xmm1, %xmm0 47; SSE42-NEXT: retq 48; 49; AVX-LABEL: test_v8i16_nosignbit: 50; AVX: # %bb.0: 51; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 52; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1 53; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 54; AVX-NEXT: retq 55 %1 = and <8 x i16> %a, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 56 %2 = lshr <8 x i16> %b, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 57 %3 = icmp ugt <8 x i16> %1, %2 58 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2 59 ret <8 x i16> %4 60} 61 62define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) { 63; SSE-LABEL: test_v16i8_reassociation: 64; SSE: # %bb.0: 65; SSE-NEXT: pminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 66; SSE-NEXT: retq 67; 68; AVX-LABEL: test_v16i8_reassociation: 69; AVX: # %bb.0: 70; AVX-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 71; AVX-NEXT: retq 72 %1 = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>) 73 %2 = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>) 74 ret <16 x i8> %2 75} 76 77define <16 x i8> @test_v16i8_demandedbits(<16 x i8> %x, <16 x i8> %y, <16 x i8> %a, <16 x i8> %b) { 78; SSE2-LABEL: test_v16i8_demandedbits: 79; SSE2: # %bb.0: 80; SSE2-NEXT: pminub %xmm1, %xmm0 81; SSE2-NEXT: pxor %xmm1, %xmm1 82; SSE2-NEXT: pcmpgtb %xmm0, %xmm1 83; SSE2-NEXT: pand %xmm1, %xmm3 84; SSE2-NEXT: pandn %xmm2, %xmm1 85; SSE2-NEXT: por %xmm3, %xmm1 86; SSE2-NEXT: movdqa %xmm1, %xmm0 87; SSE2-NEXT: retq 88; 89; SSE41-LABEL: test_v16i8_demandedbits: 90; SSE41: # %bb.0: 91; SSE41-NEXT: andps %xmm1, %xmm0 92; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2 93; SSE41-NEXT: movdqa %xmm2, %xmm0 94; SSE41-NEXT: retq 95; 96; SSE42-LABEL: test_v16i8_demandedbits: 97; SSE42: # %bb.0: 98; SSE42-NEXT: andps %xmm1, %xmm0 99; SSE42-NEXT: pblendvb %xmm0, %xmm3, %xmm2 100; SSE42-NEXT: movdqa %xmm2, %xmm0 101; SSE42-NEXT: retq 102; 103; AVX1OR2-LABEL: test_v16i8_demandedbits: 104; AVX1OR2: # %bb.0: 105; AVX1OR2-NEXT: vpand %xmm1, %xmm0, %xmm0 106; AVX1OR2-NEXT: vpblendvb %xmm0, %xmm3, %xmm2, %xmm0 107; AVX1OR2-NEXT: retq 108; 109; AVX512F-LABEL: test_v16i8_demandedbits: 110; AVX512F: # %bb.0: 111; AVX512F-NEXT: vpand %xmm1, %xmm0, %xmm0 112; AVX512F-NEXT: vpblendvb %xmm0, %xmm3, %xmm2, %xmm0 113; AVX512F-NEXT: retq 114; 115; AVX512BW-LABEL: test_v16i8_demandedbits: 116; AVX512BW: # %bb.0: 117; AVX512BW-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 118; AVX512BW-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 119; AVX512BW-NEXT: vpminub %xmm1, %xmm0, %xmm0 120; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1 121; AVX512BW-NEXT: vpcmpnltb %zmm1, %zmm0, %k1 122; AVX512BW-NEXT: vpblendmb %zmm2, %zmm3, %zmm0 {%k1} 123; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 124; AVX512BW-NEXT: vzeroupper 125; AVX512BW-NEXT: retq 126 %umin = tail call <16 x i8> @llvm.umin.v16i8(<16 x i8> %x, <16 x i8> %y) 127 %cmp = icmp sge <16 x i8> %umin, zeroinitializer 128 %res = select <16 x i1> %cmp, <16 x i8> %a, <16 x i8> %b 129 ret <16 x i8> %res 130} 131 132declare <16 x i8> @llvm.umin.v16i8(<16 x i8> %x, <16 x i8> %y) 133