xref: /llvm-project/llvm/test/CodeGen/X86/combine-andintoload.ll (revision f0dd12ec5c0169ba5b4363b62d59511181cf954a)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-none-eabi -o - | FileCheck %s
3
4define zeroext i1 @bigger(ptr nocapture readonly %c, ptr nocapture readonly %e, i64 %d, i64 %p1) {
5; CHECK-LABEL: bigger:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    andb $7, %cl
8; CHECK-NEXT:    movb $8, %al
9; CHECK-NEXT:    subb %cl, %al
10; CHECK-NEXT:    movl $5, %r8d
11; CHECK-NEXT:    movl %eax, %ecx
12; CHECK-NEXT:    shll %cl, %r8d
13; CHECK-NEXT:    movzbl (%rsi,%rdx), %eax
14; CHECK-NEXT:    xorb (%rdi,%rdx), %al
15; CHECK-NEXT:    movzbl %al, %eax
16; CHECK-NEXT:    andl %r8d, %eax
17; CHECK-NEXT:    testb $-1, %al
18; CHECK-NEXT:    sete %al
19; CHECK-NEXT:    retq
20entry:
21  %0 = trunc i64 %p1 to i16
22  %1 = and i16 %0, 7
23  %sh_prom = sub nuw nsw i16 8, %1
24  %shl = shl nuw nsw i16 5, %sh_prom
25  %arrayidx = getelementptr inbounds i8, ptr %c, i64 %d
26  %2 = load i8, ptr %arrayidx, align 1
27  %3 = and i16 %shl, 255
28  %conv2 = zext i16 %3 to i32
29  %arrayidx3 = getelementptr inbounds i8, ptr %e, i64 %d
30  %4 = load i8, ptr %arrayidx3, align 1
31  %5 = xor i8 %4, %2
32  %6 = zext i8 %5 to i32
33  %7 = and i32 %6, %conv2
34  %cmp.not = icmp eq i32 %7, 0
35  ret i1 %cmp.not
36}
37