xref: /llvm-project/llvm/test/CodeGen/X86/combine-addo.ll (revision b5d35feacb7246573c6a4ab2bddc4919a4228ed5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
4
5declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
6declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
7
8declare {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
9declare {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
10
11; fold (sadd x, 0) -> x
12define i32 @combine_sadd_zero(i32 %a0, i32 %a1) {
13; CHECK-LABEL: combine_sadd_zero:
14; CHECK:       # %bb.0:
15; CHECK-NEXT:    movl %edi, %eax
16; CHECK-NEXT:    retq
17  %1 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a0, i32 zeroinitializer)
18  %2 = extractvalue {i32, i1} %1, 0
19  %3 = extractvalue {i32, i1} %1, 1
20  %4 = select i1 %3, i32 %a1, i32 %2
21  ret i32 %4
22}
23
24define <4 x i32> @combine_vec_sadd_zero(<4 x i32> %a0, <4 x i32> %a1) {
25; CHECK-LABEL: combine_vec_sadd_zero:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    retq
28  %1 = call {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
29  %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
30  %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
31  %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
32  ret <4 x i32> %4
33}
34
35; fold (uadd x, 0) -> x
36define i32 @combine_uadd_zero(i32 %a0, i32 %a1) {
37; CHECK-LABEL: combine_uadd_zero:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    movl %edi, %eax
40; CHECK-NEXT:    retq
41  %1 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a0, i32 zeroinitializer)
42  %2 = extractvalue {i32, i1} %1, 0
43  %3 = extractvalue {i32, i1} %1, 1
44  %4 = select i1 %3, i32 %a1, i32 %2
45  ret i32 %4
46}
47
48define <4 x i32> @combine_vec_uadd_zero(<4 x i32> %a0, <4 x i32> %a1) {
49; CHECK-LABEL: combine_vec_uadd_zero:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    retq
52  %1 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
53  %2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
54  %3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
55  %4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
56  ret <4 x i32> %4
57}
58
59; fold (uadd (xor a, -1), 1) -> (usub 0, a) and flip carry
60define i32 @combine_uadd_not(i32 %a0, i32 %a1) {
61; CHECK-LABEL: combine_uadd_not:
62; CHECK:       # %bb.0:
63; CHECK-NEXT:    movl %edi, %eax
64; CHECK-NEXT:    negl %eax
65; CHECK-NEXT:    cmovael %esi, %eax
66; CHECK-NEXT:    retq
67  %1 = xor i32 %a0, -1
68  %2 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 1)
69  %3 = extractvalue {i32, i1} %2, 0
70  %4 = extractvalue {i32, i1} %2, 1
71  %5 = select i1 %4, i32 %a1, i32 %3
72  ret i32 %5
73}
74
75define <4 x i32> @combine_vec_uadd_not(<4 x i32> %a0, <4 x i32> %a1) {
76; SSE-LABEL: combine_vec_uadd_not:
77; SSE:       # %bb.0:
78; SSE-NEXT:    pxor %xmm2, %xmm2
79; SSE-NEXT:    psubd %xmm0, %xmm2
80; SSE-NEXT:    pmovsxbd {{.*#+}} xmm0 = [1,1,1,1]
81; SSE-NEXT:    pmaxud %xmm2, %xmm0
82; SSE-NEXT:    pcmpeqd %xmm2, %xmm0
83; SSE-NEXT:    blendvps %xmm0, %xmm2, %xmm1
84; SSE-NEXT:    movaps %xmm1, %xmm0
85; SSE-NEXT:    retq
86;
87; AVX-LABEL: combine_vec_uadd_not:
88; AVX:       # %bb.0:
89; AVX-NEXT:    vpxor %xmm2, %xmm2, %xmm2
90; AVX-NEXT:    vpsubd %xmm0, %xmm2, %xmm0
91; AVX-NEXT:    vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1]
92; AVX-NEXT:    vpmaxud %xmm2, %xmm0, %xmm2
93; AVX-NEXT:    vpcmpeqd %xmm2, %xmm0, %xmm2
94; AVX-NEXT:    vblendvps %xmm2, %xmm0, %xmm1, %xmm0
95; AVX-NEXT:    retq
96  %1 = xor <4 x i32> %a0, <i32 -1, i32 -1, i32 -1, i32 -1>
97  %2 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
98  %3 = extractvalue {<4 x i32>, <4 x i1>} %2, 0
99  %4 = extractvalue {<4 x i32>, <4 x i1>} %2, 1
100  %5 = select <4 x i1> %4, <4 x i32> %a1, <4 x i32> %3
101  ret <4 x i32> %5
102}
103
104; if uaddo never overflows, replace with add
105define i32 @combine_uadd_no_overflow(i32 %a0, i32 %a1, i32 %a2) {
106; CHECK-LABEL: combine_uadd_no_overflow:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    # kill: def $edx killed $edx def $rdx
109; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
110; CHECK-NEXT:    shrl $16, %esi
111; CHECK-NEXT:    shrl $16, %edx
112; CHECK-NEXT:    leal (%rdx,%rsi), %eax
113; CHECK-NEXT:    retq
114  %1 = lshr i32 %a1, 16
115  %2 = lshr i32 %a2, 16
116  %3 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 %2)
117  %4 = extractvalue {i32, i1} %3, 0
118  %5 = extractvalue {i32, i1} %3, 1
119  %6 = select i1 %5, i32 %a2, i32 %4
120  ret i32 %4
121}
122
123define <4 x i32> @combine_vec_uadd_no_overflow(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
124; SSE-LABEL: combine_vec_uadd_no_overflow:
125; SSE:       # %bb.0:
126; SSE-NEXT:    movdqa %xmm2, %xmm0
127; SSE-NEXT:    psrld $16, %xmm1
128; SSE-NEXT:    psrld $16, %xmm0
129; SSE-NEXT:    paddd %xmm1, %xmm0
130; SSE-NEXT:    retq
131;
132; AVX-LABEL: combine_vec_uadd_no_overflow:
133; AVX:       # %bb.0:
134; AVX-NEXT:    vpsrld $16, %xmm1, %xmm0
135; AVX-NEXT:    vpsrld $16, %xmm2, %xmm1
136; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
137; AVX-NEXT:    retq
138  %1 = lshr <4 x i32> %a1, <i32 16, i32 16, i32 16, i32 16>
139  %2 = lshr <4 x i32> %a2, <i32 16, i32 16, i32 16, i32 16>
140  %3 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> %2)
141  %4 = extractvalue {<4 x i32>, <4 x i1>} %3, 0
142  %5 = extractvalue {<4 x i32>, <4 x i1>} %3, 1
143  %6 = select <4 x i1> %5, <4 x i32> %a2, <4 x i32> %4
144  ret <4 x i32> %4
145}
146