1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-NOBMI,CHECK-NOBMI-SSE2 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2 | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-BMI2-SSE2 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX12,CHECK-AVX1 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx2 | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX12,CHECK-AVX2 6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX512 7declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 8declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) 9declare <16 x i16> @llvm.fshl.v16i16(<16 x i16>, <16 x i16>, <16 x i16>) 10declare <16 x i16> @llvm.fshr.v16i16(<16 x i16>, <16 x i16>, <16 x i16>) 11declare i64 @llvm.fshl.i64(i64, i64, i64) 12declare i64 @llvm.fshr.i64(i64, i64, i64) 13declare i32 @llvm.fshl.i32(i32, i32, i32) 14declare i32 @llvm.fshr.i32(i32, i32, i32) 15declare i16 @llvm.fshl.i16(i16, i16, i16) 16declare i16 @llvm.fshr.i16(i16, i16, i16) 17declare i8 @llvm.fshl.i8(i8, i8, i8) 18declare i8 @llvm.fshr.i8(i8, i8, i8) 19 20define i1 @shr_to_shl_eq_i8_s2(i8 %x) { 21; CHECK-LABEL: shr_to_shl_eq_i8_s2: 22; CHECK: # %bb.0: 23; CHECK-NEXT: movl %edi, %eax 24; CHECK-NEXT: rolb $2, %al 25; CHECK-NEXT: cmpb %al, %dil 26; CHECK-NEXT: sete %al 27; CHECK-NEXT: retq 28 %and = and i8 %x, 63 29 %shr = lshr i8 %x, 2 30 %r = icmp eq i8 %and, %shr 31 ret i1 %r 32} 33 34define i1 @shl_to_shr_ne_i8_s7(i8 %x) { 35; CHECK-LABEL: shl_to_shr_ne_i8_s7: 36; CHECK: # %bb.0: 37; CHECK-NEXT: movl %edi, %eax 38; CHECK-NEXT: shrb $7, %al 39; CHECK-NEXT: andb $1, %dil 40; CHECK-NEXT: cmpb %al, %dil 41; CHECK-NEXT: setne %al 42; CHECK-NEXT: retq 43 %shl = shl i8 %x, 7 44 %and = and i8 %x, 128 45 %r = icmp ne i8 %shl, %and 46 ret i1 %r 47} 48 49define i1 @rorl_to_srl_ne_i8_s5_fail(i8 %x) { 50; CHECK-LABEL: rorl_to_srl_ne_i8_s5_fail: 51; CHECK: # %bb.0: 52; CHECK-NEXT: movl %edi, %eax 53; CHECK-NEXT: rolb $5, %al 54; CHECK-NEXT: cmpb %dil, %al 55; CHECK-NEXT: setne %al 56; CHECK-NEXT: retq 57 %ror = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 5) 58 %r = icmp ne i8 %ror, %x 59 ret i1 %r 60} 61 62define i1 @shr_to_shl_eq_i8_s1(i8 %x) { 63; CHECK-LABEL: shr_to_shl_eq_i8_s1: 64; CHECK: # %bb.0: 65; CHECK-NEXT: movl %edi, %eax 66; CHECK-NEXT: rolb %al 67; CHECK-NEXT: cmpb %al, %dil 68; CHECK-NEXT: sete %al 69; CHECK-NEXT: retq 70 %and = and i8 %x, 127 71 %shr = lshr i8 %x, 1 72 %r = icmp eq i8 %and, %shr 73 ret i1 %r 74} 75 76define i1 @shr_to_shl_eq_i32_s3(i32 %x) { 77; CHECK-LABEL: shr_to_shl_eq_i32_s3: 78; CHECK: # %bb.0: 79; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 80; CHECK-NEXT: leal (,%rdi,8), %eax 81; CHECK-NEXT: andl $-8, %edi 82; CHECK-NEXT: cmpl %eax, %edi 83; CHECK-NEXT: sete %al 84; CHECK-NEXT: retq 85 %and = and i32 %x, 536870911 86 %shr = lshr i32 %x, 3 87 %r = icmp eq i32 %and, %shr 88 ret i1 %r 89} 90 91define i1 @shl_to_shr_eq_i32_s3_fail(i32 %x) { 92; CHECK-LABEL: shl_to_shr_eq_i32_s3_fail: 93; CHECK: # %bb.0: 94; CHECK-NEXT: movl %edi, %eax 95; CHECK-NEXT: andl $536870911, %eax # imm = 0x1FFFFFFF 96; CHECK-NEXT: shll $3, %edi 97; CHECK-NEXT: cmpl %edi, %eax 98; CHECK-NEXT: sete %al 99; CHECK-NEXT: retq 100 %and = and i32 %x, 536870911 101 %shr = shl i32 %x, 3 102 %r = icmp eq i32 %and, %shr 103 ret i1 %r 104} 105 106define i1 @shl_to_shr_ne_i32_s16(i32 %x) { 107; CHECK-NOBMI-LABEL: shl_to_shr_ne_i32_s16: 108; CHECK-NOBMI: # %bb.0: 109; CHECK-NOBMI-NEXT: movzwl %di, %eax 110; CHECK-NOBMI-NEXT: shrl $16, %edi 111; CHECK-NOBMI-NEXT: cmpl %edi, %eax 112; CHECK-NOBMI-NEXT: setne %al 113; CHECK-NOBMI-NEXT: retq 114; 115; CHECK-BMI2-LABEL: shl_to_shr_ne_i32_s16: 116; CHECK-BMI2: # %bb.0: 117; CHECK-BMI2-NEXT: rorxl $16, %edi, %eax 118; CHECK-BMI2-NEXT: cmpl %eax, %edi 119; CHECK-BMI2-NEXT: setne %al 120; CHECK-BMI2-NEXT: retq 121 %shl = shl i32 %x, 16 122 %and = and i32 %x, 4294901760 123 %r = icmp ne i32 %shl, %and 124 ret i1 %r 125} 126 127define i1 @shl_to_shr_ne_i32_s16_fail(i32 %x) { 128; CHECK-LABEL: shl_to_shr_ne_i32_s16_fail: 129; CHECK: # %bb.0: 130; CHECK-NEXT: movl %edi, %eax 131; CHECK-NEXT: shll $16, %eax 132; CHECK-NEXT: andl $2147450880, %edi # imm = 0x7FFF8000 133; CHECK-NEXT: cmpl %edi, %eax 134; CHECK-NEXT: setne %al 135; CHECK-NEXT: retq 136 %shl = shl i32 %x, 16 137 %and = and i32 %x, 2147450880 138 %r = icmp ne i32 %shl, %and 139 ret i1 %r 140} 141 142define i1 @shr_to_shl_eq_i16_s1(i16 %x) { 143; CHECK-LABEL: shr_to_shl_eq_i16_s1: 144; CHECK: # %bb.0: 145; CHECK-NEXT: movl %edi, %eax 146; CHECK-NEXT: rolw %ax 147; CHECK-NEXT: cmpw %ax, %di 148; CHECK-NEXT: sete %al 149; CHECK-NEXT: retq 150 %and = and i16 %x, 32767 151 %shr = lshr i16 %x, 1 152 %r = icmp eq i16 %and, %shr 153 ret i1 %r 154} 155 156define i1 @shr_to_shl_eq_i16_s1_fail(i16 %x) { 157; CHECK-LABEL: shr_to_shl_eq_i16_s1_fail: 158; CHECK: # %bb.0: 159; CHECK-NEXT: movzwl %di, %eax 160; CHECK-NEXT: andl $32766, %edi # imm = 0x7FFE 161; CHECK-NEXT: shrl %eax 162; CHECK-NEXT: cmpw %ax, %di 163; CHECK-NEXT: sete %al 164; CHECK-NEXT: retq 165 %and = and i16 %x, 32766 166 %shr = lshr i16 %x, 1 167 %r = icmp eq i16 %and, %shr 168 ret i1 %r 169} 170 171define i1 @shl_to_shr_eq_i64_s44(i64 %x) { 172; CHECK-LABEL: shl_to_shr_eq_i64_s44: 173; CHECK: # %bb.0: 174; CHECK-NEXT: movq %rdi, %rax 175; CHECK-NEXT: shrq $44, %rax 176; CHECK-NEXT: andl $1048575, %edi # imm = 0xFFFFF 177; CHECK-NEXT: cmpl %eax, %edi 178; CHECK-NEXT: sete %al 179; CHECK-NEXT: retq 180 %shl = shl i64 %x, 44 181 %and = and i64 %x, 18446726481523507200 182 %r = icmp eq i64 %shl, %and 183 ret i1 %r 184} 185 186define i1 @shr_to_shl_ne_i64_s32(i64 %x) { 187; CHECK-NOBMI-LABEL: shr_to_shl_ne_i64_s32: 188; CHECK-NOBMI: # %bb.0: 189; CHECK-NOBMI-NEXT: movq %rdi, %rax 190; CHECK-NOBMI-NEXT: shrq $32, %rax 191; CHECK-NOBMI-NEXT: cmpl %eax, %edi 192; CHECK-NOBMI-NEXT: setne %al 193; CHECK-NOBMI-NEXT: retq 194; 195; CHECK-BMI2-LABEL: shr_to_shl_ne_i64_s32: 196; CHECK-BMI2: # %bb.0: 197; CHECK-BMI2-NEXT: rorxq $32, %rdi, %rax 198; CHECK-BMI2-NEXT: cmpq %rax, %rdi 199; CHECK-BMI2-NEXT: setne %al 200; CHECK-BMI2-NEXT: retq 201 %and = and i64 %x, 4294967295 202 %shr = lshr i64 %x, 32 203 %r = icmp ne i64 %and, %shr 204 ret i1 %r 205} 206 207define i1 @rorl_to_shl_eq_i64_s16(i64 %x) { 208; CHECK-NOBMI-LABEL: rorl_to_shl_eq_i64_s16: 209; CHECK-NOBMI: # %bb.0: 210; CHECK-NOBMI-NEXT: movq %rdi, %rax 211; CHECK-NOBMI-NEXT: rolq $16, %rax 212; CHECK-NOBMI-NEXT: cmpq %rdi, %rax 213; CHECK-NOBMI-NEXT: sete %al 214; CHECK-NOBMI-NEXT: retq 215; 216; CHECK-BMI2-LABEL: rorl_to_shl_eq_i64_s16: 217; CHECK-BMI2: # %bb.0: 218; CHECK-BMI2-NEXT: rorxq $48, %rdi, %rax 219; CHECK-BMI2-NEXT: cmpq %rdi, %rax 220; CHECK-BMI2-NEXT: sete %al 221; CHECK-BMI2-NEXT: retq 222 %ror = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 16) 223 %r = icmp eq i64 %ror, %x 224 ret i1 %r 225} 226 227define i1 @ashr_to_shl_ne_i64_s32_fail(i64 %x) { 228; CHECK-LABEL: ashr_to_shl_ne_i64_s32_fail: 229; CHECK: # %bb.0: 230; CHECK-NEXT: movl %edi, %eax 231; CHECK-NEXT: sarq $32, %rdi 232; CHECK-NEXT: cmpq %rdi, %rax 233; CHECK-NEXT: setne %al 234; CHECK-NEXT: retq 235 %and = and i64 %x, 4294967295 236 %shr = ashr i64 %x, 32 237 %r = icmp ne i64 %and, %shr 238 ret i1 %r 239} 240 241define i1 @shl_to_shr_eq_i64_s63(i64 %x) { 242; CHECK-LABEL: shl_to_shr_eq_i64_s63: 243; CHECK: # %bb.0: 244; CHECK-NEXT: movq %rdi, %rax 245; CHECK-NEXT: shrq $63, %rax 246; CHECK-NEXT: andl $1, %edi 247; CHECK-NEXT: cmpl %eax, %edi 248; CHECK-NEXT: sete %al 249; CHECK-NEXT: retq 250 %shl = shl i64 %x, 63 251 %and = and i64 %x, 9223372036854775808 252 %r = icmp eq i64 %shl, %and 253 ret i1 %r 254} 255 256define i1 @shl_to_shr_eq_i64_s63_fail(i64 %x) { 257; CHECK-LABEL: shl_to_shr_eq_i64_s63_fail: 258; CHECK: # %bb.0: 259; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000 260; CHECK-NEXT: andq %rdi, %rax 261; CHECK-NEXT: shlq $63, %rdi 262; CHECK-NEXT: cmpq %rax, %rdi 263; CHECK-NEXT: seta %al 264; CHECK-NEXT: retq 265 %shl = shl i64 %x, 63 266 %and = and i64 %x, 9223372036854775808 267 %r = icmp ugt i64 %shl, %and 268 ret i1 %r 269} 270 271define i1 @shr_to_shl_eq_i64_s7(i64 %x) { 272; CHECK-LABEL: shr_to_shl_eq_i64_s7: 273; CHECK: # %bb.0: 274; CHECK-NEXT: movq %rdi, %rax 275; CHECK-NEXT: shlq $7, %rax 276; CHECK-NEXT: andq $-128, %rdi 277; CHECK-NEXT: cmpq %rax, %rdi 278; CHECK-NEXT: sete %al 279; CHECK-NEXT: retq 280 %and = and i64 %x, 144115188075855871 281 %shr = lshr i64 %x, 7 282 %r = icmp eq i64 %and, %shr 283 ret i1 %r 284} 285 286define i1 @shl_to_shr_ne_i32_s24(i32 %x) { 287; CHECK-LABEL: shl_to_shr_ne_i32_s24: 288; CHECK: # %bb.0: 289; CHECK-NEXT: movzbl %dil, %eax 290; CHECK-NEXT: shrl $24, %edi 291; CHECK-NEXT: cmpl %edi, %eax 292; CHECK-NEXT: setne %al 293; CHECK-NEXT: retq 294 %shl = shl i32 %x, 24 295 %and = and i32 %x, 4278190080 296 %r = icmp ne i32 %shl, %and 297 ret i1 %r 298} 299 300define i1 @shr_to_shl_ne_i32_s24_fail(i32 %x) { 301; CHECK-LABEL: shr_to_shl_ne_i32_s24_fail: 302; CHECK: # %bb.0: 303; CHECK-NEXT: movl %edi, %eax 304; CHECK-NEXT: shrl $24, %eax 305; CHECK-NEXT: andl $-16777216, %edi # imm = 0xFF000000 306; CHECK-NEXT: cmpl %edi, %eax 307; CHECK-NEXT: setne %al 308; CHECK-NEXT: retq 309 %shl = lshr i32 %x, 24 310 %and = and i32 %x, 4278190080 311 %r = icmp ne i32 %shl, %and 312 ret i1 %r 313} 314 315define i1 @shr_to_shl_ne_i32_s8(i32 %x) { 316; CHECK-NOBMI-LABEL: shr_to_shl_ne_i32_s8: 317; CHECK-NOBMI: # %bb.0: 318; CHECK-NOBMI-NEXT: movl %edi, %eax 319; CHECK-NOBMI-NEXT: roll $8, %eax 320; CHECK-NOBMI-NEXT: cmpl %eax, %edi 321; CHECK-NOBMI-NEXT: setne %al 322; CHECK-NOBMI-NEXT: retq 323; 324; CHECK-BMI2-LABEL: shr_to_shl_ne_i32_s8: 325; CHECK-BMI2: # %bb.0: 326; CHECK-BMI2-NEXT: rorxl $24, %edi, %eax 327; CHECK-BMI2-NEXT: cmpl %eax, %edi 328; CHECK-BMI2-NEXT: setne %al 329; CHECK-BMI2-NEXT: retq 330 %and = and i32 %x, 16777215 331 %shr = lshr i32 %x, 8 332 %r = icmp ne i32 %and, %shr 333 ret i1 %r 334} 335 336define <4 x i1> @shr_to_ror_eq_4xi32_s4(<4 x i32> %x) { 337; CHECK-NOBMI-LABEL: shr_to_ror_eq_4xi32_s4: 338; CHECK-NOBMI: # %bb.0: 339; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1 340; CHECK-NOBMI-NEXT: psrld $4, %xmm1 341; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 342; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0 343; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1 344; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0 345; CHECK-NOBMI-NEXT: retq 346; 347; CHECK-BMI2-SSE2-LABEL: shr_to_ror_eq_4xi32_s4: 348; CHECK-BMI2-SSE2: # %bb.0: 349; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1 350; CHECK-BMI2-SSE2-NEXT: psrld $4, %xmm1 351; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 352; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 353; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1 354; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0 355; CHECK-BMI2-SSE2-NEXT: retq 356; 357; CHECK-AVX1-LABEL: shr_to_ror_eq_4xi32_s4: 358; CHECK-AVX1: # %bb.0: 359; CHECK-AVX1-NEXT: vpsrld $4, %xmm0, %xmm1 360; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 361; CHECK-AVX1-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 362; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 363; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 364; CHECK-AVX1-NEXT: retq 365; 366; CHECK-AVX2-LABEL: shr_to_ror_eq_4xi32_s4: 367; CHECK-AVX2: # %bb.0: 368; CHECK-AVX2-NEXT: vpsrld $4, %xmm0, %xmm1 369; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [268435455,268435455,268435455,268435455] 370; CHECK-AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 371; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 372; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 373; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 374; CHECK-AVX2-NEXT: retq 375; 376; CHECK-AVX512-LABEL: shr_to_ror_eq_4xi32_s4: 377; CHECK-AVX512: # %bb.0: 378; CHECK-AVX512-NEXT: vprold $4, %xmm0, %xmm1 379; CHECK-AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 380; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 381; CHECK-AVX512-NEXT: retq 382 %shr = lshr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4> 383 %and = and <4 x i32> %x, <i32 268435455, i32 268435455, i32 268435455, i32 268435455> 384 %r = icmp ne <4 x i32> %shr, %and 385 ret <4 x i1> %r 386} 387 388define <4 x i1> @shl_to_ror_eq_4xi32_s8(<4 x i32> %x) { 389; CHECK-NOBMI-LABEL: shl_to_ror_eq_4xi32_s8: 390; CHECK-NOBMI: # %bb.0: 391; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1 392; CHECK-NOBMI-NEXT: pslld $8, %xmm1 393; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 394; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0 395; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1 396; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0 397; CHECK-NOBMI-NEXT: retq 398; 399; CHECK-BMI2-SSE2-LABEL: shl_to_ror_eq_4xi32_s8: 400; CHECK-BMI2-SSE2: # %bb.0: 401; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1 402; CHECK-BMI2-SSE2-NEXT: pslld $8, %xmm1 403; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 404; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 405; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1 406; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0 407; CHECK-BMI2-SSE2-NEXT: retq 408; 409; CHECK-AVX12-LABEL: shl_to_ror_eq_4xi32_s8: 410; CHECK-AVX12: # %bb.0: 411; CHECK-AVX12-NEXT: vpslld $8, %xmm0, %xmm1 412; CHECK-AVX12-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 413; CHECK-AVX12-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 414; CHECK-AVX12-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 415; CHECK-AVX12-NEXT: vpxor %xmm1, %xmm0, %xmm0 416; CHECK-AVX12-NEXT: retq 417; 418; CHECK-AVX512-LABEL: shl_to_ror_eq_4xi32_s8: 419; CHECK-AVX512: # %bb.0: 420; CHECK-AVX512-NEXT: vprold $8, %xmm0, %xmm1 421; CHECK-AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 422; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 423; CHECK-AVX512-NEXT: retq 424 %shr = shl <4 x i32> %x, <i32 8, i32 8, i32 8, i32 8> 425 %and = and <4 x i32> %x, <i32 4294967040, i32 4294967040, i32 4294967040, i32 4294967040> 426 %r = icmp ne <4 x i32> %shr, %and 427 ret <4 x i1> %r 428} 429 430define <4 x i1> @shl_to_ror_eq_4xi32_s7_fail_no_p2(<4 x i32> %x) { 431; CHECK-NOBMI-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2: 432; CHECK-NOBMI: # %bb.0: 433; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1 434; CHECK-NOBMI-NEXT: pslld $7, %xmm1 435; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 436; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0 437; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1 438; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0 439; CHECK-NOBMI-NEXT: retq 440; 441; CHECK-BMI2-SSE2-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2: 442; CHECK-BMI2-SSE2: # %bb.0: 443; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1 444; CHECK-BMI2-SSE2-NEXT: pslld $7, %xmm1 445; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 446; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 447; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1 448; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0 449; CHECK-BMI2-SSE2-NEXT: retq 450; 451; CHECK-AVX1-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2: 452; CHECK-AVX1: # %bb.0: 453; CHECK-AVX1-NEXT: vpslld $7, %xmm0, %xmm1 454; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 455; CHECK-AVX1-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 456; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 457; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 458; CHECK-AVX1-NEXT: retq 459; 460; CHECK-AVX2-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2: 461; CHECK-AVX2: # %bb.0: 462; CHECK-AVX2-NEXT: vpslld $7, %xmm0, %xmm1 463; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4294967168,4294967168,4294967168,4294967168] 464; CHECK-AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 465; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 466; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 467; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 468; CHECK-AVX2-NEXT: retq 469; 470; CHECK-AVX512-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2: 471; CHECK-AVX512: # %bb.0: 472; CHECK-AVX512-NEXT: vpslld $7, %xmm0, %xmm1 473; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 474; CHECK-AVX512-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 475; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 476; CHECK-AVX512-NEXT: retq 477 %shr = shl <4 x i32> %x, <i32 7, i32 7, i32 7, i32 7> 478 %and = and <4 x i32> %x, <i32 4294967168, i32 4294967168, i32 4294967168, i32 4294967168> 479 %r = icmp ne <4 x i32> %shr, %and 480 ret <4 x i1> %r 481} 482 483define <4 x i1> @shr_to_ror_eq_4xi32_s4_fail_no_splat(<4 x i32> %x) { 484; CHECK-NOBMI-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat: 485; CHECK-NOBMI: # %bb.0: 486; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1 487; CHECK-NOBMI-NEXT: psrld $4, %xmm1 488; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm2 489; CHECK-NOBMI-NEXT: psrld $8, %xmm2 490; CHECK-NOBMI-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm1[2,0] 491; CHECK-NOBMI-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0] 492; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 493; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0 494; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1 495; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0 496; CHECK-NOBMI-NEXT: retq 497; 498; CHECK-BMI2-SSE2-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat: 499; CHECK-BMI2-SSE2: # %bb.0: 500; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1 501; CHECK-BMI2-SSE2-NEXT: psrld $4, %xmm1 502; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm2 503; CHECK-BMI2-SSE2-NEXT: psrld $8, %xmm2 504; CHECK-BMI2-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm1[2,0] 505; CHECK-BMI2-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0] 506; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 507; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 508; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1 509; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0 510; CHECK-BMI2-SSE2-NEXT: retq 511; 512; CHECK-AVX1-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat: 513; CHECK-AVX1: # %bb.0: 514; CHECK-AVX1-NEXT: vpsrld $8, %xmm0, %xmm1 515; CHECK-AVX1-NEXT: vpsrld $4, %xmm0, %xmm2 516; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3,4,5],xmm1[6,7] 517; CHECK-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 518; CHECK-AVX1-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 519; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 520; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 521; CHECK-AVX1-NEXT: retq 522; 523; CHECK-AVX2-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat: 524; CHECK-AVX2: # %bb.0: 525; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 526; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [268435455,268435455,268435455,268435455] 527; CHECK-AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 528; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 529; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 530; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 531; CHECK-AVX2-NEXT: retq 532; 533; CHECK-AVX512-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat: 534; CHECK-AVX512: # %bb.0: 535; CHECK-AVX512-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 536; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 537; CHECK-AVX512-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0 538; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 539; CHECK-AVX512-NEXT: retq 540 %shr = lshr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 8> 541 %and = and <4 x i32> %x, <i32 268435455, i32 268435455, i32 268435455, i32 268435455> 542 %r = icmp ne <4 x i32> %shr, %and 543 ret <4 x i1> %r 544} 545 546define <16 x i1> @shl_to_ror_eq_16xi16_s8_fail_preserve_i16(<16 x i16> %x) { 547; CHECK-NOBMI-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16: 548; CHECK-NOBMI: # %bb.0: 549; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm2 550; CHECK-NOBMI-NEXT: psllw $8, %xmm2 551; CHECK-NOBMI-NEXT: movdqa %xmm1, %xmm3 552; CHECK-NOBMI-NEXT: psllw $8, %xmm3 553; CHECK-NOBMI-NEXT: movdqa {{.*#+}} xmm4 = [0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255] 554; CHECK-NOBMI-NEXT: pand %xmm4, %xmm0 555; CHECK-NOBMI-NEXT: pcmpeqw %xmm2, %xmm0 556; CHECK-NOBMI-NEXT: pand %xmm4, %xmm1 557; CHECK-NOBMI-NEXT: pcmpeqw %xmm3, %xmm1 558; CHECK-NOBMI-NEXT: packsswb %xmm1, %xmm0 559; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1 560; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0 561; CHECK-NOBMI-NEXT: retq 562; 563; CHECK-BMI2-SSE2-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16: 564; CHECK-BMI2-SSE2: # %bb.0: 565; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm2 566; CHECK-BMI2-SSE2-NEXT: psllw $8, %xmm2 567; CHECK-BMI2-SSE2-NEXT: movdqa %xmm1, %xmm3 568; CHECK-BMI2-SSE2-NEXT: psllw $8, %xmm3 569; CHECK-BMI2-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255] 570; CHECK-BMI2-SSE2-NEXT: pand %xmm4, %xmm0 571; CHECK-BMI2-SSE2-NEXT: pcmpeqw %xmm2, %xmm0 572; CHECK-BMI2-SSE2-NEXT: pand %xmm4, %xmm1 573; CHECK-BMI2-SSE2-NEXT: pcmpeqw %xmm3, %xmm1 574; CHECK-BMI2-SSE2-NEXT: packsswb %xmm1, %xmm0 575; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1 576; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0 577; CHECK-BMI2-SSE2-NEXT: retq 578; 579; CHECK-AVX1-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16: 580; CHECK-AVX1: # %bb.0: 581; CHECK-AVX1-NEXT: vpsllw $8, %xmm0, %xmm1 582; CHECK-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 583; CHECK-AVX1-NEXT: vpsllw $8, %xmm2, %xmm2 584; CHECK-AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 585; CHECK-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 586; CHECK-AVX1-NEXT: vpcmpeqw %xmm3, %xmm2, %xmm2 587; CHECK-AVX1-NEXT: vpcmpeqw %xmm0, %xmm1, %xmm0 588; CHECK-AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0 589; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 590; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0 591; CHECK-AVX1-NEXT: vzeroupper 592; CHECK-AVX1-NEXT: retq 593; 594; CHECK-AVX2-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16: 595; CHECK-AVX2: # %bb.0: 596; CHECK-AVX2-NEXT: vpsllw $8, %ymm0, %ymm1 597; CHECK-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 598; CHECK-AVX2-NEXT: vpcmpeqw %ymm0, %ymm1, %ymm0 599; CHECK-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 600; CHECK-AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 601; CHECK-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 602; CHECK-AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 603; CHECK-AVX2-NEXT: vzeroupper 604; CHECK-AVX2-NEXT: retq 605; 606; CHECK-AVX512-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16: 607; CHECK-AVX512: # %bb.0: 608; CHECK-AVX512-NEXT: vpsllw $8, %ymm0, %ymm1 609; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0 610; CHECK-AVX512-NEXT: vpcmpeqw %ymm0, %ymm1, %ymm0 611; CHECK-AVX512-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero 612; CHECK-AVX512-NEXT: vpmovdb %zmm0, %xmm0 613; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 614; CHECK-AVX512-NEXT: vzeroupper 615; CHECK-AVX512-NEXT: retq 616 %shr = shl <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> 617 %and = and <16 x i16> %x, <i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040> 618 %r = icmp ne <16 x i16> %shr, %and 619 ret <16 x i1> %r 620} 621 622define <16 x i8> @shl_s3_cmp_v16i8(<16 x i8> %x, <16 x i8> %y) { 623; CHECK-NOBMI-LABEL: shl_s3_cmp_v16i8: 624; CHECK-NOBMI: # %bb.0: 625; CHECK-NOBMI-NEXT: pcmpeqb %xmm1, %xmm0 626; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 627; CHECK-NOBMI-NEXT: retq 628; 629; CHECK-BMI2-SSE2-LABEL: shl_s3_cmp_v16i8: 630; CHECK-BMI2-SSE2: # %bb.0: 631; CHECK-BMI2-SSE2-NEXT: pcmpeqb %xmm1, %xmm0 632; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 633; CHECK-BMI2-SSE2-NEXT: retq 634; 635; CHECK-AVX12-LABEL: shl_s3_cmp_v16i8: 636; CHECK-AVX12: # %bb.0: 637; CHECK-AVX12-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 638; CHECK-AVX12-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 639; CHECK-AVX12-NEXT: retq 640; 641; CHECK-AVX512-LABEL: shl_s3_cmp_v16i8: 642; CHECK-AVX512: # %bb.0: 643; CHECK-AVX512-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 644; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 645; CHECK-AVX512-NEXT: retq 646 %cmp = icmp eq <16 x i8> %x, %y 647 %ext = sext <16 x i1> %cmp to <16 x i8> 648 %shr = shl <16 x i8> %ext, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> 649 ret <16 x i8> %shr 650} 651 652define <4 x i64> @shl_s31_cmp_v4f64(<4 x double> %x, <4 x double> %y) { 653; CHECK-NOBMI-LABEL: shl_s31_cmp_v4f64: 654; CHECK-NOBMI: # %bb.0: 655; CHECK-NOBMI-NEXT: cmpeqpd %xmm3, %xmm1 656; CHECK-NOBMI-NEXT: cmpeqpd %xmm2, %xmm0 657; CHECK-NOBMI-NEXT: psllq $31, %xmm0 658; CHECK-NOBMI-NEXT: psllq $31, %xmm1 659; CHECK-NOBMI-NEXT: retq 660; 661; CHECK-BMI2-SSE2-LABEL: shl_s31_cmp_v4f64: 662; CHECK-BMI2-SSE2: # %bb.0: 663; CHECK-BMI2-SSE2-NEXT: cmpeqpd %xmm3, %xmm1 664; CHECK-BMI2-SSE2-NEXT: cmpeqpd %xmm2, %xmm0 665; CHECK-BMI2-SSE2-NEXT: psllq $31, %xmm0 666; CHECK-BMI2-SSE2-NEXT: psllq $31, %xmm1 667; CHECK-BMI2-SSE2-NEXT: retq 668; 669; CHECK-AVX1-LABEL: shl_s31_cmp_v4f64: 670; CHECK-AVX1: # %bb.0: 671; CHECK-AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 672; CHECK-AVX1-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 673; CHECK-AVX1-NEXT: retq 674; 675; CHECK-AVX2-LABEL: shl_s31_cmp_v4f64: 676; CHECK-AVX2: # %bb.0: 677; CHECK-AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 678; CHECK-AVX2-NEXT: vpsllq $31, %ymm0, %ymm0 679; CHECK-AVX2-NEXT: retq 680; 681; CHECK-AVX512-LABEL: shl_s31_cmp_v4f64: 682; CHECK-AVX512: # %bb.0: 683; CHECK-AVX512-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 684; CHECK-AVX512-NEXT: vpsllq $31, %ymm0, %ymm0 685; CHECK-AVX512-NEXT: retq 686 %cmp = fcmp oeq <4 x double> %x, %y 687 %ext = sext <4 x i1> %cmp to <4 x i64> 688 %shr = shl <4 x i64> %ext, <i64 31, i64 31, i64 31, i64 31> 689 ret <4 x i64> %shr 690} 691 692define <16 x i8> @shr_s1_cmp_v16i8(<16 x i8> %x, <16 x i8> %y) { 693; CHECK-NOBMI-LABEL: shr_s1_cmp_v16i8: 694; CHECK-NOBMI: # %bb.0: 695; CHECK-NOBMI-NEXT: pcmpeqb %xmm1, %xmm0 696; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 697; CHECK-NOBMI-NEXT: retq 698; 699; CHECK-BMI2-SSE2-LABEL: shr_s1_cmp_v16i8: 700; CHECK-BMI2-SSE2: # %bb.0: 701; CHECK-BMI2-SSE2-NEXT: pcmpeqb %xmm1, %xmm0 702; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 703; CHECK-BMI2-SSE2-NEXT: retq 704; 705; CHECK-AVX12-LABEL: shr_s1_cmp_v16i8: 706; CHECK-AVX12: # %bb.0: 707; CHECK-AVX12-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 708; CHECK-AVX12-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 709; CHECK-AVX12-NEXT: retq 710; 711; CHECK-AVX512-LABEL: shr_s1_cmp_v16i8: 712; CHECK-AVX512: # %bb.0: 713; CHECK-AVX512-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 714; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0 715; CHECK-AVX512-NEXT: retq 716 %cmp = icmp eq <16 x i8> %x, %y 717 %ext = sext <16 x i1> %cmp to <16 x i8> 718 %shr = lshr <16 x i8> %ext, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> 719 ret <16 x i8> %shr 720} 721 722define <8 x i32> @shr_s9_cmp_v8i32(<8 x i32> %x, <8 x i32> %y) { 723; CHECK-NOBMI-LABEL: shr_s9_cmp_v8i32: 724; CHECK-NOBMI: # %bb.0: 725; CHECK-NOBMI-NEXT: pcmpgtd %xmm3, %xmm1 726; CHECK-NOBMI-NEXT: pcmpgtd %xmm2, %xmm0 727; CHECK-NOBMI-NEXT: psrld $9, %xmm0 728; CHECK-NOBMI-NEXT: psrld $9, %xmm1 729; CHECK-NOBMI-NEXT: retq 730; 731; CHECK-BMI2-SSE2-LABEL: shr_s9_cmp_v8i32: 732; CHECK-BMI2-SSE2: # %bb.0: 733; CHECK-BMI2-SSE2-NEXT: pcmpgtd %xmm3, %xmm1 734; CHECK-BMI2-SSE2-NEXT: pcmpgtd %xmm2, %xmm0 735; CHECK-BMI2-SSE2-NEXT: psrld $9, %xmm0 736; CHECK-BMI2-SSE2-NEXT: psrld $9, %xmm1 737; CHECK-BMI2-SSE2-NEXT: retq 738; 739; CHECK-AVX1-LABEL: shr_s9_cmp_v8i32: 740; CHECK-AVX1: # %bb.0: 741; CHECK-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 742; CHECK-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 743; CHECK-AVX1-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2 744; CHECK-AVX1-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 745; CHECK-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 746; CHECK-AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 747; CHECK-AVX1-NEXT: retq 748; 749; CHECK-AVX2-LABEL: shr_s9_cmp_v8i32: 750; CHECK-AVX2: # %bb.0: 751; CHECK-AVX2-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 752; CHECK-AVX2-NEXT: vpsrld $9, %ymm0, %ymm0 753; CHECK-AVX2-NEXT: retq 754; 755; CHECK-AVX512-LABEL: shr_s9_cmp_v8i32: 756; CHECK-AVX512: # %bb.0: 757; CHECK-AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 758; CHECK-AVX512-NEXT: vpsrld $9, %ymm0, %ymm0 759; CHECK-AVX512-NEXT: retq 760 %cmp = icmp sgt <8 x i32> %x, %y 761 %ext = sext <8 x i1> %cmp to <8 x i32> 762 %shr = lshr <8 x i32> %ext, <i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9> 763 ret <8 x i32> %shr 764} 765 766define i1 @shr_to_shl_eq_i32_s5_fail_doesnt_add_up(i32 %x) { 767; CHECK-LABEL: shr_to_shl_eq_i32_s5_fail_doesnt_add_up: 768; CHECK: # %bb.0: 769; CHECK-NEXT: movl %edi, %eax 770; CHECK-NEXT: andl $7, %eax 771; CHECK-NEXT: shrl $5, %edi 772; CHECK-NEXT: cmpl %edi, %eax 773; CHECK-NEXT: sete %al 774; CHECK-NEXT: retq 775 %and = and i32 %x, 7 776 %sh = lshr i32 %x, 5 777 %r = icmp eq i32 %and, %sh 778 ret i1 %r 779} 780 781define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_add_up2(i32 %x) { 782; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_add_up2: 783; CHECK: # %bb.0: 784; CHECK-NEXT: movl %edi, %eax 785; CHECK-NEXT: andl $268435455, %eax # imm = 0xFFFFFFF 786; CHECK-NEXT: shrl $5, %edi 787; CHECK-NEXT: cmpl %edi, %eax 788; CHECK-NEXT: sete %al 789; CHECK-NEXT: retq 790 %and = and i32 %x, 268435455 791 %sh = lshr i32 %x, 5 792 %r = icmp eq i32 %and, %sh 793 ret i1 %r 794} 795 796define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_add_up3(i32 %x) { 797; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_add_up3: 798; CHECK: # %bb.0: 799; CHECK-NEXT: movl %edi, %eax 800; CHECK-NEXT: andl $67108863, %eax # imm = 0x3FFFFFF 801; CHECK-NEXT: shrl $5, %edi 802; CHECK-NEXT: cmpl %edi, %eax 803; CHECK-NEXT: sete %al 804; CHECK-NEXT: retq 805 %and = and i32 %x, 67108863 806 %sh = lshr i32 %x, 5 807 %r = icmp eq i32 %and, %sh 808 ret i1 %r 809} 810 811define i1 @shr_to_shl_eq_i8_s5_fail_doesnt_not_mask(i32 %x) { 812; CHECK-LABEL: shr_to_shl_eq_i8_s5_fail_doesnt_not_mask: 813; CHECK: # %bb.0: 814; CHECK-NEXT: movl %edi, %eax 815; CHECK-NEXT: andl $11, %eax 816; CHECK-NEXT: shrl $5, %edi 817; CHECK-NEXT: cmpl %edi, %eax 818; CHECK-NEXT: sete %al 819; CHECK-NEXT: retq 820 %and = and i32 %x, 11 821 %sh = lshr i32 %x, 5 822 %r = icmp eq i32 %and, %sh 823 ret i1 %r 824} 825 826define i1 @shl_to_shr_eq_i32_s9_fail_wrong_mask(i32 %x) { 827; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_wrong_mask: 828; CHECK: # %bb.0: 829; CHECK-NEXT: movl %edi, %eax 830; CHECK-NEXT: andl $511, %eax # imm = 0x1FF 831; CHECK-NEXT: shll $9, %edi 832; CHECK-NEXT: cmpl %edi, %eax 833; CHECK-NEXT: sete %al 834; CHECK-NEXT: retq 835 %and = and i32 %x, 511 836 %sh = shl i32 %x, 9 837 %r = icmp eq i32 %and, %sh 838 ret i1 %r 839} 840 841define i1 @shr_to_shl_eq_i32_s5_fail_wrong_mask(i32 %x) { 842; CHECK-LABEL: shr_to_shl_eq_i32_s5_fail_wrong_mask: 843; CHECK: # %bb.0: 844; CHECK-NEXT: movl %edi, %eax 845; CHECK-NEXT: andl $-32, %eax 846; CHECK-NEXT: shrl $5, %edi 847; CHECK-NEXT: cmpl %edi, %eax 848; CHECK-NEXT: sete %al 849; CHECK-NEXT: retq 850 %and = and i32 %x, -32 851 %sh = lshr i32 %x, 5 852 %r = icmp eq i32 %and, %sh 853 ret i1 %r 854} 855 856define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up(i32 %x) { 857; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up: 858; CHECK: # %bb.0: 859; CHECK-NEXT: movl %edi, %eax 860; CHECK-NEXT: andl $65024, %eax # imm = 0xFE00 861; CHECK-NEXT: shll $9, %edi 862; CHECK-NEXT: cmpl %edi, %eax 863; CHECK-NEXT: sete %al 864; CHECK-NEXT: retq 865 %and = and i32 %x, 65024 866 %sh = shl i32 %x, 9 867 %r = icmp eq i32 %and, %sh 868 ret i1 %r 869} 870 871define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up2(i32 %x) { 872; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up2: 873; CHECK: # %bb.0: 874; CHECK-NEXT: movl %edi, %eax 875; CHECK-NEXT: andl $-1024, %eax # imm = 0xFC00 876; CHECK-NEXT: shll $9, %edi 877; CHECK-NEXT: cmpl %edi, %eax 878; CHECK-NEXT: sete %al 879; CHECK-NEXT: retq 880 %and = and i32 %x, -1024 881 %sh = shl i32 %x, 9 882 %r = icmp eq i32 %and, %sh 883 ret i1 %r 884} 885 886define i1 @shl_to_shr_eq_i32_s9_fail_doesnt_add_up3(i32 %x) { 887; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_doesnt_add_up3: 888; CHECK: # %bb.0: 889; CHECK-NEXT: movl %edi, %eax 890; CHECK-NEXT: andl $-256, %eax 891; CHECK-NEXT: shll $9, %edi 892; CHECK-NEXT: cmpl %edi, %eax 893; CHECK-NEXT: sete %al 894; CHECK-NEXT: retq 895 %and = and i32 %x, -256 896 %sh = shl i32 %x, 9 897 %r = icmp eq i32 %and, %sh 898 ret i1 %r 899} 900 901define i1 @shl_to_shr_eq_i32_s9_fail_not_mask(i32 %x) { 902; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_not_mask: 903; CHECK: # %bb.0: 904; CHECK-NEXT: movl %edi, %eax 905; CHECK-NEXT: andl $-511, %eax # imm = 0xFE01 906; CHECK-NEXT: shll $9, %edi 907; CHECK-NEXT: cmpl %edi, %eax 908; CHECK-NEXT: sete %al 909; CHECK-NEXT: retq 910 %and = and i32 %x, -511 911 %sh = shl i32 %x, 9 912 %r = icmp eq i32 %and, %sh 913 ret i1 %r 914} 915 916define i1 @shl_to_shr_eq_i32_s9_fail_not_mask2(i32 %x) { 917; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_not_mask2: 918; CHECK: # %bb.0: 919; CHECK-NEXT: movl %edi, %eax 920; CHECK-NEXT: andl $-255, %eax 921; CHECK-NEXT: shll $9, %edi 922; CHECK-NEXT: cmpl %edi, %eax 923; CHECK-NEXT: sete %al 924; CHECK-NEXT: retq 925 %and = and i32 %x, -255 926 %sh = shl i32 %x, 9 927 %r = icmp eq i32 %and, %sh 928 ret i1 %r 929} 930 931define i1 @shl_to_shr_eq_i32_s9_fail_wrong_mask2(i32 %x) { 932; CHECK-LABEL: shl_to_shr_eq_i32_s9_fail_wrong_mask2: 933; CHECK: # %bb.0: 934; CHECK-NEXT: movl %edi, %eax 935; CHECK-NEXT: andl $8388607, %eax # imm = 0x7FFFFF 936; CHECK-NEXT: shll $9, %edi 937; CHECK-NEXT: cmpl %edi, %eax 938; CHECK-NEXT: sete %al 939; CHECK-NEXT: retq 940 %and = and i32 %x, 8388607 941 %sh = shl i32 %x, 9 942 %r = icmp eq i32 %and, %sh 943 ret i1 %r 944} 945 946define i1 @shl_to_shr_eq_i32_s9(i32 %x) { 947; CHECK-LABEL: shl_to_shr_eq_i32_s9: 948; CHECK: # %bb.0: 949; CHECK-NEXT: movl %edi, %eax 950; CHECK-NEXT: shrl $9, %eax 951; CHECK-NEXT: andl $8388607, %edi # imm = 0x7FFFFF 952; CHECK-NEXT: cmpl %eax, %edi 953; CHECK-NEXT: sete %al 954; CHECK-NEXT: retq 955 %and = and i32 %x, -512 956 %sh = shl i32 %x, 9 957 %r = icmp eq i32 %and, %sh 958 ret i1 %r 959} 960 961define i1 @shr_to_shl_eq_i32_s5(i32 %x) { 962; CHECK-LABEL: shr_to_shl_eq_i32_s5: 963; CHECK: # %bb.0: 964; CHECK-NEXT: movl %edi, %eax 965; CHECK-NEXT: shll $5, %eax 966; CHECK-NEXT: andl $-32, %edi 967; CHECK-NEXT: cmpl %eax, %edi 968; CHECK-NEXT: sete %al 969; CHECK-NEXT: retq 970 %and = and i32 %x, 134217727 971 %sh = lshr i32 %x, 5 972 %r = icmp eq i32 %and, %sh 973 ret i1 %r 974} 975 976define i1 @shr_to_rotate_eq_i32_s5(i32 %x) { 977; CHECK-NOBMI-LABEL: shr_to_rotate_eq_i32_s5: 978; CHECK-NOBMI: # %bb.0: 979; CHECK-NOBMI-NEXT: movl %edi, %eax 980; CHECK-NOBMI-NEXT: roll $4, %eax 981; CHECK-NOBMI-NEXT: cmpl %eax, %edi 982; CHECK-NOBMI-NEXT: sete %al 983; CHECK-NOBMI-NEXT: retq 984; 985; CHECK-BMI2-LABEL: shr_to_rotate_eq_i32_s5: 986; CHECK-BMI2: # %bb.0: 987; CHECK-BMI2-NEXT: rorxl $28, %edi, %eax 988; CHECK-BMI2-NEXT: cmpl %eax, %edi 989; CHECK-BMI2-NEXT: sete %al 990; CHECK-BMI2-NEXT: retq 991 %and = and i32 %x, 268435455 992 %sh = lshr i32 %x, 4 993 %r = icmp eq i32 %and, %sh 994 ret i1 %r 995} 996 997define i32 @issue108722(i32 %0) { 998; CHECK-NOBMI-LABEL: issue108722: 999; CHECK-NOBMI: # %bb.0: 1000; CHECK-NOBMI-NEXT: movl %edi, %ecx 1001; CHECK-NOBMI-NEXT: roll $24, %ecx 1002; CHECK-NOBMI-NEXT: xorl %eax, %eax 1003; CHECK-NOBMI-NEXT: cmpl %edi, %ecx 1004; CHECK-NOBMI-NEXT: sete %al 1005; CHECK-NOBMI-NEXT: retq 1006; 1007; CHECK-BMI2-LABEL: issue108722: 1008; CHECK-BMI2: # %bb.0: 1009; CHECK-BMI2-NEXT: rorxl $8, %edi, %ecx 1010; CHECK-BMI2-NEXT: xorl %eax, %eax 1011; CHECK-BMI2-NEXT: cmpl %edi, %ecx 1012; CHECK-BMI2-NEXT: sete %al 1013; CHECK-BMI2-NEXT: retq 1014 %2 = tail call i32 @llvm.fshl.i32(i32 %0, i32 %0, i32 24) 1015 %3 = icmp eq i32 %2, %0 1016 %4 = zext i1 %3 to i32 1017 ret i32 %4 1018} 1019 1020 1021;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: 1022; CHECK-AVX: {{.*}} 1023; CHECK-NOBMI-SSE2: {{.*}} 1024