xref: /llvm-project/llvm/test/CodeGen/X86/bug80500.ll (revision 2f448bf509432c1a19ec46ab8cbc7353c03c6280)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686 -mcpu=skylake | FileCheck %s
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4; Fix for a typo introduced by D80500
5
6define i32 @load_fold_udiv1(ptr %p) {
7; CHECK-LABEL: load_fold_udiv1:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
10; CHECK-NEXT:    movl $-2004318071, %edx # imm = 0x88888889
11; CHECK-NEXT:    mulxl (%eax), %eax, %eax
12; CHECK-NEXT:    shrl $3, %eax
13; CHECK-NEXT:    retl
14  %v = load i32, ptr %p, align 4
15  %ret = udiv i32 %v, 15
16  ret i32 %ret
17}
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