xref: /llvm-project/llvm/test/CodeGen/X86/bit-test-shift.ll (revision 298c0b352d5ed998c91328f5023fb192c688e1ed)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-- | FileCheck %s
3; <rdar://problem/8285015>
4
5define i32 @x(i32 %t) nounwind readnone ssp {
6; CHECK-LABEL: x:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
9; CHECK-NEXT:    shll $23, %eax
10; CHECK-NEXT:    sarl $31, %eax
11; CHECK-NEXT:    andl $-26, %eax
12; CHECK-NEXT:    retl
13entry:
14  %and = and i32 %t, 256
15  %tobool = icmp eq i32 %and, 0
16  %retval.0 = select i1 %tobool, i32 0, i32 -26
17  ret i32 %retval.0
18}
19