xref: /llvm-project/llvm/test/CodeGen/X86/avx-select.ll (revision 2b63077cfa13095b3e64f79fe825cc85ca9da7be)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
4
5define <8 x i32> @select00(i32 %a, <8 x i32> %b) nounwind {
6; X86-LABEL: select00:
7; X86:       # %bb.0:
8; X86-NEXT:    cmpl $255, {{[0-9]+}}(%esp)
9; X86-NEXT:    vxorps %xmm1, %xmm1, %xmm1
10; X86-NEXT:    je .LBB0_2
11; X86-NEXT:  # %bb.1:
12; X86-NEXT:    vmovaps %ymm0, %ymm1
13; X86-NEXT:  .LBB0_2:
14; X86-NEXT:    vxorps %ymm1, %ymm0, %ymm0
15; X86-NEXT:    retl
16;
17; X64-LABEL: select00:
18; X64:       # %bb.0:
19; X64-NEXT:    cmpl $255, %edi
20; X64-NEXT:    vxorps %xmm1, %xmm1, %xmm1
21; X64-NEXT:    je .LBB0_2
22; X64-NEXT:  # %bb.1:
23; X64-NEXT:    vmovaps %ymm0, %ymm1
24; X64-NEXT:  .LBB0_2:
25; X64-NEXT:    vxorps %ymm1, %ymm0, %ymm0
26; X64-NEXT:    retq
27  %cmpres = icmp eq i32 %a, 255
28  %selres = select i1 %cmpres, <8 x i32> zeroinitializer, <8 x i32> %b
29  %res = xor <8 x i32> %b, %selres
30  ret <8 x i32> %res
31}
32
33define <4 x i64> @select01(i32 %a, <4 x i64> %b) nounwind {
34; X86-LABEL: select01:
35; X86:       # %bb.0:
36; X86-NEXT:    cmpl $255, {{[0-9]+}}(%esp)
37; X86-NEXT:    vxorps %xmm1, %xmm1, %xmm1
38; X86-NEXT:    je .LBB1_2
39; X86-NEXT:  # %bb.1:
40; X86-NEXT:    vmovaps %ymm0, %ymm1
41; X86-NEXT:  .LBB1_2:
42; X86-NEXT:    vxorps %ymm1, %ymm0, %ymm0
43; X86-NEXT:    retl
44;
45; X64-LABEL: select01:
46; X64:       # %bb.0:
47; X64-NEXT:    cmpl $255, %edi
48; X64-NEXT:    vxorps %xmm1, %xmm1, %xmm1
49; X64-NEXT:    je .LBB1_2
50; X64-NEXT:  # %bb.1:
51; X64-NEXT:    vmovaps %ymm0, %ymm1
52; X64-NEXT:  .LBB1_2:
53; X64-NEXT:    vxorps %ymm1, %ymm0, %ymm0
54; X64-NEXT:    retq
55  %cmpres = icmp eq i32 %a, 255
56  %selres = select i1 %cmpres, <4 x i64> zeroinitializer, <4 x i64> %b
57  %res = xor <4 x i64> %b, %selres
58  ret <4 x i64> %res
59}
60
61; If a X86ISD::BLENDV node appears before legalization, constant fold using (mask < 0) instead of like a vselect (mask != 0).
62define void @fold_blendv_mask(<4 x i32> %a0) {
63; X86-LABEL: fold_blendv_mask:
64; X86:       # %bb.0: # %entry
65; X86-NEXT:    vmovaps {{.*#+}} ymm0 = [4294942349,7802,29242,15858,29361,4294951202,4294964216,4294941010]
66; X86-NEXT:    vmovaps %ymm0, (%eax)
67; X86-NEXT:    vzeroupper
68; X86-NEXT:    retl
69;
70; X64-LABEL: fold_blendv_mask:
71; X64:       # %bb.0: # %entry
72; X64-NEXT:    vmovaps {{.*#+}} ymm0 = [4294942349,7802,29242,15858,29361,4294951202,4294964216,4294941010]
73; X64-NEXT:    vmovaps %ymm0, (%rax)
74; X64-NEXT:    vzeroupper
75; X64-NEXT:    retq
76entry:
77  br label %head
78
79head:
80  %v0 = insertelement <4 x i32> %a0, i32 44158, i64 0
81  %v1 = insertelement <4 x i32> %v0, i32 54560, i64 1
82  %v2 = insertelement <4 x i32> %v1, i32 45291, i64 2
83  %v3 = insertelement <4 x i32> %v2, i32 18686, i64 3
84  %isneg = icmp slt <4 x i32> %v3, zeroinitializer
85  %or0 = select <4 x i1> %isneg, <4 x i32> <i32 26146, i32 -1257, i32 -2, i32 -3052>, <4 x i32> <i32 -24947, i32 7802, i32 29242, i32 15858>
86  %or1 = shufflevector <4 x i32> %or0, <4 x i32> <i32 29361, i32 -16094, i32 -3080, i32 -26286>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
87  br i1 poison, label %exit, label %head
88
89exit:
90  store <8 x i32> %or1, ptr addrspace(1) undef, align 32
91  ret void
92}
93