xref: /llvm-project/llvm/test/CodeGen/X86/atomic-or.ll (revision b33aeee3e3766191ba7ffe2f7b60016ba1fddff2)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs | FileCheck %s
3
4; rdar://9692967
5
6define void @t1(ptr %p, i32 %b) nounwind {
7; CHECK-LABEL: t1:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
10; CHECK-NEXT:    movl $2147483648, %eax # imm = 0x80000000
11; CHECK-NEXT:    lock orq %rax, (%rdi)
12; CHECK-NEXT:    retq
13entry:
14  %p.addr = alloca ptr, align 8
15  store ptr %p, ptr %p.addr, align 8
16  %tmp = load ptr, ptr %p.addr, align 8
17  %0 = atomicrmw or ptr %tmp, i64 2147483648 seq_cst
18  ret void
19}
20
21define void @t2(ptr %p, i32 %b) nounwind {
22; CHECK-LABEL: t2:
23; CHECK:       # %bb.0: # %entry
24; CHECK-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp)
25; CHECK-NEXT:    lock orq $2147483644, (%rdi) # imm = 0x7FFFFFFC
26; CHECK-NEXT:    retq
27entry:
28  %p.addr = alloca ptr, align 8
29  store ptr %p, ptr %p.addr, align 8
30  %tmp = load ptr, ptr %p.addr, align 8
31  %0 = atomicrmw or ptr %tmp, i64 2147483644 seq_cst
32  ret void
33}
34