xref: /llvm-project/llvm/test/CodeGen/X86/and-shift.ll (revision e9caa37e9c69f6a6e5ab59d33b9d492054819ded)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-unknown-unknown   | FileCheck %s --check-prefixes=X86
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64
4; RUN: llc < %s -mtriple=x86_64-unknown-gnux32 | FileCheck %s --check-prefixes=X64
5
6define i32 @shift30_and2_i32(i32 %x) {
7; X86-LABEL: shift30_and2_i32:
8; X86:       # %bb.0:
9; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
10; X86-NEXT:    shrl $30, %eax
11; X86-NEXT:    andl $-2, %eax
12; X86-NEXT:    retl
13;
14; X64-LABEL: shift30_and2_i32:
15; X64:       # %bb.0:
16; X64-NEXT:    movl %edi, %eax
17; X64-NEXT:    shrl $30, %eax
18; X64-NEXT:    andl $-2, %eax
19; X64-NEXT:    retq
20  %shr = lshr i32 %x, 30
21  %and = and i32 %shr, 2
22  ret i32 %and
23}
24
25define i64 @shift62_and2_i64(i64 %x) {
26; X86-LABEL: shift62_and2_i64:
27; X86:       # %bb.0:
28; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
29; X86-NEXT:    shrl $30, %eax
30; X86-NEXT:    andl $-2, %eax
31; X86-NEXT:    xorl %edx, %edx
32; X86-NEXT:    retl
33;
34; X64-LABEL: shift62_and2_i64:
35; X64:       # %bb.0:
36; X64-NEXT:    movq %rdi, %rax
37; X64-NEXT:    shrq $62, %rax
38; X64-NEXT:    andl $-2, %eax
39; X64-NEXT:    retq
40  %shr = lshr i64 %x, 62
41  %and = and i64 %shr, 2
42  ret i64 %and
43}
44
45define i64 @shift30_and2_i64(i64 %x) {
46; X86-LABEL: shift30_and2_i64:
47; X86:       # %bb.0:
48; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
49; X86-NEXT:    shrl $30, %eax
50; X86-NEXT:    andl $-2, %eax
51; X86-NEXT:    xorl %edx, %edx
52; X86-NEXT:    retl
53;
54; X64-LABEL: shift30_and2_i64:
55; X64:       # %bb.0:
56; X64-NEXT:    movq %rdi, %rax
57; X64-NEXT:    shrl $30, %eax
58; X64-NEXT:    andl $-2, %eax
59; X64-NEXT:    retq
60  %shr = lshr i64 %x, 30
61  %and = and i64 %shr, 2
62  ret i64 %and
63}
64