1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=x86_64-- -mcpu=generic < %s | FileCheck %s 3 4; Verify that the DAGCombiner doesn't wrongly remove the 'and' from the dag. 5 6define i8 @foo(ptr %V) { 7; CHECK-LABEL: foo: 8; CHECK: # %bb.0: 9; CHECK-NEXT: movzbl 2(%rdi), %eax 10; CHECK-NEXT: andb $95, %al 11; CHECK-NEXT: retq 12 %V3i8 = load <3 x i8>, ptr %V, align 4 13 %t0 = and <3 x i8> %V3i8, <i8 undef, i8 undef, i8 95> 14 %t1 = extractelement <3 x i8> %t0, i64 2 15 ret i8 %t1 16} 17 18