1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 3; rdar://7527734 4 5define i32 @test1(i32 %x) nounwind ssp { 6; CHECK-LABEL: test1: 7; CHECK: # %bb.0: 8; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 9; CHECK-NEXT: shll $5, %edi 10; CHECK-NEXT: leal 3(%rdi), %eax 11; CHECK-NEXT: retq 12 %t0 = shl i32 %x, 5 13 %t1 = or i32 %t0, 3 14 ret i32 %t1 15} 16 17; This test no longer requires or to be converted to 3 addr form because we are 18; are able to use a zero extend instead of an 'and' which gives the register 19; allocator freedom. 20define i64 @test2(i8 %A, i8 %B) nounwind { 21; CHECK-LABEL: test2: 22; CHECK: # %bb.0: 23; CHECK-NEXT: shll $4, %edi 24; CHECK-NEXT: andl $48, %edi 25; CHECK-NEXT: movzbl %sil, %eax 26; CHECK-NEXT: shrl $4, %eax 27; CHECK-NEXT: orl %edi, %eax 28; CHECK-NEXT: retq 29 %C = zext i8 %A to i64 30 %D = shl i64 %C, 4 31 %E = and i64 %D, 48 32 %F = zext i8 %B to i64 33 %G = lshr i64 %F, 4 34 %H = or i64 %G, %E 35 ret i64 %H 36} 37 38;; Test that OR is only emitted as LEA, not as ADD. 39 40; No reason to emit an add here, should be an or. 41define void @test3(i32 %x, ptr %P) nounwind readnone ssp { 42; CHECK-LABEL: test3: 43; CHECK: # %bb.0: 44; CHECK-NEXT: shll $5, %edi 45; CHECK-NEXT: orl $3, %edi 46; CHECK-NEXT: movl %edi, (%rsi) 47; CHECK-NEXT: retq 48 %t0 = shl i32 %x, 5 49 %t1 = or i32 %t0, 3 50 store i32 %t1, ptr %P 51 ret void 52} 53 54define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp { 55; CHECK-LABEL: test4: 56; CHECK: # %bb.0: 57; CHECK-NEXT: # kill: def $esi killed $esi def $rsi 58; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 59; CHECK-NEXT: andl $6, %edi 60; CHECK-NEXT: andl $16, %esi 61; CHECK-NEXT: leal (%rsi,%rdi), %eax 62; CHECK-NEXT: retq 63 %and = and i32 %a, 6 64 %and2 = and i32 %b, 16 65 %or = or i32 %and2, %and 66 ret i32 %or 67} 68 69define void @test5(i32 %a, i32 %b, ptr nocapture %P) nounwind ssp { 70; CHECK-LABEL: test5: 71; CHECK: # %bb.0: 72; CHECK-NEXT: andl $6, %edi 73; CHECK-NEXT: andl $16, %esi 74; CHECK-NEXT: orl %edi, %esi 75; CHECK-NEXT: movl %esi, (%rdx) 76; CHECK-NEXT: retq 77 %and = and i32 %a, 6 78 %and2 = and i32 %b, 16 79 %or = or i32 %and2, %and 80 store i32 %or, ptr %P, align 4 81 ret void 82} 83 84